Abstract: A method for optimizing provisioning workflows in cloud computing is provided. The method comprises determining a time coefficient for each resource type or aggregated resource types which define the installation time of a current workflow; accessing the current workflow and creating a tree topology based on the current workflow which defines serialized and parallelized provisioning steps; dividing the tree topology into independent sub-paths; determining a timing condition for an execution time of an optimized workflow; creating an optimized workflow template maintaining the timing condition by: selecting cheapest installation methods and cheapest resources; and reducing the parallelization of the tree topology; creating the optimized workflow by merging the optimized workflow template with data and the resource types of the current workflow.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance.

Abstract: Backwards compatible architecture for improving the arithmetic capability of existing processing blocks for relatively low cost is disclosed. The architecture includes a processing block on an integrated circuit device. The processing block includes a first, a second, and a third configurable multiplier and a configurable adder network. The processing block also includes a configurable interconnect within the processing block for routing signals between each of the multipliers and the adder network in accordance with a mode of operation. One or more of the processing blocks may be used to perform compute various calculations such as complex number multiplication and/or real number multiplication. The calculations may be performed on input values contain various numbers of bits, such as 36 bit numbers, 54 bit numbers, or 72 bit numbers.

Abstract: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract: Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

Abstract: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.

Abstract: Technologies pertaining to the automatic computation of transfer functions for a physical system are described herein. The physical system is one of an electrical system, a mechanical system, an electromechanical system, an electrochemical system, or an electromagnetic system. A netlist in the form of a matrix comprises data that is indicative of elements in the physical system, values for the elements in the physical system, and structure of the physical system. Transfer functions for the physical system are computed based upon the netlist.

Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.

Abstract: A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. The selector is coupled to the delay chain and the clock line and may select one of the clock signal and the skewed clock signal.

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.

Abstract: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: Embodiments of the invention provide a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.

Abstract: A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design parameters indicative of a plurality of loads of a multiple-load device; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components.

Abstract: A system and a method are disclosed for concurrently simulating multiple parameters of a design of an electrical circuit. A first simulation time and a first set of environmental parameters is determined and the design is simulated for the determined first simulation time. Multiple simulation engines, each analyzing on simulation parameter, simulate the design based on the first set of environmental parameters and the first set of environmental parameters are updated based on the results of each of the simulation engines. A determination is made whether the simulation results have converged. If the simulation results have not converged, each of the analysis engines simulated the design using the updated set of environmental parameters. If the simulation results are determined to be convergent, the simulation system determines a second simulation time and repeats the simulation process for the second simulation time.

Abstract: This application discloses a voltage analysis tool to perform a static power aware analysis on a circuit design without having to simulate the circuit design. The voltage analysis tool can determine a set of components in the circuit design corresponds to a design pattern representing a voltage-transition device, and set an output voltage for the set of components based, at least in part, on characteristics of the voltage-transition device. The voltage analysis tool can propagate the output voltage to other portions of the circuit design, and determine whether the portions of the circuit design receiving the output voltage have a rule violation.

Abstract: An environment and method are provided for designing and implementing a circuit comprising an integrated circuit (IC) including a number of parametric analog elements for which operating parameters can be set. Generally, the method comprises: specifying requirements for the circuit including physical properties to be sensed by the circuit and actions to be taken by the circuit; designing the circuit based on the specified requirements and resources available on the IC; and setting parameters of at least one of the parametric analog circuit elements of the IC based on the circuit design. In one embodiment, the specifying, designing, and setting parameters steps are performed using a computer executable code embodied in a computer readable medium on a server coupled to a client computer through an internet protocol network. Other embodiments are also provided.

Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting.

Abstract: A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.

Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.

Abstract: Techniques for emulating a logic block in an integrated circuit (IC) design are provided. The techniques include identifying a plurality of logic elements that are connectable to formal logic block. These logic elements are connected to perform logic functions associated with the logic block. The logic block may be a physical logic block on one IC design and a non-existent logic block on another IC design. The logic elements and associated connections form an emulated logic block.

Abstract: A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes. In some embodiments, multiple adjacent devices as identified as interface devices for purposes of the analysis. One situation where it may be useful to analyze a larger portion of the circuitry in this way where the analysis is being performed on a netlist having a power gate.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: A method for visually verifying an implementation of a design is described. The method includes integrating logical design data, physical design data, and physical implementation data into a common data format and graphically displaying the commonly formatted data to provide a visualization of the design, the visualization including a spatial context component associated with the physical implementation data.

Abstract: A method, apparatus and product for detecting corresponding paths in combinationally equivalent circuit designs. The method comprising: obtaining a first circuit design and a second circuit design, the first and second circuit designs have corresponding sets of input and output elements; obtaining a path in the first circuit design, the path commencing in an input element and ending in an output element, wherein the input element and the output element are connected by combinational logic elements; automatically extracting, by a computer, a sensitization function of the path in the first circuit design; and automatically determining, by the computer, one or more paths in the second circuit design which are sensitized by the sensitization function of the path.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode.

Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit.

Abstract: Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: Methods and circuits for optimizing performance and power consumption in a circuit design and circuit employing one or more lower threshold voltage (Lvt) cells or devices are described. A base supply voltage amplitude is determined for providing operating power for the circuit. The base supply voltage amplitude is a low or lowest voltage level that still satisfies a performance specification for the circuit. Providing a low or lowest base supply voltage level reduces or minimizes the standby (i.e., non-switching) power consumption in the Lvt device(s) since current leakage is reduced as the supply voltage level is reduced. Reducing the supply voltage level used to power the Lvt device(s) also reduces active power consumption for the circuit as well. Thus, total power consumption is optimized or reduced while still receiving the benefit of using Lvt devices to optimize or increase performance of a circuit layout and circuit.

Abstract: The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA2) corresponding to the analog block is produced in a native technology and a second integrated-circuit portion (BN2) corresponding to said digital block, is produced in a shrunk technological version associated with said native technology.

Abstract: An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a plurality of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.

Abstract: The present disclosure describes a memory block manager. In some aspects a request is transmitted to a model of an IP block at a randomized time and a response is received from the model of the IP block useful to characterize behavior of the IP block when fabricated. In other aspects a response to a request is transmitted to a model of an IP block at a randomized time and a communication is received from the model of the IP block useful to characterize behavior of the fabricated IP block when fabricated.

Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.

Abstract: A parameter setting circuit and method for an integrated circuit apply a pulse current to a pin of the integrated circuit during a programming mode of the integrated circuit, and then extract the difference between the voltage on the pin and the DC component of the voltage on the pin to determine a setting signal for parameter setting to an internal circuit of the integrated circuit. By this way, an input pin, an output pin or an input/output pin of the integrated circuit may be used as the pin implementing the parameter setting function.

Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.

Abstract: A design support apparatus includes a memory and a processor coupled to the memory. The processor executes a process including: for each of the plurality of first cells, selecting the second cell connected via the wire to the identified another first cell, the another first cell being included in the identified other first cells, when the identified another first cell is included in the identified other first cells; for each of the plurality of first cells, registering, in the first information, information that the first cell and the selected second cell are connected via the wire when the first cell and the selected second cell satisfy predetermined design rules; and copying the selected second cell, and registering, in the first information, information that the copied second cell and the first cell are connected via the wire when the predetermined design rules are not satisfied.

Abstract: Technology for translating a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the behavior, or other functionality, of multiple circuit portions, with at least some of the multiple circuit portions having multiple components. The technology includes determining components across the multiple circuit portions of the behavioral description that have commonalities, and synthesizing the structural description with a description of a shared circuit portion instead of individual structural descriptions of the components having the determined commonality. The synthesized structural description may be organized according to a different hierarchical structure than that of the behavioral description.

Abstract: Software method to identify presence of multiple digital drivers disposed in a manner that creates multiple conflicting current paths in complex electronic circuit designs. Digital drivers are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions that drive the digital driver's state. The previous level of predecessor circuit node states earlier in the circuit are checked to see if they simultaneously create pull up paths to power nets and pull down paths to ground nets, thus logically determining if a contention configuration is possible. This back-trace analysis is then repeated for the next previous level of predecessor circuit portions, further seeking logical contention issues within the expanding logic tree. This is continued until either no predecessor circuit portion that causes contention is found, or until a portion that does cause logical contention is found, in which case the contention digital drivers are reported.

Abstract: Disclosed is an improved method, system, and computer program product to perform automated generation and/or modification of control scripts for EDA tools. A script generator/modifier mechanism is used to access an optimization database to identify potential content of the control script. This potential content is then analyzed to identify the appropriate content to insert into the control script, to accomplish the intended goal of the user in operating the EDA tool. The script generator/modifier mechanism may itself be implemented in a script format.

Abstract: A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is created. In the degraded netlist, the first transistor is degraded by a device degradation for the first transistor. The second transistor is degraded by a device degradation for the second transistor. The circuit is re-simulated with the first degraded transistor and the second degraded transistor in place of the first MOS transistor.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: There is provided a mechanism of preferentially using a memory layer which suffers a small influence of heat of an SOC die, based on the positional relationship between the SOC die and the memory layer, and decreasing the refresh frequency of the DRAM and a leakage current. To accomplish this, an information processing apparatus allocates, in order to execute an accepted job, a memory area for executing the job preferentially from a memory physically farthest from the SOC die among a plurality of memories, and then executes the job.

Abstract: A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design by identifying rules for a first layer and for second layer(s) adjacent to the first layer, determining one or more sets of grids based on the rules, extending or implementing shapes to terminate at some grids of the one or more sets of grids, and populating the data of the ends of the shapes in the first layer in a data structure. The one or more sets of grids are in direction(s) perpendicular to the routing direction(s) of the first layer and have one or more grid pitches determined based at least in part upon routing pitch(es) of the second layer(s) and rule(s) for vias.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract: A system and method optimizes hardware description code generated from a graphical program or model automatically. The system may include a streaming optimizer, and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The streaming optimizer may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.