Strained Structure of a Semiconductor Device
A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.
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The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor device with a strained structure.
BACKGROUNDWhen a semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is scaled down through various technology nodes, a high-k gate dielectric layer and metal gate electrode layer are incorporated into the gate stack of the MOSFET to improve device performance with the decreased feature sizes. In addition, strained structures in source and drain (S/D) recess cavities of the MOSFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, it is difficult to achieve enhanced carrier mobility for a field-effect transistor (FET) because strained materials can not deliver a given amount of strain into channel region of the FET, thereby increasing the likelihood of device instability and/or device failure. As the gate length and spacing between devices decrease, these problems are exacerbated.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion.
It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to
Referring to
In some embodiments, the semiconductor substrate 202 comprises a P-active region 204p and an N-active region 204n separated by an isolation region 206. The active regions 204p, 204n may include various doping configurations depending on design requirements. For example, the P-active region 204p is doped with n-type dopants, such as phosphorus or arsenic; the N-active region 204n is doped with p-type dopants, such as boron or BF2. As such, the P-active region 204p may be usable for forming a p-type Field Effect Transistor (pFET) 200p, while the N-active region 204n may be usable for forming an n-type Field Effect Transistor (nFET) 200n. Thus, the semiconductor device 200 comprises both the pFET 200p and the nFET 200n.
Isolation regions 206 may be formed on the substrate 202 to isolate the various active regions 204p, 204n from each other. The isolation regions 206 may utilize isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI), to define and electrically isolate the various active regions 204p, 204n. In the present embodiment, the isolation regions 206 comprise an STI. The isolation regions 206 may comprise materials such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or combinations thereof. The isolation regions 206, and in the present embodiment, the STI, may be formed by any suitable process. As one example, the formation of the STI may include patterning the semiconductor substrate 202 by a photolithography process, etching a trench in the substrate 202 (for example, by using a dry etching, wet etching, and/or plasma etching process), and filling the trench (for example, by using a chemical vapor deposition process) with a dielectric material. In some embodiments, the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.
Still referring to
In one example, the gate dielectric layer 212 and gate electrode layer 214 are sequentially deposited over the substrate 202. In some embodiments, the gate dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric. High-k dielectrics comprise metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. In the present embodiment, the gate dielectric layer 212 is a high-k dielectric layer with a thickness in the range of about 10 to 30 angstroms. The gate dielectric layer 212 may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The gate dielectric layer 212 may further comprise an interfacial layer (not shown) to reduce damage between the gate dielectric layer 212 and the substrate 202. The interfacial layer may comprise silicon oxide.
In some embodiments, the gate electrode layer 214 may comprise a single layer or multilayer structure. In the present embodiment, the gate electrode layer 214 may comprise poly-silicon. Further, the gate electrode layer 214 may be doped poly-silicon with uniform or non-uniform doping. In some embodiments, the gate electrode layer 214 may include an N-work-function metal for the N-gate stack 210n. The N-work-function metal comprises Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. In some embodiments, the gate electrode layer 214 may include a P-work-function metal for the P-gate stack 210p. The P-work-function metal comprises TiN, WN, TaN, and Ru. In the present embodiment, the gate electrode layer 214 comprises a thickness in the range of about 30 nm to about 60 nm. The gate electrode layer 214 may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof.
Then, a layer of photoresist (not shown) is formed over the gate electrode layer 214 by a suitable process, such as spin-on coating, and patterned to form a patterned photoresist feature by a proper lithography patterning method. In at least one embodiment, a width of the patterned photoresist feature is in the range of about 5 to 45 nm. The patterned photoresist feature can then be transferred using a dry etching process to the underlying layers (i.e., the gate electrode layer 214 and the gate dielectric layer 212) to form the P-gate stack 210p and the N-gate stacks 210n. The photoresist layer may be stripped thereafter.
In another example, a hard mask layer 216 is formed over the gate electrode layer 214; a patterned photoresist layer (not shown) is formed on the hard mask layer 216; and the pattern of the photoresist layer is transferred to the hard mask layer 216 and then transferred to the gate electrode layer 214 and the gate dielectric layer 212 to form the P-gate stack 210p and the N-gate stack 210n. The hard mask layer 216 comprises silicon oxide. In some alternative embodiments, the hard mask layer 216 may comprise silicon nitride, silicon oxynitride, and/or other suitable dielectric materials, and may be formed using a method such as CVD or PVD. The hard mask layer 216 has a thickness in the range from about 100 to 800 angstroms. The photoresist layer may be stripped thereafter.
Still referring to
The process steps up to this point have provided the substrate 202 having the P-gate stack 210p over channel portion of the P-active region 204p and the N-gate stack 210n over channel portion of the N-active region 204n. Conventionally, portions of the N-active region (other than where the N-gate stack 210n and the pair of sidewall spacers 218n are formed thereover) are recessed to form N-source and drain (S/D) cavities in the N-active region 204n. Then an N-strained material is epi-grown in the N-S/D cavities to form N-S/D regions to strain or stress the channel region of the nFET 200n to enhance carrier mobility of the nFET 200n. Further, portions of the P-active region 204p (other than where the P-gate stack 210p and the pair of sidewall spacers 218p are formed thereover) are recessed to form P-source and drain (S/D) cavities in the P-active region 204p. Then a P-strained material is epi-grown in the P-SD cavities to form P-S/D regions to strain or stress the channel region of the pFET 200p to enhance carrier mobility of the pFET 200p. However, the strained material (i.e., the N-strained material or P-strained material) may not deliver a given amount of strain into channel region of the semiconductor device, resulting in an insufficient on-current of the semiconductor device.
Accordingly, the processing discussed below with reference to
For fabricating one embodiment of the strained structure 250 (shown in
In the depicted embodiment, a dummy dielectric layer comprising a material such as silicon oxide is formed over the substrate 202 by a CVD process, and patterned to form a dummy dielectric feature 220p by proper lithography and etch methods. The dummy dielectric feature 220p covers the P-active region 204p and exposes portions of the N-active region 204n (other than where the N-gate stack 210n and the pair of sidewall spacers 218n are formed thereover). Then, using the dummy dielectric feature 220p and the pair of sidewall spacers 218n as hard masks, a biased etching process is performed to recess the major surface 208s of the substrate 202 that are unprotected or exposed to form the N-S/D cavities 208n in the N-active region 204n. In one embodiment, the etching process may be performed using a chemical selected from NF3, CF4, and SF6 as an etching gas. In an alternative embodiment, the etching process may be performed using a solution comprising NH4OH and H2O2.
Referring to
In the depicted embodiment, a pre-cleaning process may be performed to clean the N-S/D cavities 208n with HF or other suitable solution. Then, the N-strained material 222n such as SiCP is selectively grown by an LPCVD process to fill the N-SD cavities 208n. In the depicted embodiment, the LPCVD process is performed at a temperature of about 400 to 800° C. and under a pressure of about 1 to 15 Torr, using SiH4, CH4, and H2 as reaction gases. Then the dummy dielectric feature 220p is removed using HF solution.
Referring to
Referring to
In the depicted embodiment, a pre-cleaning process may be performed to clean the P-S/D cavities 208p with HF or other suitable solution. Then, the P-strained material 222p such as silicon germanium (SiGe) is selectively grown by an LPCVD process to fill the P-S/D cavities 208p. In one embodiment, the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiH2Cl2, HCl, GeH4, B2H6, and H2 as reaction gases. Then the dummy dielectric feature 220n is removed using HF solution.
Referring to
Then, the structure depicted in
In the depicted embodiment, a first RTA process is applied to heat the substrate 202 at a temperature of about 230° C. to 260° C. The first metal layer 224 in contact with the strained materials 222 will form a high-resistance silicide. Then, the remaining un-reacted first metal layer 224 is removed using, for example, a solution comprising NH4OH, H2O2, and deionized water. In order to transform the high-resistance silicide to a low-resistance silicide, a second RTA process is applied to heat the substrate 202 at a temperature of about 650° C. to 750° C., thereby forming the first silicide regions 226.
Referring to
Subsequent CMOS processing steps applied to the semiconductor device 200 of
Referring to
Then, the structure depicted in
In the depicted embodiment, a third RTA process is applied to heat the substrate 202 at a temperature of about 230° C. to 260° C. The second metal layer 234 meeting the strained material 222 will form a high-resistance silicide. Then, the remaining un-reacted second metal layer 234 is removed using, for example, a solution comprising NH4OH, H2O2, and deionized water. In order to transform the high-resistance silicide to a low-resistance silicide, a fourth RTA process is applied to heat the substrate 202 at a temperature of about 650° C. to 750° C., thereby forming the second silicide regions 236. In the depicted embodiment, the second N-silicide regions 236n are on the remaining N-strained material 222n (referred to as N-strained regions 238n hereafter), while the second P-silicide regions 236p are on the remaining P-strained material 222p (referred to as P-strained regions 238p hereafter).
In some embodiments, the P-strained region 238p has a first top surface 238q higher than the major surface 202s. In some embodiments, a distance H1 between the first top surface 238q and the major surface 202s is in the range of about 5 to 15 nm.
In some embodiments, the N-strained region 238n has a second top surface 238m lower than the major surface 202s. In some embodiments, a distance H2 between the second top surface 238m and the major surface 202s is in the range of about 10 to 25 nm.
In some embodiments, the first N-silicide regions 226n and the second N-silicide regions 236n are combined and referred to as N-silicide regions 240n. As such, a volume of the N-silicide regions 240n is a summation of a volume of the first N-silicide regions 226n and a volume of the second N-silicide regions 236n, which is greater than each of the volume of the first N-silicide regions 226n and the volume of the second N-silicide regions 236n. In some embodiment, a maximum thickness t2 of the N-silicide region 240n is in the range of about 10 to 25 nm. In the depicted embodiment, the N-silicide regions 240n are on the N-strained region 238n. Further, the N-silicide regions 240n are used to strain or stress the channel region of the nFET 200n to enhance carrier mobility of the nFET 200n.
In some embodiments, the first P-silicide regions 226p and the second P-silicide regions 236p are combined and referred to as P-silicide regions 240p. As such, a volume of the P-silicide regions 240p is a summation of a volume of the first P-silicide regions 226p and a volume of the second P-silicide regions 236p, which is greater than each of the volume of the first P-silicide regions 226p and the volume of the second P-silicide regions 236p. In some embodiments, a maximum thickness t1 of the P-silicide region 240p is in the range of about 10 to 25 nm. It should be noted that the P-silicide regions 240p (with similar stress as the N-silicide regions 240n) will degrade carrier mobility of the pFET 200p if the P-silicide regions 240p strain or stress the channel region of the pFET 200p. In the depicted embodiment, the P-silicide regions 240p are on the P-strained regions 238p. Further, the P-silicide regions 240p is used to strain or stress the P-gate stack 210p to enhance work-function of the P-gate stack 210p. Thus, the P-silicide regions 240p are adjacent to the P-gate stack 210p, but far from the channel region of the pFET 200p.
In some embodiments, the P-silicide regions 240p and P-strained regions 238p are combined and referred to as a P-strained structure 250p. In some embodiments, the N-silicide regions 240n and N-strained regions 238n are combined and referred to as an N-strained structure 250n. In some embodiments, the P-strained structure 250p and N-strained structure 250n are combined and referred to as a strained structure 250.
Accordingly, Applicant's method may fabricate large-volume N-silicide regions 240n in the S/D regions of the nFET 200n of the semiconductor device 200, thereby delivering a given amount of strain into channel region of the semiconductor device 200. Further, Applicant's method may fabricate large-volume P-silicide regions 240p in the S/D regions of the pFET 200p of the semiconductor device 200, thereby delivering a given amount of strain into P-gate stack 210p of the semiconductor device 200. Problems associated with insufficient on-current of the semiconductor device 200 may be avoided, thereby enhancing the device performance.
It is understood that the semiconductor device 200 may undergo further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc.
In accordance with embodiments, a semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.
In accordance with another embodiments, a method for fabricating a semiconductor device comprises providing a substrate comprising a major surface; forming a cavity below the major surface; epi-growing a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; forming a first metal layer over the strained material; heating the first metal layer and the strained material to form a first silicide region; forming an interlayer dielectric (ILD) layer over the first silicide region and extending over the substrate; forming an opening in the ILD layer, wherein the opening is on the first silicide region; forming a second metal layer on the first silicide region in the opening; and heating the second metal layer and the strained material to form a second silicide region lower than the first silicide region.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. A semiconductor device, comprising:
- a substrate comprising a major surface;
- a p-type Field Effect Transistor (pFET) comprising:
- a P-gate stack over the major surface,
- a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and
- a P-silicide region on the P-strained region; and
- an n-type Field Effect Transistor (nFET) comprising:
- an N-gate stack over the major surface,
- an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and
- a N-silicide region on the N-strained region.
2. The semiconductor device of claim 1, wherein a distance between the first top surface and the major surface is in the range of about 5 to 15 nm.
3. The semiconductor device of claim 1, wherein a maximum thickness of the P-silicide region is in the range of about 10 to 25 nm.
4. The semiconductor device of claim 1, wherein the P-silicide region comprises titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or palladium silicide.
5. The semiconductor device of claim 1, wherein the P-strained region comprises SiGe or SiGe:B.
6. The semiconductor device of claim 1, wherein the P-gate stack comprises a P-work-function metal.
7. The semiconductor device of claim 6, wherein the P-work-function metal comprises TiN, WN, TaN, and Ru.
8. The semiconductor device of claim 1, wherein the P-gate stack comprises a gate dielectric, wherein the gate dielectric the gate dielectric comprises silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric.
9. The semiconductor device of claim 1, wherein a distance between the second top surface and the major surface is in the range of about 10 to 25 nm.
10. The semiconductor device of claim 1, wherein a maximum thickness of the N-silicide region is in the range of about 10 to 25 nm.
11. The semiconductor device of claim 1, wherein the N-silicide region comprises titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or palladium silicide.
12. The semiconductor device of claim 1, wherein the N-strained region comprises SiCP or SiP.
13. The semiconductor device of claim 1, wherein the N-gate stack comprises an N-work-function metal.
14. The semiconductor device of claim 13, wherein the N-work-function metal comprises Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
15. The semiconductor device of claim 1, wherein the N-gate stack comprises a gate dielectric, wherein the gate dielectric the gate dielectric comprises silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric.
16. A method for fabricating a semiconductor device, comprising:
- providing a substrate comprising a major surface;
- forming a cavity below the major surface;
- epi-growing a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;
- forming a first metal layer over the strained material;
- heating the first metal layer and the strained material to form a first silicide region;
- forming an interlayer dielectric (ILD) layer over the first silicide region and extending over the substrate;
- forming an opening in the ILD layer, wherein the opening is on the first silicide region;
- forming a second metal layer on the first silicide region in the opening; and
- heating the second metal layer and the strained material to form a second silicide region lower than the first silicide region.
17. The method of claim 16, wherein the step of heating the first metal layer and the strained material comprises
- heating the substrate at a temperature of about 230 to 260° C.;
- removing remaining first metal layer; and
- heating the substrate at a temperature of about 650 to 750° C.
18. The method of claim 16, wherein the step of heating the second metal layer and the strained material comprises:
- heating the substrate at a temperature of about 230 to 260° C.;
- removing remaining second metal layer; and
- heating the substrate at a temperature of about 650 to 750° C.
19. The method of claim 16, wherein the step of forming a first metal layer over the strained material is performed by a physical vapor deposition process.
20. The method of claim 16, wherein the cavity is adjacent to one side of a gate stack.
Type: Application
Filed: Aug 17, 2012
Publication Date: Feb 20, 2014
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Chung-Hsien Chen (Taipei), Ting-Chu Ko (Hsin-Chu), Chih-Hao Chang (Chu-Bei City), Chih-Sheng Chang (Hsin-Chu), Shou-Zen Chang (Panchiao City), Clement Hsingjen Wann (Carmel, NY)
Application Number: 13/588,860
International Classification: H01L 27/092 (20060101); H01L 21/20 (20060101);