INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION

Abstract

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid may have slots of a particular aspect ratio which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The lower sub-chamber plasma has a lower electron density, lower effective electron temperature, and higher negative ion:positive ion ratio as compared to the upper sub-chamber plasma. The disclosed embodiments may result in an etching process having good center to edge uniformity, selectivity, profile angle, and Iso/Dense loading.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Application No. 61/809,246, titled “INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION,” filed Apr. 5, 2013, which is herein incorporated by reference in its entirety and for all purposes.

BACKGROUND

One operation frequently employed in the production of semiconductors is an etching operation. In an etching operation, one or more materials are partly or wholly removed from a partially fabricated integrated circuit. Plasma etching is often used, especially where the geometries involved are small, high aspect ratios are used, or precise pattern transfer is needed.

Typically, a plasma contains electrons, as well as positive and negative ions, and some radicals. The radicals, positive ions, and negative ions interact with a substrate to etch features, surfaces and materials on the substrate. During the etching process, a chamber coil performs a function analogous to that of a primary coil in a transformer, while the plasma performs a function analogous to that of a secondary coil in the transformer.

With the move from planar to 3D transistor structures (e.g., FinFET gate structures for logic devices), plasma etching processes need to be increasingly precise and uniform in order to produce quality products. Among other factors, the plasma etch processes should have good selectivity, profile angle, Iso/Dense loading, and overall uniformity.

It is beneficial for an etching process to have good selectivity between the material that is etched and the material that is retained. In the context of the FinFET gate structure, this means that there should be good selectivity of the gate being etched to other exposed components such as a silicon nitride mask. The profile angle is measured as the angle between a recently etched (roughly vertical) sidewall and a horizontal plane. In many applications, the ideal profile angle is 90 degrees, producing a vertical etched opening. Sometimes, the local on-wafer feature density can affect the etching process. For example, an area of the wafer where features are dense may etch somewhat differently (e.g., etch more quickly, more slowly, more isotropically, more anisotropically, etc.) as compared to an area of the wafer where features are more isolated. The differences which arise due to variations in feature density are referred to as I/D loading. It is beneficial to minimize these differences during fabrication. In addition to meeting these and potentially other device-specific requirements, the etching process often needs to be consistently executed over the entire face of a substrate (e.g., the etch properties should be uniform from the center to the edge of a semiconductor wafer).

It has been found difficult to achieve multiple objectives such as those set forth above when etching advanced structures such as FinFET gates.

SUMMARY

Disclosed herein are various methods and apparatus for etching a semiconductor substrate and layers thereon during the manufacture of semiconductor devices. In one aspect of the embodiments herein, an apparatus for etching a feature on a substrate is provided. The apparatus may include a chamber defining an interior where a plasma can be provided; a substrate holder for holding a substrate in the chamber during etching; a plasma generator for producing a plasma within the chamber; and a grid dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder, where the upper sub-chamber has a height that is at least about ⅙ that of the lower sub-chamber, and where the grid includes a plurality of slots that extend substantially radially outwards that substantially prevent formation of induced current in the grid when the plasma is produced within the chamber.

The apparatus may also include a controller designed or configured to produce the plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber, where the effective electron temperature in the lower zone plasma is about 1 eV or less, and is less than the effective electron temperature in the upper zone plasma, and where the electron density in the lower zone plasma is about 5×10⁹ cm⁻³ or less, and is less than the electron density in the upper zone plasma. The controller may also be designed or configured to apply a bias to the grid and/or to the substrate holder. The controller may also be designed or configured to deliver an etchant gas to the chamber. In certain cases, the controller is designed or configured to provide a pressure of less than about 2000 mTorr in the chamber while the plasma etches the substrate. In certain cases, however, the controller is designed or configured to provide a lower pressure in the chamber during etching, such as a pressure less than about 200 mTorr. In other cases, the controller may be designed or configured to maintain a pressure in the reaction chamber between about 1-20 mTorr, or between about 5-20 mTorr. The controller may also be designed or configured to produce an ion-ion plasma in the lower sub-chamber.

In certain embodiments, the grid may have an average thickness of between about 1-50 mm, or between about 5-20 mm. The slots in the grid typically have an aspect ratio between about 0.3-5. In some embodiments the aspect ratio of the slots is between about 0.5-2, or between about 1-4. The slots are often arranged such that they extend radially outwards. Azimuthally adjacent slots are sometimes separated by at least about 15°. In these or other cases, azimuthally adjacent slots may be separated by no more than about 60°, for example by no more than about 50°.

The plasma generator in certain embodiments includes a coil disposed above a ceiling of the chamber. In some embodiments, the substrate holder is an electrostatic chuck. Various other elements may be included in the apparatus. For example, the apparatus may also include a process gas inlet. Furthermore, the apparatus may include a vacuum connection.

In a further aspect of the disclosed embodiments, a system is provided for processing semiconductor substrates. The system may include a vacuum transfer module; a robot in the vacuum transfer module; a plurality of stations attached to the vacuum transfer module; and a controller having a processor; where at least one of the plurality of stations includes a chamber defining an interior where a plasma can be provided; a substrate holder for holding the substrate in the chamber during etching; a plasma generator for producing a plasma within the chamber; and a grid dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder; where the upper sub-chamber has a height that is at least about ⅙ that of the lower sub-chamber; and where the grid includes a plurality of slots that extend substantially radially outwards that substantially prevent formation of induced current in the grid when the plasma is produced within the chamber.

In various embodiments, the stations are interfaced to facets in the vacuum transfer module. There may be a plurality of sensors in each facet.

In yet another aspect of the embodiments herein, a grid is disclosed for use in connection with a semiconductor etching apparatus, including a plate having a diameter that is substantially the same as the diameter of a standard semiconductor substrate for semiconductor device fabrication; and a plurality of slots that extend substantially radially outwards in the plate to substantially porevent formation of induced current in the plate when the plate is exposed to plasma; where the slots have an aspect ratio that is between about 0.3-5.

The grid, when placed in a processing chamber of a semiconductor etching apparatus, thereby dividing the processing chamber into an upper sub-chamber and a lower sub-chamber, and exposed to plasma generated in the upper sub-chamber, operates to maintain a lower electron density in the lower sub-chamber that is at least about 10 times lower than an upper electron density in the upper sub-chamber. In some embodiments, the grid may operate to maintain the lower electron density at least about 100 times lower than the upper electron density. In many cases the standard semiconductor substrate has a diameter of about 200, 300 or 450 mm. The azimuthally adjacent slots may be separated by at least about 10°. The azimuthally adjacent slots may also be separated by no more than about 60°. In some embodiments the grid is made of metal. In other cases, the grid is made of an insulative material. In certain cases the grid may include both metal and an insulative material.

In another aspect of the embodiments herein, a method is provided for etching a feature on a substrate, including providing the substrate to a substrate holder in a chamber with a plasma generator and a grid dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder, where the upper sub-chamber has a height that is at least about ⅙ that of the lower sub-chamber; generating a plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber; etching the feature in the substrate by interaction of the lower zone plasma with the substrate, where the effective electron temperature in the lower zone plasma is about 1 eV or less, and is less than the effective electron temperature in the upper zone plasma, and where the electron density in the lower zone plasma is about 5×10⁹ cm⁻³ or less, and is less than the electron density in the upper zone plasma.

In some cases, substantially no current is generated in the grid when generating the plasma. The method may also include applying a bias to the grid, and/or applying a bias to the substrate holder. In certain embodiments, the method also includes providing an etchant gas to the chamber. The etching may be performed at a chamber pressure of less than about 2000 mTorr, and in some cases the etching is performed at a chamber pressure between about 1-200 mTorr, or between about 1-20 mTorr, or between about 5-20 mTorr. The lower zone plasma may be an ion-ion plasma, as described herein.

These and other features will be described below with reference to the associated drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional diagram illustrating a plasma processing system utilized for etching operations in accordance with certain embodiments disclosed herein.

FIG. 2A is a simplified top-down view of a grid structure in accordance with certain embodiments disclosed herein.

FIG. 2B is a picture of a grid structure in accordance with certain embodiments herein.

FIGS. 3A-3C illustrate certain problems that arise due to etching byproduct dissociation.

FIG. 4 shows an embodiment of a multi-station cluster tool according to a disclosed embodiment.

FIGS. 5A-5B show SEM images of FinFET structures that have been etched according to a high pressure conventional technique (FIG. 5A) and according to an embodiment using a plasma grid (FIG. 5B).

FIGS. 6A-6B show SEM images of features etched according to a low pressure conventional technique (FIG. 6A) and according to a presently disclosed embodiment using a plasma grid (FIG. 6B).

FIG. 7 shows various SEM images of features that have been etched according to various regimes without the use of a plasma grid.

DETAILED DESCRIPTION

In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to devices on a semiconductor wafer during any of various stages of integrated circuit fabrication thereon. The following detailed description assumes the invention is implemented on a wafer. Exemplary work pieces (sometimes referred to as standard semiconductor substrates) include 200, 300 and 450 mm diameter semiconductor substrates. However, the invention is not so limited. The work piece may be of various shapes, sizes, and materials.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

Disclosed is an apparatus used in etching semiconductor substrates and layers formed thereon during the manufacture of semiconductor devices. The apparatus is defined by a chamber in which etching is performed. In certain embodiments, the chamber includes a planar window, a generally planar excitation coil, and a pedestal or chuck for holding the semiconductor substrate during etching. Of course, this disclosure is not limited to any particular type of plasma source. In addition to planar excitation coils, dome and plate plasma sources may be employed. Sources include inductively coupled plasma sources, capacitively coupled plasma sources, and others known to those of skill in the art. The embodiments herein utilize a grid positioned within the chamber that separates the chamber into two sub-chambers. During operation, each sub-chamber contains a plasma having distinct properties. Plasma is primarily or exclusively generated in the upper sub-chamber, and certain species are able to pass unaffected through the grid into the lower sub-chamber. The grid has slots, which penetrate the thickness of the grid. In certain implementations the slots extend roughly/substantially radially outward. As used herein, “extending substantially radially outwards” means that the feature being discussed has at least some radially directed component. In other words, the entire feature need not be overall radially directed, so long as a substantial part of the feature extends in a generally center-to-edge direction. Further, the “center-to-edge direction” is defined to include a range of angles around the true center-to-edge direction (e.g., within about 20° of the true center-to-edge direction).

The grid may contain multiple radial slots that penetrate the thickness of the grid. The grid and slots are designed such that only a small number of high energy electrons may pass through the grid, and the low energy electrons are effectively prevented from passing through due to the sheath surrounding the grid. The higher energy electrons generally become lower energy “colder” electrons upon passing through the grid and entering the lower sub-chamber. While high energy electrons may have sufficient energy to pass through the grid, many of them approach the grid at an angle at which they collide with the grid and lose energy. The high energy electrons that do make it through the grid do not have enough energy collectively to sustain the plasma underneath grid because they are now isolated from the excitation source. The mechanisms for the hot electrons to become cold in the lower chamber include collision with the grid, electron collisions with neutral species under the grid and removal of the excitation source from the electrons under the grid. Thus, the grid may have the function of producing a plasma in the lower sub-chamber having a low electron density (n_e) and low average effective electron temperature (T_e). Above the grid, the plasma is typically a conventional electron-ion plasma, in which a very large fraction of the negatively charged species are electrons. Below the grid, the plasma contains a much higher percentage of negative ions and in fact may be an ion-ion plasma. Certain characteristics of an ion-ion plasma are described below. Generally, as compared to the electron-ion plasma, the ion-ion plasma contains a significantly higher proportion of negatively charged species that are ions (rather than electrons).

Position of the Grid within the Reactor

The grid is positioned inside the plasma chamber, thereby separating the chamber into an upper sub-chamber and a lower sub-chamber. An example of a chamber suitable for modification to include a grid as described herein is a Kiyo Reactor from Lam Research Corporation of Fremont, Calif. For context, the following description may be considered with reference to FIG. 1, which is further described below. In certain implementations, the grid is positioned between about 1-6 inches above the interior base of the reaction chamber, or between about 1-6 inches (e.g., between about 1.5-3 inches) above a substrate supporter such as a pedestal. In these or other implementations, the grid may be positioned between about 1-6 inches (e.g., between about 1.5-3 inches) below the interior ceiling of the reaction chamber. The ceiling is often outfitted with a dielectric window.

In certain embodiments, the heights of the upper and lower sub-chambers are substantially the same (e.g., within about 5%), while in other embodiments these heights may differ more considerably. The ratio of the height of the upper chamber to the height of the lower chamber (h_u/h₁), also referred to as the sub-chamber height ratio, may be between about 0.1-10, or between about 0.2-5. In some embodiments, the sub-chamber height ratio is greater than about ⅙.

The grid should not be positioned too close to the wafer, as this may cause printing of the grid to occur on the wafer's face. In other words, the pattern of slots in the grid may undesirably appear on the face of the wafer after processing, causing severe etch non-uniformity on the substrate surface. For many applications, a separation distance of at least about 1 inch from the top of the substrate to the grid is sufficient.

The Grid Design

The grid is a relatively thin sheet having slots. Additionally, in some embodiments, the grid may include holes or perforations of other shapes. Thus, the grid includes holes and slots in combination. Non-limiting examples of grid structures are shown in FIGS. 2A-2B. The material contained in the grid may be an insulator, conductor, or some combination thereof. In certain implementations, the grid contains one or more materials including, but not limited to, metals, metallic alloys such as stainless steel, aluminum, titanium, ceramic, silicon, silicon carbide, silicon nitride, and a combination thereof. The material may or may not be anodized or otherwise passivated for, e.g., corrosion resistance. In some cases, the grid may include an insulative material such as ceramic, glass, robust polymer able to withstand harsh plasma environments, or a composite of any of these materials. In one embodiment, the grid is made from a metallic material having a ceramic coating. Other coatings may also be used. The use of a coated grid is especially beneficial where the layers being etched are volatile. In certain implementations, a grid may be coated with a pure coating including, but not limited to, coatings of Y₂O₃, YF₃, YAG, titanium nitride, or CeO₂, for example. Further, the grid may be grounded, floating or biased. In some implementations, a grounded grid acts as an enhanced bias current return for the cathode.

The grid generally spans an entire horizontal cross-section of the chamber when it is grounded. When the grid is biased, a spacing of about 5 cm or greater may be maintained between the grid and nearest grounded surface. Where the chamber is circular (as viewed from above), the grid will also be circular. This allows the grid to effectively divide the reaction chamber into two sub-chambers. In certain designs, the circular shape of the grid is defined by to the geometry of the substrate, which is typically a circular wafer. As is well known, wafers typically are provided in various sizes, such as 200 mm, 300 mm, 450 mm, etc. Other shapes are possible for square type substrates or smaller substrates, depending on the etching operations performed within chamber. The cross-section of the grid may have a variety of shapes. A flat planar grid cross-section is appropriate for some embodiments. However, dished, domed, oscillating (e.g., sinusoidal, square wave, chevron shapes), slanted, etc. grid cross-sections are appropriate in other embodiments. The slots or holes through any of these cross-sectional profiles will have characteristics (including aspect ratios) as described elsewhere herein.

The grid may on average be between about 1-50 mm thick, preferably between about 5-20 mm thick. If the grid is too thick, it may not function correctly (e.g., it may block too many species from getting through, have too much mass, take up too much space in the reaction chamber, etc.). If the grid is too thin, it may not be able to withstand the plasma processing, and may need to be replaced fairly often. The thickness of the grid is also limited by the desired aspect ratio of the slots in the grid, as the height of the slots is determined by the grid thickness, as described below.

In some embodiments, the grid functions as a separator between an upstream and a downstream plasma, where the downstream plasma exists in the lower sub-chamber and may be radical rich. In this manner, a plasma chamber outfitted with a grid may produce a result similar to that accomplished with existing remote plasma tools such as the GAMMA™ platform tools available from Novellus Systems, now Lam Research Corporation of Fremont, Calif. When operated for this purpose, the grid may be relatively thick, e.g., about 20-50 mm thick.

In certain embodiments, the grid includes slots that in a typical embodiment have a long, thin shape. The slots extend radially outwards from the center of the grid. The slots have a height, width and thickness (the width and length are explicitly labeled in FIG. 2A). The slot height is measured along an axis perpendicular to the face of the grid, and this height is generally equal to the thickness of the grid. The width of the slots may be variable or constant over the radial extent of the slots. In certain cases, the slots may be pie-shaped (i.e., thinner towards the center and thicker towards the edge of the grid). In various embodiments, the slots extend length-wise outwards from the center of the grid (i.e., radially). In some embodiments, the slot widths are no greater than about 25 mm. The length of the slots may be variable or constant around the azimuthal extent of the grid. The angular separation of the radial slots may be variable or constant around the grid.

If no slots were present in the grid, a current would be induced in the grid during plasma generation. This current would flow substantially circularly around the grid or would form local eddy currents, and would result in increased power consumption. However, the presence of the slots prevents such parasitic current from forming, thereby saving power and resulting in a more efficient process. Openings having shapes such as substantially circular holes would be less effective in preventing this current from forming. However, as mentioned above, circular openings may be used in conjunction with slotted openings.

The aspect ratio of a slot is defined as the ratio of the slot's height to its width (h/w). Typically, the geometry of this aspect ratio will be viewable as a cross-section taken perpendicular to the lengthwise direction of the slot (often radial). Because the width of the slots may be variable, the aspect ratio may be similarly variable. In certain embodiments, the aspect ratio of the slots is between about 0.3-5, or between about 1-4, or between about 0.5-2. In many embodiments, grids having these aspect ratios reduce the electron density and effective electron temperature in the lower sub-chamber, as compared to the upper sub-chamber. As mentioned, it is believed that the effective electron temperature is reduced as electrons pass through the slots at least in part because a number of hot electrons are colliding with the grid. Further, the effective electron temperature in the lower sub-chamber is reduced compared to the upper sub-chamber because the electrons in the lower sub-chamber are shielded by the grid and therefore are not subject to inductive heating from the plasma coils (or other plasma source).

When holes are employed together with slots, the holes may serve the same purposes as the slots. Therefore they will generally have aspect ratios as set forth above. In some embodiments, the holes have a diameter in the range of about 0.05 inches to about 0.2 inches. They penetrate the full thickness of the grid.

An additional benefit provided by the grid is that it may neutralize convective flow effects from the main injector. This allows for a more uniform gas flow onto the face of the wafer. The presence of a grid between the wafer and the gas injector(s) in the upper chamber can significantly reduce the convective impact of any gas delivered out of the gas injector(s) because the grid will disrupt the gas flow and result in a more diffusive flow regime over the wafer.

In some embodiments, the grid contains gas delivery holes. In such embodiments, the grid may serve the additional purpose of being a showerhead for the upper and/or lower sub-chambers. In these embodiments, one or more channels may be included in one or more grids. These channels may be fed with gas from an inlet (or multiple inlets), and deliver the gas to a plurality of outlet holes in the grid(s). The outlet holes may form gas distribution showerheads that deliver process gasses to either or both of the upper and lower sub-chambers.

In some implementations, the grid has a region such as a central region containing a feature for allowing a probing apparatus to be disposed through the grid. The probing apparatus can be provided to probe process parameters associated with the plasma processing system during operation. Probing processes can include optical emission endpoint detection, interferometeric endpoint detection, plasma density measurements, ion density measurements, and other metric probing operations. In certain embodiments, the central region of the grid is open. In other embodiments, the central region of the grid contains an optically clear material (e.g., quartz, sapphire, etc.) to allow light to be transmitted through the grid.

In certain embodiments, it may be preferable to have a slot in the grid about every 15 mm to 40 mm near the outer edge of the grid for a 300 mm wafer etcher. This corresponds to azimuthally adjacent slots being separated by about 18°, or about 48°, respectively. As such, in certain embodiments, azimuthally adjacent slots are separated by at least about 10°, or at least about 15°. In these or other embodiments, azimuthally adjacent slots are separated by no more than about 40°, or no more than about 50°, or no more than about 60°.

In various embodiments, the grid does not play a substantial role in plasma formation. However, the grid may play a role in confining the electron-ion plasma to the upper sub-chamber and filtering out species for delivery to the lower sub-chamber.

Plasma Properties

The grid effectively divides the plasma chamber into two zones: an upper zone proximate the coils (or other plasma generation mechanism) for generating the plasma and a lower zone proximate the substrate holder. In various embodiments, the plasma in the upper zone contains relatively “hot,” high-energy electrons. Often, this plasma is characterized as an electron-ion plasma. In various embodiments, the plasma in the lower zone contains relatively “cold,” low-energy electrons. Often, this lower zone plasma is characterized as an ion-ion plasma.

Plasma may be generated primarily or exclusively in the upper sub-chamber. In one embodiment, an inductively coupled plasma is generated in the upper sub-chamber by running current through coils located above the upper sub-chamber. A single coil or multiple coils may be employed. In other embodiments, a capacitively coupled plasma is generated, e.g., using a VHF CCP source. The plasma in the upper sub-chamber will have distinctly different characteristics from the plasma in the lower sub-chamber due to the presence of the grid.

In many embodiments, the upper zone plasma is a conventional electron-ion plasma. In this type of plasma, most of the positively charged species are positive ions and most of the negatively charged species are electrons. Although negative ions exist, they are present only in relatively low concentrations. In contrast, the plasma in the lower sub-chamber is often an ion-ion plasma. As compared to the electron-ion plasma, the ion-ion plasma has a greater proportion of negatively charged species that are negative ions, and a lower proportion of negatively charged species that are electrons. In certain implementations, the ratio of the concentration of positive ions to the concentration of electrons (sometimes referred to as the positive ion to electron ratio, n_i/n_e) in the ion-ion plasma is about 2 or greater, and in some cases is about 5 or greater, or even about 10 or greater. In certain cases, the positive ion to electron ratio is at least about 2 times greater (e.g., at least 5 times greater) in the lower plasma than in the upper plasma.

A related difference between the two plasmas is that the upper zone plasma has a significantly higher electron density. For example, the electron density in the lower zone plasma may be about 5×10⁹ cm⁻³ or less (e.g., about 1×10⁹ cm⁻³ or less). These ranges are particularly applicable to electron negative processing gases. The upper zone plasma may have an electron density that is at least about 10 times greater (e.g., at least about 100 times greater, or at least about 1000 times greater) than that of the lower zone plasma. In some cases, the lower sub-chamber has an ion-ion plasma where electron density is at least an order of magnitude smaller than the negative ion density and positive ion density. In a particular lower sub-chamber plasma example, the density of electrons (Ne) is about 10⁸ cm⁻³, the density of positive ions (Ni+) is about 10⁹ cm⁻³, and the density of negative ions (Ni−) is about 10⁹ cm⁻³.

An additional difference between the upper and lower zone plasmas is that the lower zone plasma will typically have a higher ratio of negative ions to positive ions. Because the upper zone electron-ion plasma typically contains primarily positive ions and electrons, with relatively few negative ions, the negative ion:positive ion ratio will be low. The negative ion:positive ion ratio in the lower zone plasma may be between about 0.5-1 (e.g., between about 0.8-0.95).

One possible non-limiting explanation for relatively low concentration of electrons in the lower zone plasma is that the electrons present in the lower zone (e.g., the electrons passing from the upper zone to the lower zone through the grid) are generally not heated by RF fields and quickly lose energy due to inelastic collisions with gas molecules, resulting in low effective electron temperature. These low energy electrons are more likely (as compared to the high energy electrons in the upper zone plasma) to interact with a neutral species to produce negative ions. Electrons must have a relatively low energy to attach to neutrals and form negative ions. This negative ion production will not occur with high energy electrons, which may “kick off” another electron when colliding with the neutral species instead of combining to form a negative ion.

As indicated, the effective electron temperature is greater in the upper zone plasma as compared to the lower zone plasma. Electrons may be cooled as they pass through the slots in the grid. Typically, the effective electron temperature in the lower zone plasma is about 1 eV or less. In certain cases, the effective electron temperature in the lower zone plasma may be between about 0.1-1 eV (e.g., between about 0.2-0.9 eV). The effective electron temperature may be at least about two times greater (e.g., at least about three times greater) in the upper zone plasma than in the lower zone plasma, as measured in electron volts. In a particular implementation, the upper zone plasma has an effective electron temperature of about 2.5 eV and the lower zone plasma has an effective electron temperature of about 0.8 eV. In various embodiments, this difference in the effective electron temperature arises wholly or partially from the presence of the grid.

Without being limited to any specific theory or mechanism, the role of the grid may be explained as follows. The grid may partially shield the lower sub-chamber such that the charged species therein are not directly exposed to power from the plasma coils. Additionally, the particular aspect ratios of the slots in the grid cause a fraction of the high energy electrons to collide with the grid when passing through the slots. This produces two qualitatively different plasmas in the two plasma zones.

Another distinguishing characteristic of the upper and lower zone plasmas is their plasma potentials. The plasma potential in the upper chamber is generally higher than in the lower chamber. For example, the plasma potential in the upper plasma may be between about 8-35 V (e.g., between about 10-20 V), while the plasma potential in the lower plasma may be between about 0.4-10 V (e.g., between about 0.5-3 V). This difference in plasma potential may occur because the electron energy is lower in the lower sub-chamber, so the lower zone plasma does not need to be as positive to prevent electrons from leaving it.

Further, the two plasmas will typically have different energy distribution functions (e.g., ion energy distribution function and electron energy distribution function). Both the electron and ion energy distribution functions will be narrower in the lower plasma and broader in the upper plasma. By using the grid, it is possible to achieve a very narrow ion energy distribution function without using sophisticated control with a waveform generator. For example, the ion energy distribution function for the lower plasma might have a full width half maximum of only about 5 V. As a consequence, negative current can be drawn from negative ions, which arrive at the substrate surface to maintain electro-neutrality (instead of electrons serving this purpose). This provides a unique etching mechanism.

The radical concentration in the lower zone plasma may range between about 1% of total neutral density to about 70% of the total neutral density, or between about 10% to about 70% of the total neutral density, or between about 10% to about 50% of the total neutral density.

The chamber pressure during the etch operation may be below about 2000 mTorr, such as between about 1-2000 mTorr (e.g., between about 2-200 mTorr). In one particular example, the chamber pressure is maintained at or below about 20 mTorr. These pressures are particularly useful when employed with a lower zone plasma having an effective electron temperature of about 0.5 eV or lower and/or an electron density of about 5×10⁸ cm⁻³ or lower. These pressures are also particularly useful when employed with a lower zone ion-ion plasma.

Ion-ion plasmas are believed to provide certain benefits for semiconductor processing. For example, partially fabricated semiconductor devices etched in an ion-ion plasma show very good selectivity, profile angle, Iso/Dense (I/D) loading, and overall uniformity across the face of the substrate being etched. Previous techniques could not simultaneously achieve all of these benefits (i.e., process designers had to choose between, for example, achieving good overall etch uniformity and the other benefits). Thus, the embodiments herein represent a significant advancement in etching methodology.

FIGS. 3A-3C illustrate the effect of the breakdown of etching byproducts on a feature being etched. To begin, FIG. 3A shows a substrate having three layers deposited thereon. The bottom layer 303 represents a gate oxide, the middle layer 305 represents polysilicon, and the top layer 307 (shown as three separate blocks) represents a hard mask. It is believed that in a conventional etching process, the plasma present in the chamber acts, in part, to dissociate etching byproducts 310, as shown in FIG. 3B. The mechanism may include ion-assisted chemical etching, represented in part by positive ion 309. These byproducts 310 are often volatile components (e.g., SiBr₄), which under the right conditions are swept away from the substrate. However, when a high effective electron temperature plasma, which is typical of an electron-ion plasma, contacts with the wafer, high energy electrons in the plasma can react with the volatile byproducts 310 to cause them to dissociate into physico-chemically “sticky” dissociation products 312 (e.g., SiBr₂). These dissociation products 312 may adhere to the substrate as shown in FIG. 3B, often to a sidewall of a feature being etched, and cause the etch process to occur in a non-vertical or otherwise undesirable manner, as shown in FIG. 3C. This dissociation product adherence/redeposition leads to local loading effects resulting in a non-vertical etch.

The use of a grid to reduce the effective electron temperature of the plasma proximate the substrate being etched reduces these undesirable effects. The grid may result in the production of an ion-ion plasma, with its correspondingly reduced electron density and effective electron temperature, thereby reducing these undesirable effects. Because ions generally have significantly less energy than electrons, the ions in the present embodiments' ion-ion plasma do not cause this byproduct dissociation. Although the present embodiments may produce an electron-ion plasma, this high electron density/high effective electron temperature plasma may be confined to the upper sub-chamber. Therefore, etch byproducts tend to contact only the lower zone plasma, and do not come into contact with the high effective electron temperature, upper zone plasma. Further, although there will be some electrons present in the ion-ion plasma, these electrons generally have a low T_e and therefore will not typically have enough energy to cause the byproduct dissociation. As such, the etch byproducts are not dissociated into “sticky” problem-causing compounds.

Wafer Biasing

In certain implementations, the wafer is biased during processing. This is accomplished by applying a bias to the electrostatic chuck used to hold/support the wafer. Because the wafer is exposed to a lower T_e, low electron density plasma (such as an ion-ion plasma) in the lower sub-chamber, bias may be applied to the chuck in a way that captures/encourages the unique benefits of the ion-ion plasma. Further, the bias may be applied in a manner that avoids the formation of an electron-ion plasma in the lower sub-chamber. For example, the bias may have a frequency and power appropriate to prevent formation of an electron-ion plasma where an ion-ion plasma would be formed without the power contributed by the chuck bias. For example, the RF bias may have a frequency below about 20 MHz, preferably between about 100 kHz to about 13.56 MHz, to reduce the amount of electron heating generated by the application of bias power to the substrate. In some embodiments, the bias (regardless of frequency) is pulsed in the range of about 1 Hz to about 10 kHz with a duty cycle of between about 1% and 99%.

In conventional electron-ion plasmas, the plasma potential is fairly high and positive, as described above. This plasma potential effectively limits the ability of the electrons to escape from the plasma. However, the lower zone plasma typically has an unconventionally low electron density and effective electron temperature and therefore only requires a much lower plasma potential to effectively confine its electrons. The low plasma potential opens the operating window, optionally allowing negative ions present in the ion-ion plasma to accelerate towards and strike the wafer during a bias waveform's positive cycle. This etching regime was previously unobtainable in continuous wave plasmas.

The frequency of the bias applied to the electrostatic chuck may be designed to optimize the formation and attraction of ions (particularly but not exclusively negative ions) in an ion-ion plasma.

The power level of the bias applied to the electrostatic chuck may be designed to prevent formation of an electron-ion plasma in the lower sub-chamber. In some embodiments, the power supplied to bias the chuck is between about 3-300 W, for example between about 5-150 W. This may correspond to a bias voltage between about 0-500 V.

In certain embodiments, the frequency of the bias applied to the electrostatic chuck is between about 0.1-15 MHz (e.g., between about 400 kHz-13.56 MHz). In a particular example, the bias is about 8 MHz. This frequency may be particularly useful, as it corresponds to the ion transport frequency. Other frequencies may also be used, but are likely to be less effective. For example, frequencies between about 100 kHz-1 MHz may work to some extent, but will be less effective than the higher frequencies cited above. Another consideration regarding the bias applied to the chuck/wafer is that if the frequency of the bias is too high, the bias may act to form an electron-ion plasma in the lower sub-chamber. In order to avoid this condition, the frequency of the bias applied to the electrostatic chuck should be less than about 30 MHz. In certain embodiments, the frequency of the bias is between about 100 kHz and 13 MHz.

It should be noted that where a grid is used and an AC bias of appropriate frequency is applied to the electrostatic chuck/wafer, the plasma sheath over the wafer can operate to alternately pull negative ions and positive ions out of the plasma and accelerate them towards the face of the wafer. In other words, the plasma sheath will attract negative ions in a positive cycle and then positive ions in a negative cycle, and these cycles repeat with the AC bias. As explained above, this negative ion attraction (to the wafer) was not possible before implementation of the present embodiments because the plasma potential was too high, thereby drowning out any attractive effect from the relevant half of the AC bias cycles.

As mentioned, the bias may be applied in pulses. However, pulsing is not needed for many cases. The present embodiments achieve a stable ion-ion plasma above the wafer during the entire etching process. As such, the bias on the chuck/wafer does not need to be pulsed to achieve the benefits described herein. However, in certain embodiments, the bias may nevertheless be applied in pulses, for example to reduce the etch rate or the amount of ion bombardment of the substrate to thereby increase the selectivity of the etch to the under-layer. Bias pulsing in ion-ion plasmas can be particularly beneficial by enhancing selectivity when alternating between ions and radicals. In other words, pulsing may partition the flux of ions and radicals to the substrate surface (pulse on: radicals+ions; pulse off: radicals only).

Process/Applications

The apparatus and plasma conditions disclosed herein may be used to etch any of a variety materials such as silicon (including polycrystalline, amorphous, single crystal, and/or microcrystalline silicon), metals (including but not limited to TiN, W, TaN, etc), oxides and nitrides (including but not limited to SiO, SiOC, SiN, SiON, etc.), organics (including but not limited to photoresists, amorphous carbon, etc), and a variety of other materials including, but not limited to, W, Pt, Ir, PtMn, PdCo, Co, CoFeB, CoFe, NiFe, W, Ag, Cu, Mo, TaSn, Ge₂Sb₂Te₂, InSbTe Ag—Ge—S, Cu—Te—S, IrMn, and/or Ru. The concept can be extended to materials like NiO_x, SrTiO_x, perovskite (CaTiO₃), PrCAMnO₃, PZT (PbZr_1-xTi_xO₃), (SrBiTa)O₃, and the like. The apparatus can be used with any gas combination that is available in a present day fabrication facility (including HBr, CO, NH₃, CH₃OH, and the like).

The apparatus and plasma conditions disclosed herein may be employed to etch features in devices or other structures at any technology node. In some embodiments, the etch is used during fabrication of in the 20-10 nm nodes or beyond. Etching can occur before both front end of line fabrication procedures and back end of line fabrication procedures. The etching may provide superior vertical profile, material selectivity, I/D loading, and/or wafer center to edge uniformity of better than about 2%. A few examples of suitable etch applications include shallow trench isolation, gate etch, spacer etch, source/drain recess etch, oxide recess, and hard-mask open etch.

Apparatus

The methods described herein may be performed by any suitable apparatus. A suitable apparatus includes a chamber divided by a grid structure into an upper sub-chamber and a lower sub-chamber, and electronic hardware for providing and maintaining etching conditions as described herein. Suitable apparatus will also include a system controller having instructions for controlling the hardware to achieve these conditions and for performing a sequence of process operations appropriate for applications such as etching a gate electrode of a FET. In some embodiments, the hardware may include one or more process stations included in a process tool.

FIG. 1 schematically shows a cross-sectional view of an inductively coupled plasma etching apparatus 100 in accordance with certain embodiments herein. The inductively coupled plasma etching apparatus 100 includes an overall etching chamber structurally defined by chamber walls 101 and a window 111. The chamber walls 101 are typically fabricated from stainless steel or aluminum. The window 111 is typically fabricated from quartz or other dielectric material. An internal plasma grid 150 divides the overall etching chamber into an upper sub-chamber 102 and a lower sub-chamber 103. A chuck 117 is positioned within the lower sub-chamber 103 near the bottom inner surface. The chuck 117 is configured to receive and hold a semiconductor wafer (i.e., “wafer”) 119 upon which the etching process is performed. The chuck 117 can be an electrostatic chuck for supporting the wafer when present. In some embodiments, an edge ring (not shown) surrounds chuck 117, and has an upper surface that is approximately planar with a top surface of a wafer, when present over chuck 117. The chuck 117 also includes electrostatic electrodes to enable the chucking and dechucking of the wafer. A filter and a DC clamp power supply may be provided for this purpose. Other control systems for lifting the wafer off of the chuck 117 can also be provided. The chuck 117 can be electrically charged using an RF power supply 123. The RF power supply 123 is connected to matching circuitry 121 through a connection 127. The matching circuitry 121 is connected to the chuck 117 through a connection 125. In this manner, the RF power supply 123 is connected to the chuck 117.

A coil 133 is positioned above the window 111. The coil 133 is fabricated from an electrically conductive material and includes at least one complete turn. The exemplary coil 133 shown in FIG. 1 includes three turns. The cross-sections of coil 133 are shown with symbols, and coils having an “X” extend rotationally into the page, while coils having a “•” extend rotationally out of the page. An RF power supply 141 is configured to supply RF power to the coil 133. In general, the RF power supply 141 is connected to matching circuitry 139 through a connection 145. The matching circuitry 139 is connected to the coil 133 through a connection 143. In this manner, the RF power supply 141 is connected to the coil 133. An optional Faraday shield 149 is positioned between the coil 133 and the window 111. The Faraday shield 149 is maintained in a spaced apart relationship relative to the coil 133. The Faraday shield 149 is disposed immediately above the window 111. The coil 133, the Faraday shield 149, and the window 111 are each configured to be substantially parallel to one another. The Faraday shield may prevent metal or other species from depositing on the dielectric window of the plasma chamber.

Process gases may be supplied through a main injection port 160 positioned in the upper chamber and/or through a side injection port 170, sometimes referred to as an STG. Gas exhaust ports are not shown. Also not shown are pumps connected to the chamber 101 to enable vacuum control and removal of gaseous byproducts from the chamber during operational plasma processing.

During operation of the apparatus, one or more reactant gases may be supplied through the injection ports 160 and/or 170. In certain embodiments, gas may be supplied only through the main injection port, or only through the side injection port. In some cases, the injection ports may be replaced by showerheads. The Faraday shield 149 and/or grid 150 may include internal channels and holes that allow delivery of process gas to the chamber. In other words, either or both of Faraday shield 149 and grid 150 may serve as a showerhead for delivery of process gas.

Radiofrequency power is applied from the RF power supply 141 to the coil 133 to cause an RF current to flow through the coil 133. The RF current flowing through the coil 133 generates an electromagnetic field about the coil 133. The electromagnetic field generates an inductive current within the upper sub-chamber 102. The inductive current acts on the gas present in the upper sub-chamber 102 to generate an electron-ion plasma in the upper sub-chamber 102. The internal plasma grid 150 limits the amount of hot electrons in the lower sub-chamber 103. In various embodiments, the apparatus is designed and operated such that the plasma present in the lower sub-chamber is an ion-ion plasma.

Both the upper electron-ion plasma and the lower ion-ion plasma will contain positive ions and negative ions, though the ion-ion plasma will have a greater ratio of negative ions:positive ions. The physical and chemical interactions of the various ions and radicals with the wafer 119 selectively etch features of the wafer. Volatile etching byproducts are removed from the lower sub-chamber through an exhaust port (not shown). Importantly, these volatile byproducts are not substantially exposed to hot electrons, and therefore they are not likely to be dissociated into non-volatile “sticky” dissociation products.

Typically, the chuck disclosed herein operates at elevated temperatures ranging between about 30° Celsius and about 250° Celsius, preferably between about 30-150° Celsius. The temperature will depend on the etching process operation and specific recipe. The chamber 101 may also operate at pressures in the range of between about 1 mTorr and about 95 mTorr, or between about 5-20 mTorr. However, in certain embodiments, the pressure may be higher, as disclosed above.

Although not shown, chamber 101 is typically coupled to facilities when installed in a clean room, or a fabrication facility. Facilities include plumbing that provide processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to chamber 101, when installed in the target fabrication facility. Additionally, chamber 101 may be coupled to a transfer chamber that will enable robotics to transfer semiconductor wafers into and out of chamber 101 using typical automation.

FIGS. 2A-2B show examples of internal plasma grids in accordance with the embodiments herein. The grid may have slots that extend radially outward. In the embodiment of FIG. 2B, there are three types of slots. Each of the three slot types has a different slot length. The slots shown in FIG. 2B have an aspect ratio that is suitable for creating an ion-ion plasma in the lower sub-chamber, as described above. The slots shown in FIG. 2A may not be drawn to scale.

In various embodiments, the semiconductor etching apparatus may be integrated into a multi-station tool. The multi-station tool may include multiple plasma etching reactors as disclosed herein, and may include additional stations for performing other semiconductor manufacturing processes. Multi-station integrated processing tools and methods of using such tools are further discussed and described in PCT Application No. PCT/US2006/004625, filed Feb. 8, 2006, and titled “WAFER MOVEMENT CONTROL MACROS,” and U.S. patent application Ser. No. 12/116,897, filed May 7, 2008, and titled “DYNAMIC ALIGNMENT OF WAFERS USING COMPENSATION VALUES OBTAINED THROUGH A SERIES OF WAFER MOVEMENTS,” each of which is herein incorporated by reference in its entirety.

FIG. 4 depicts a typical semiconductor process cluster architecture illustrating the various modules that interface with a vacuum transfer module 38 (VTM). As is well known to those skilled in the art, the arrangement of transfer modules to “transfer” wafers among multiple storage facilities and processing modules is frequently referred to as a “cluster tool architecture” system. Airlock 30, also called a loadlock or a transfer module, is shown in VTM 38 with four processing modules 20a-20d which may be individually optimized to perform various fabrication processes. By way of example, processing modules 20a-20d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and/or other typical semiconductor processes. One or more of the substrate etching processing modules (any of 20a-20d) may be implemented as disclosed herein, i.e., with a grid structure dividing the reaction chamber into an upper sub-chamber and a lower sub-chamber. When speaking in general about airlock 30 or process module 20, the term station will be used at times to refer to either an airlock or a process module. Each station has a facet 36 that interfaces the station to vacuum transfer module 38. Inside each facet, sensors 1-18 are used to detect the passing of wafer 26 when going in and out of the respective stations.

Robot 22 transfers wafer 26 between stations. In one embodiment, robot 22 has one arm, and in another embodiment robot 22 has two arms, where each arm has and end effector 24 to pick the wafers for transport. Front-end robot 32, in atmospheric transfer module 40 (ATM), is used to transfer wafers from cassette, or Front Opening Unified Pod (FOUP) 34 in Load Port Module (LPM) 42 to airlock 30. Module center 28 inside process module 20 indicates the ideal placement for placing wafer 26. Aligner 44 in ATM 40 is used to align wafers.

In an exemplary processing method, a wafer is placed in one of the FOUPs 34 in the Load Port Module 42. Front-end robot 32 transfers the wafer from the FOUP 34 to an aligner 44, which allows the wafer to be properly centered before it is etched. After being aligned, the wafer is moved by the front-end robot 32 into an airlock module 30. Because airlock modules have the ability to match the environment between an atmospheric transfer module and a vacuum transfer module, the wafer is able to move between the two pressure environments without being damaged. From the airlock module 30, the wafer is moved by robot 22 through vacuum transfer module 38 and into one of the process modules 20a-20d. In order to achieve this wafer movement, the robot 22 uses the end effectors 24 on each of its arms. Once the wafer has been processed, it is moved by robot 22 from the process modules 20a-20d to an airlock module 30. From here, the wafer may be moved by the front end-robot 32 to one of the FOUPs 34 or to the aligner 44.

It should be noted that the computer controlling the wafer movement can be local to the cluster architecture, or can be located somewhere in the manufacturing floor, or in a remote location, and connected to the cluster architecture via a network.

System Controller

In some embodiments, a system controller (which may include one or more physical or logical controllers) controls some or all of the operations of an etching chamber. The system controller may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and/or digital input/output connections, stepper motor controller boards, and other like components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on the memory devices associated with the controller or they may be provided over a network. In certain embodiments, the system controller executes system control software.

The system control software may include instructions for controlling the timing of application and/or magnitude of any one or more of the following chamber operational conditions: the mixture and/or composition of gases, chamber pressure, chamber temperature, wafer/wafer supporter temperature, the bias applied to the wafer, the frequency and power applied to coils or other plasma generation components, wafer position, wafer movement speed, and other parameters of a particular process performed by the tool. System control software may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components necessary to carry out various process tool processes. System control software may be coded in any suitable computer readable programming language.

In some embodiments, system control software includes input/output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a semiconductor fabrication process may include one or more instructions for execution by the system controller. The instructions for setting process conditions for an etching phase may be included in a corresponding etching recipe phase, for example. In some embodiments, the recipe phases may be sequentially arranged, so that all instructions for a process phase are executed concurrently with that process phase.

Other computer software and/or programs may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas composition control program, a pressure control program, a heater control program, and an RF power supply control program.

In some cases, the controllers control gas concentration, wafer movement, and/or the power supplied to the coils and/or electrostatic chuck. The controller may control the gas concentration by, for example, opening and closing relevant valves to produce one or more inlet gas streams that provide the necessary reactant(s) at the proper concentration(s). The wafer movement may be controlled by, for example, directing a wafer positioning system to move as desired. The power supplied to the coils and/or chuck may be controlled to provide particular RF power levels to create the desired electron-ion plasma in the upper sub-chamber and ion-ion plasma in the lower sub-chamber. Further, the controller may be configured to supply power to an electrostatic chuck under conditions such that an electron-ion plasma does not form in the lower sub-chamber. In other words, the controller is configured to maintain an ion-ion plasma (or at least a plasma with a suitably low effective electron temperature and density) in the lower sub-chamber. The controllers may control these or other aspects based on sensor output (e.g., when power, potential, pressure, etc. reach a certain threshold), the timing of an operation (e.g., opening valves at certain times in a process) or based on received instructions from a user.

The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility.

Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon nitride film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.

It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed.

The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof

Experimental

Experiments have confirmed that the presently disclosed methods and apparatus provide for improved etching of partially fabricated devices on semiconductor substrates. When using a plasma grid, the etched product shows good selectivity, profile angle, iso/dense loading, and overall etch uniformity.

FIGS. 5A-5B show scanning electron microscope (SEM) images of FinFET structures that have been etched according to a high pressure conventional technique (5A) and according to the present embodiments using a plasma grid (5B). As shown in FIG. 5A, the conventional technique results in significant non-uniformity between the center and edge of the wafer. For example, the bottom of the feature was substantially more etched at the center of the wafer than at the edge. This suggests that dissociation byproduct redeposition was more problematic near the edges of the wafer than at the center. The I/D loading was large, and there was poor selectivity between the materials. Iso/Dense loading may be considered in several ways. Iso/Dense etch depth loading may be calculated as the difference between an etch depth for isolated features (generally large features, for example lines having 500 nm spaces) and an etch depth for dense features (generally small features, for example lines having 30 nm spaces). Iso/Dense profile loading may be calculated as the difference between a profile angle for isolated features and a profile angle for dense features. Iso/Dense loading may also refer to a comparison of critical dimensions (CDs). In this regard, Iso/Dense loading may be calculated as: (bottom CD−top CD) for isolated features—(bottom CD−top CD) for dense features. Unless otherwise specified, I/D loading is intended to refer to this comparison of critical dimensions.

Conversely, as shown in FIG. 5B, the use of the plasma grid substantially increases the center to edge uniformity. Further, the I/D loading was much lower, and the selectivity was improved. This experiment was performed on a Si carrier wafer thinned to a thickness representative of the FinFET height and covered with 50% SiN coupons to simulate the etch of a full-patterned wafer. The FinFET structures were over-etched by 65% to minimize the taper in the profile.

FIGS. 6A-6B show SEM images of features etched according to a low pressure conventional technique (6A) and according to the present embodiments using a plasma grid (6B). The conventional technique showed relatively poor selectivity between the silicon and oxide, the etched features had a tapered profile, and the I/D loading was poor. As shown in FIG. 6B, however, the plasma grid provided improved selectivity (infinite selectivity), a more vertical profile angle, and virtually no I/D loading. This experiment was performed on a chip cleaved from a patterned wafer and placed on the center of a carrier wafer. This experiment was performed on a Si carrier wafer thinned to a thickness representative of the FinFET height and covered with 50% SiN coupons to simulate the etch of a full-patterned wafer.

FIG. 7 shows various SEM images of features that have been etched according to various regimes without the use of a plasma grid. Two different pressures were used, as well as four different total flow rates. The effective electron temperature (Te) decreases with increasing pressure. Residence time decreases with increasing total flow rate. For each pressure, increasing the total flow rate improves the etch results. In particular, the high flow cases show better (more vertical) profile angles and improved selectivity (more mask remaining). However, these improvements are mitigated by poorer I/D loading and center to edge uniformity. The results at high flow rates support the belief that certain byproducts and/or dissociation products, when not swept away in gaseous form, may be adhering to feature sidewalls and/or bottoms to produce poor etching results, as illustrated in FIGS. 3A-3C. When the total flow rate is higher, these byproducts are more effectively swept out of the reaction chamber and are less likely to cause etching defects.

Various experiments showed that the use of the plasma grid resulted in an etching process with very good selectivity, profile angle, I/D loading, and center to edge uniformity. In certain cases, the selectivity (i.e., the etch rate of Si:etch rate of oxide) is greater than about 10, or greater than about 100. In fact, infinite selectivity may be achieved using the plasma grid in certain cases. In these cases, there is virtually no etching of the oxide material, and there may even be a small amount of deposition on the oxide surface. The profile angle achieved in many cases is substantially vertical (e.g., over about 89°). In certain implementations, the I/D loading was shown to be below about 2°. Further, the center to edge uniformity in various implementations was less than about 2 nm.

Claims

1. An apparatus for etching a feature on a substrate, the apparatus comprising:

a chamber defining an interior where a plasma can be provided;

a substrate holder for holding a substrate in the chamber during etching;

a plasma generator for producing a plasma within the chamber; and

a grid dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder,

wherein the upper sub-chamber has a height that is at least about ⅙ that of the lower sub-chamber,

wherein the grid comprises a plurality of slots that extend substantially radially outwards that substantially prevent formation of induced current in the grid when the plasma is produced within the chamber.

2. The apparatus of claim 1, further comprising a controller designed or configured to produce the plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber,

wherein the effective electron temperature in the lower zone plasma is about 1 eV or less, and is less than the effective electron temperature in the upper zone plasma, and

wherein the electron density in the lower zone plasma is about 5×109 cm−3 or less, and is less than the electron density in the upper zone plasma.

3. The apparatus of claim 2, wherein the controller is further designed or configured to apply a bias to the grid.

4. The apparatus of claim 2, wherein the controller is further designed or configured to apply a bias to the substrate holder.

5. The apparatus of claim 2, wherein the controller is further designed or configured to deliver an etchant gas to the chamber.

6. The apparatus of claim 2, wherein the controller is further designed or configured to provide a pressure of less than about 2000 mTorr in the chamber while the plasma etches the substrate.

7. The apparatus of claim 2, wherein the controller is further designed or configured to produce an ion-ion plasma in the lower sub-chamber.

8. The apparatus of claim 1, wherein the grid has an average thickness of between about 1 and 50 mm.

9. The apparatus of claim 1, wherein the slots of the grid have a height to width aspect ratio of between about 0.3-5.

10. The apparatus of claim 1, wherein the slots are separated from azimuthally adjacent slots by no more than about 60 degrees.

11. The apparatus of claim 1, wherein the plasma generator comprises a coil disposed above a ceiling of the chamber.

12. (canceled)

13. The apparatus of claim 1, further comprising a vacuum connection.

14. (canceled)

15. A grid for use in connection with a semiconductor etching apparatus, comprising:

a plate having a diameter that is substantially the same as the diameter of a standard semiconductor substrate for semiconductor device fabrication;

a plurality of slots that extend substantially radially outwards in the plate to substantially prevent formation of induced current in the plate when the plate is exposed to plasma;

wherein the slots have an aspect ratio that is between about 0.3-5.

16. The grid of claim 15, wherein the grid, when placed in a processing chamber of a semiconductor etching apparatus, thereby dividing the processing chamber into an upper sub-chamber and a lower sub-chamber, and exposed to a plasma generated in the upper sub-chamber, operates to maintain a lower electron density in the lower sub-chamber that is at least about 10 times lower than an upper electron density in the upper sub-chamber.

17. The grid of claim 16, wherein the grid operates to maintain the lower electron density at least about 100 times lower than the upper electron density.

18. The grid of claim 15, wherein the standard semiconductor substrate has a diameter of about 300 mm or about 450 mm.

19. The grid of claim 15, wherein azimuthally adjacent slots are separated by at least about 10°, and by no more than about 60°.

20. The grid of claim 15, wherein the grid comprises metal.

21. The grid of claim 15, wherein the grid comprises an insulative material.

22. A method of etching a feature on a substrate, the method comprising:

providing the substrate to a substrate holder in a chamber comprising a plasma generator and a grid dividing the interior of the plasma chamber into an upper sub-chamber proximate the plasma generator and a lower sub-chamber proximate the substrate holder, wherein the upper sub-chamber has a height that is at least about ⅙ that of the lower sub-chamber;

generating a plasma in the chamber under conditions that produce an upper zone plasma in the upper sub-chamber and a lower zone plasma in the lower sub-chamber; and

etching the feature in the substrate by interaction of the lower zone plasma with the substrate,

wherein the effective electron temperature in the lower zone plasma is about 1 eV or less, and is less than the effective electron temperature in the upper zone plasma, and

wherein the electron density in the lower zone plasma is about 5×109 cm−3 or less, and is less than the electron density in the upper zone plasma.

23-28. (canceled)