Conductor Comprising Silicide Layer Formed By Silicidation Reaction Of Silicon With Metal Layer (epo) Patents (Class 257/E21.199)
  • Patent number: 11443949
    Abstract: A substrate processing method includes providing a substrate containing a first semiconductor material and a second semiconductor material, treating the first semiconductor material and the second semiconductor material with a chemical source that selectively forms a chemical layer on the second semiconductor material relative to the first semiconductor material, and exposing the substrate to a first metal-containing precursor that selectively deposits a first metal-containing layer on the first semiconductor material relative to the chemical layer on the second semiconductor material.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 13, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 11404309
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11367781
    Abstract: A manufacturing method of the semiconductor structure including the following is provided. Gate structures are formed on a substrate. Each gate structure includes a gate, a first spacer, and a second spacer. The gate is disposed on the substrate. The first spacer is disposed on a sidewall of the gate. The second spacer is disposed on the first spacer. In a region between two adjacent gate structures, the first spacers are separated from each other, and the second spacers are separated from each other. A protective layer is formed between the two adjacent gate structures. The protective layer covers lower portions of the second spacers and exposes upper portions of the second spacers. A part of the upper portions of the second spacers is removed using the protective layer as a mask to enlarge a distance between the upper portions of the second spacers. The protective layer is removed.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 21, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Zhenhai Zhang
  • Patent number: 11227951
    Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Patent number: 10977977
    Abstract: It is an object to provide a semiconductor display device with high reliability. Further, it is an object to provide a semiconductor display device which can reduce power consumption. A decoder is provided for a scan line driver circuit and operates such that, in accordance with a signal input to the scan line driver circuit, a pulse is sequentially input only to scan lines included in pixels of rows performing display and a pulse is not input to scan lines included in pixels of rows at which display is not performed. Then, all pixels or part of pixels in the line selected by the pulse is supplied with a video signal from a signal line driver circuit, whereby display of an image is performed in pixels arranged in the specific area of the pixel portion.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Umezaki, Mai Akiba
  • Patent number: 10770352
    Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a first region for forming a first transistor and a second region for forming a second transistor, the first transistor having a working current less than the second transistor. The fabrication method further includes forming a gate electrode layer on the base substrate; etching the gate electrode layer to form a first gate electrode in the first region; after forming the first gate electrode, etching the gate electrode layer to form a second gate electrode in the second region, with the second gate electrode having an undercut structure; forming a first source/drain doped region in the base substrate on both sides of the first gate electrode and forming a second source/drain region in the base substrate on both sides of the second gate electrode.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 8, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10714330
    Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 14, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoo Nakayama, Tatsuya Usami
  • Patent number: 10672804
    Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 10651089
    Abstract: A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Shogo Mochizuki, Oleg Gluschenkov
  • Patent number: 10553427
    Abstract: Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1-x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 4, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinhai Han, Kang Sub Yim, Zhijun Jiang, Deenesh Padhi
  • Patent number: 10553481
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 10395981
    Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Peter Moll, Jeremy Austin Wahl
  • Patent number: 10360831
    Abstract: It is an object to provide a semiconductor display device with high reliability. Further, it is an object to provide a semiconductor display device which can reduce power consumption. A decoder is provided for a scan line driver circuit and operates such that, in accordance with a signal input to the scan line driver circuit, a pulse is sequentially input only to scan lines included in pixels of rows performing display and a pulse is not input to scan lines included in pixels of rows at which display is not performed. Then, all pixels or part of pixels in the line selected by the pulse is supplied with a video signal from a signal line driver circuit, whereby display of an image is performed in pixels arranged in the specific area of the pixel portion.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Umezaki, Mai Akiba
  • Patent number: 10276671
    Abstract: A semiconductor device includes a compound semiconductor layer, a gate electrode, and first and second insulating layers. The first insulating layer covers the gate electrode on the compound semiconductor layer and has a cavity that surrounds the gate electrode. The second insulating layer is provided on the first insulating layer and has an opening at a position corresponding to the cavity. A part of the second insulating layer, which is provided on the first insulating layer that covers the gate electrode, corresponding to the cavity is removed via the opening, so that the generation of parasitic capacitance due to the second insulating layer is suppressed.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shirou Ozaki
  • Patent number: 10019924
    Abstract: It is an object to provide a semiconductor display device with high reliability. Further, it is an object to provide a semiconductor display device which can reduce power consumption. A decoder is provided for a scan line driver circuit and operates such that, in accordance with a signal input to the scan line driver circuit, a pulse is sequentially input only to scan lines included in pixels of rows performing display and a pulse is not input to scan lines included in pixels of rows at which display is not performed. Then, all pixels or part of pixels in the line selected by the pulse is supplied with a video signal from a signal line driver circuit, whereby display of an image is performed in pixels arranged in the specific area of the pixel portion.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: July 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Umezaki, Mai Akiba
  • Patent number: 10020260
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shafaat Ahmed, Benjamin G. Moser, Vimal Kumar Kamineni, Dinesh Koli, Vishal Chhabra
  • Patent number: 9997628
    Abstract: The present disclosure provides a semiconductor device and a method of fabricating the semiconductor device. In some embodiments, the semiconductor device includes a substrate having a well region, a first source/drain region, a second source/drain region, a buried channel and a gate structure. The first source/drain region is located within the well region. The gate structure includes a co-doped gate including polysilicon and having a first concentration of a n-type impurity and a second concentration of a p-type impurity, in which the n-type impurity and the p-type impurity are mixed and distributed.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Jheng-Hong Jiang, Fu-Cheng Chang, Ching-Hung Kao, Hsin-Chi Chen
  • Patent number: 9966434
    Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
  • Patent number: 9722030
    Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
  • Patent number: 9722081
    Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Patent number: 9666686
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok
  • Patent number: 9624576
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee
  • Patent number: 9537040
    Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: January 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Patent number: 9425283
    Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: Suk Ki Kim, Kang Sik Choi
  • Patent number: 9337293
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pai-Chieh Wang, Tsung Yao Wen, Jyh-Huei Chen
  • Patent number: 8975682
    Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Rebha El Farhane, Benoit Froment
  • Patent number: 8975181
    Abstract: A semiconductor device and manufacture method thereof include a silicide material formed on a source region and a drain region on opposite sides of a gate, wherein the gate having sidewalls on both side surfaces is formed on a substrate. The gate has a first sidewall spacer and a second sidewall spacer on each sidewall, the first spacer has a horizontal portion and a vertical portion, the horizontal portion is located between the second sidewall spacer and the substrate, the vertical portion is located between the second sidewall spacer and the sidewalls. A protecting layer is selectively deposited on the silicide material.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fenglian Li
  • Patent number: 8877595
    Abstract: A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Manoj Mehrotra
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8859398
    Abstract: Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tobias Letz, Frank Feustel, Kai Frohberg
  • Patent number: 8765603
    Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Wei-Yang Lee, Xiong-Fei Yu, Kuang-Yuan Hsu
  • Patent number: 8722534
    Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Hoon Kim, Vivian W. Ryan
  • Patent number: 8592277
    Abstract: A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 26, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, James Kent Naylor
  • Patent number: 8497205
    Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Mitsuaki Izuha
  • Patent number: 8482043
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A Glass, Thomas Hoffman
  • Patent number: 8440564
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Patent number: 8435889
    Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: May 7, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 8368219
    Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 5, 2013
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jusuke Ogura
  • Patent number: 8350344
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Son, Woon-Kyung Lee
  • Patent number: 8343867
    Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Yu-Ying Hsu, Chi-Ju Lee, Sin-Hua Wu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 8334574
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Keun Park
  • Patent number: 8330234
    Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 11, 2012
    Assignee: NEC Corporation
    Inventor: Takashi Hase
  • Patent number: 8304319
    Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wen-Chi Tsai, Mei-Yun Wang, Chii-Ming Wu, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 8304841
    Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeff J. Xu, Cheng-Tung Lin, Hsiang-Yi Wang, Wen-Chin Lee, Betty Hsieh
  • Patent number: 8283248
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyun Kim, Kyung-Hyun Kim, Jae-Hwang Sim, Jae-Jin Shin, Jong-Heun Lim, Hyun-Min Park
  • Patent number: 8247257
    Abstract: A method for providing a semiconductor material for photovoltaic devices, the method includes providing a sample of iron disilicide comprising approximately 90 percent or greater of a beta phase entity. The sample of iron disilicide is characterized by a substantially uniform first particle size ranging from about 1 micron to about 10 microns. The method includes combining the sample of iron disilicide and a binding material to form a mixture of material. The method includes providing a substrate member including a surface region and deposits the mixture of material overlying the surface region of the substrate. In a specific embodiment, the mixture of material is subjected to a post-deposition process such as a curing process to form a thickness of material comprising the sample of iron disilicide overlying the substrate member. In a specific embodiment, the thickness of material is characterized by a thickness of about the first particle size.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: August 21, 2012
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Frederic Victor Mikulec, Bing Shen Gao, Jinman Huang
  • Patent number: 8232201
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: July 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Patent number: 8187970
    Abstract: Methods for forming cobalt silicide materials are disclosed herein. In one example, a method for forming a cobalt silicide material includes exposing a substrate having a silicon-containing material to either a wet etch solution or a pre-clean plasma during a first step and then to a hydrogen plasma during a second step of a pre-clean process. The exemplary method further includes depositing a cobalt metal layer on the silicon-containing material by a CVD process, heating the substrate to form a first cobalt silicide layer comprising CoSi at the interface of the cobalt metal layer and the silicon-containing material during a first annealing process, removing any unreacted cobalt metal from the first cobalt silicide layer during an etch process, and heating the substrate to form a second cobalt silicide layer comprising CoSi2 during a second annealing process.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: May 29, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Sang-Ho Yu, See-Eng Phan, Mei Chang, Amit Khandelwal, Hyoung-Chan Ha
  • Patent number: 8178433
    Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Glenn A. Biery, Michelle L. Steen
  • Patent number: 8178438
    Abstract: Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 15, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoaki Moriwaka