Process tube for manufacturing semiconductor wafers
Latest Tokyo Electron Limited Patents:
- SURFACE RELIEF GRATING WITH METAL INSERT
- SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM
- Plasma processing apparatus, power supply system, control method, program, and storage medium
- Method for etching a layer through a patterned mask layer
- Board processing equipment and recovery processing method
Description
Claims
The ornamental design for a process tube for manufacturing semiconductor wafers, as shown and described.
Referenced Cited
U.S. Patent Documents
| 4950870 | August 21, 1990 | Mitsuhashi et al. |
| D324645 | March 17, 1992 | Magro et al. |
| D404368 | January 19, 1999 | Shimazu |
| D405429 | February 9, 1999 | Hanagata et al. |
| D405430 | February 9, 1999 | Matsushima |
| D407696 | April 6, 1999 | Shimazu |
| 5948300 | September 7, 1999 | Gero et al. |
| 5968593 | October 19, 1999 | Sakamoto et al. |
| D417438 | December 7, 1999 | Matsushima |
| D424024 | May 2, 2000 | Hanagata et al. |
| D552047 | October 2, 2007 | Sugawara |
| D586768 | February 17, 2009 | Inoue et al. |
| 20070181062 | August 9, 2007 | Kim et al. |
Patent History
Patent number: D611013
Type: Grant
Filed: Sep 26, 2008
Date of Patent: Mar 2, 2010
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Kiyohiko Takahashi (Oshu)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/309,700
Type: Grant
Filed: Sep 26, 2008
Date of Patent: Mar 2, 2010
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Kiyohiko Takahashi (Oshu)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/309,700
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)