Process tube for manufacturing semiconductor wafers

- Tokyo Electron Limited
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Description

FIG. 1 is a perspective view;

FIG. 2 is a front view;

FIG. 3 is a rear view;

FIG. 4 is a left side view and the right side being a mirror image thereof;

FIG. 5 is a plan view and the bottom plan being a mirror image thereof;

FIG. 6 is a sectional view thereof along 6—6 of the plan view shown in FIG. 5;

FIG. 7 is an enlarged sectional view along 7—7 of the rear view shown in FIG. 3; and,

FIG. 8 is a view of process tube for manufacturing semiconductor wafers in use wherein the broken line showing of the environment is for illustrative purposes only and forms no part of the claimed design.

Claims

The ornamental design for a process tube for manufacturing semiconductor wafers, as shown and described.

Referenced Cited
U.S. Patent Documents
4950870 August 21, 1990 Mitsuhashi et al.
D324645 March 17, 1992 Magro et al.
D404368 January 19, 1999 Shimazu
D405429 February 9, 1999 Hanagata et al.
D405430 February 9, 1999 Matsushima
D407696 April 6, 1999 Shimazu
5948300 September 7, 1999 Gero et al.
5968593 October 19, 1999 Sakamoto et al.
D417438 December 7, 1999 Matsushima
D424024 May 2, 2000 Hanagata et al.
D552047 October 2, 2007 Sugawara
D586768 February 17, 2009 Inoue et al.
20070181062 August 9, 2007 Kim et al.
Patent History
Patent number: D611013
Type: Grant
Filed: Sep 26, 2008
Date of Patent: Mar 2, 2010
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Kiyohiko Takahashi (Oshu)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/309,700