Abstract: A circuit board pad connector system includes a connector that is configured to mount to a connector pad that is included on a circuit board. The connector includes a connector lead frame. A lead portion is provided on the connector lead frame such that the lead portion is oriented substantially perpendicularly relative to the connector pad when the connector is mounted to the connector pad. A first mounting portion is provided on the connector lead frame, is configured to mount the connector to the connector pad, and extends in a first direction that is substantially perpendicular relative to the lead portion. A second mounting portion is provided on the connector lead frame, is configured to mount the connector to the connector pad, and extends in a second direction that is different than the first direction and that is substantially perpendicular relative to the lead portion.

Abstract: A printed circuit board and an electronic apparatus having the printed circuit board are provided. The printed circuit board includes a circuit board body and an electronic element disposed on the circuit board body, the circuit board body is provided with a conductive hole, the circuit board body is grounded by a conductor provided in the conductive hole, and at least one through hole is disposed between the conductive hole and at least part of the electronic element.

Abstract: An enhanced social network module associated with an entity may create a social network for an individual, group, and/or organization. The module may then use the social network to determine risk associated with insuring a member of the social network. The determined risk may be used to calculate a rate for insuring the member. Additional features of the module may allow for the calculation of a group rate for insuring all members of the social network, the calculation of various centrality measures for each member of the social network, the calculation of a trust score for any given member, and the ability to poll members of the social network to determine various characteristics of any given member.

Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.

Abstract: A method of connecting a fine wire to an ultrafine wire, the fine wire exhibiting a first cross-section and the ultrafine wire exhibiting a second cross-section, the second cross-section smaller than the first cross-section, the method constituted of: providing an uninsulated portion of the fine wire exhibiting a flat surface; depositing a conductive material on the flat surface of the provided uninsulated portion of the fine wire; providing an uninsulated portion of the ultrafine wire; and bonding the provided uninsulated portion of the ultrafine wire to the deposited conductive material on the flat surface of the provided uninsulated portion of the fine wire by thermocompression.

Abstract: In some examples, a printed circuit board assembly can include a printed circuit board having four (4) central processor unit (CPU) sockets disposed thereon and sixty four (64) dual in-line memory modules (DIMMs) disposed thereon. The printed circuit board can have a top surface and a bottom surface with two (2) CPU sockets and thirty two (32) DIMMs disposed on the top surface and two (2) CPU sockets and thirty two (32) DIMMs disposed on the bottom surface.

Abstract: A coil component includes a body in which a coil portion is embedded. The coil portion includes a support member; first insulators formed on first and second main surfaces of the support member, respectively, and having an opening having a planar coil shape; coils filling the openings; and second insulators covering the coils.

Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

Abstract: A thermal management system includes one or more heating elements positioned proximate a battery pack. A temperature sensor is configured to determine a battery temperature for the battery pack. A controller is configured to: compare the battery temperature to a desired set point, and if the battery temperature is below the desired set point, energize the one or more heating elements positioned proximate the battery pack to raise the temperature of the battery pack.

Abstract: A package structure and a manufacturing method thereof, and a display panel are provided, and the package structure comprises a package stack disposed on a substrate; and an additional layer disposed on the package stack. The package structure provided by the present disclosure results in saving of one deposition process and one mask process, thereby the manufacturing process is simplified. Moreover, a narrow bezel may be realized.

Abstract: A manufacturing method for a circuit board and a circuit board are provided. The method includes steps: providing a substrate having a first metal layer; forming a patterned first opening on the first metal layer to expose the substrate; forming a patterned first dielectric layer on the substrate, the first dielectric layer is made of a photosensitive dielectric material and covers the first opening; photosensitizing the first dielectric layer to cure the first dielectric layer; forming a patterned second metal layer on the first metal layer; forming a patterned third metal layer on the second metal layer, and the third metal layer being adjacent to the first dielectric layer; removing a portion of the first metal layer not covered by the second metal layer; and forming a second dielectric layer on the substrate. A thickness of the third metal layer is greater than a thickness of the second metal layer.

Abstract: A wiring assembly includes a differential input port, a differential output port, and first and second pairs of electrical leads. The differential input port is configured to receive a differential signal from a sensor at a first end of the wiring assembly. The differential output port is configured to output the differential signal at a second end of the wiring assembly. The first and second pairs of electrical leads convey the differential signal from the first end to the second end, and are connected to one another at the first end and at the second end in a configuration that cancels pickup of an ambient magnetic field by the wiring assembly.

Abstract: A power supply includes a main circuit board and a multilayer power transmission board for transmitting power from one area of the main circuit board to another area of the main circuit board. The main circuit board includes a power input connector having power connections. The multilayer power transmission board includes conductive layers electrically coupled to the power connections of the power input connector, and a dielectric medium positioned between each of the conductive layers. The conductive layers of the multilayer board may include at least two conductive neutral layers and at least two conductive line layers positioned in an alternating configuration. Other example power supplies, multilayer boards and methods of manufacturing power supplies are also disclosed.

Abstract: Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.

Abstract: A wiring substrate includes a first substrate including a wiring layer and a solder resist layer that partially covers the wiring layer. The solder resist layer includes a circular opening partially exposing the wiring layer and a support partially covering the wiring layer within the opening. The wiring layer includes a first connection pad exposed in the opening and formed by a portion of the wiring layer located at an outer side of the support. The wiring substrate further includes a cylindrical connection pin and a bonding member that bonds a first end surface of the connection pin and the first connection pad located in the opening.

Abstract: A pad 11 is disposed at an end point of a first wiring 17 provided on a board 15, is connectable to one of N (N: an integer of two or more) wirings provided on the board 15 via a resistor or a conductor, and has (N+1) sides that are disposed by deforming respective sides of an equilateral polygon having (N+1) sides into convex sides each having a radius of curvature that is larger than a radius of curvature of a circumscribed circle of the equilateral polygon.

Abstract: The present disclosure provides a metal-resin composite and a preparation method. The metal-resin composite includes a metal substrate; a porous resin layer formed on the metal substrate; a plastic layer formed on the porous resin layer; and a pore passage. The pore passage passes through the porous resin layer and extends inside the metal substrate, and the plastic layer fills in the pore passage to bond with the metal substrate.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

Abstract: A wiring assembly includes a differential input port, a differential output port, and first and second pairs of electrical conductors. The differential input port is configured to receive a differential signal from a sensor at a first end of the wiring assembly. The differential output port is configured to output the differential signal at a second end of the wiring assembly. The first and second pairs of electrical conductors are laid out in a three-dimensional (3D) crossover configuration relative to one another and configured to conduct the differential signal from the first end to the second end, and to cancel pickup of a magnetic field by the wiring assembly. The electrical conductors of each pair are connected to one another at the first end and at the second end.

Abstract: Systems and methods for fine pitch component placement on printed circuit boards are described. In one embodiment, a printed circuit board includes multiple vias and multiple of electrically conductive pads. The multiple vias include at least a first via and a second via. The multiple electrically conductive pads include a first pad and a second pad. The first pad and/or the second pad may include an electrically conductive material such as copper, silver, gold, or another conductive material. In some cases, the first pad and the second pad each have a reduced width portion positioned between and spaced apart from the first via and the second via.

Abstract: A flexible printed circuit board according to an embodiment of the present invention includes an insulative base film; and a conductive pattern provided on at least one surface of the base film and including a wiring line including a bent portion having an angle of greater than or equal to 60° or a branched portion having an angle of greater than or equal to 60° in plan view. The wiring line is provided with a relaxation structure that relaxes stress concentration at the bent portion or the branched portion. The relaxation structure is structured such that the wiring line constitutes a wide wiring line or a dense wiring line group in a region in which a distance from the bent portion or the branched portion is less than or equal to 5 times a minimum width of the wiring line. The wide wiring line has a wiring line width that is greater than or equal to twice the minimum width of the wiring line.

Abstract: Method of manufacturing laminate body by: curing thermosetting resin composition on a support; laminating the curable resin onto a substrate; heating the laminate; forming a via hole in the cured resin layer; peeling the supporting body from the cured composite; performing a second heating of the cured composite; removing resin residue in the via hole of the cured composite; and forming a conductor layer on an inner wall surface of the via hole by electroless plating or a combination of electroless plating and electrolytic plating.

Abstract: An apparatus comprising a printed circuit board (PCB) that includes: a multilayer lamination of layers; vias on a surface of the PCB; and bonding pads that couple a ball grid array of an integrated circuit (IC) package to layers through the vias, wherein the bonding pads includes: first bonding pads in a first area of the PCB, each first bonding pad being coupled to a via of the vias in the first area, second bonding pads arranged in a second area of the PCB, each second bonding pad being coupled to a via of the vias in the second area, and third bonding pads arranged in a third area of the PCB, each third bonding pad being coupled to two or more vias of the vias in the third area, wherein the third area is located between the first area and the second area is disclosed.

Abstract: An electronic unit comprising a box defining a reception compartment for receiving an electronic module along two mutually opposite directions of an insertion axis, the compartment including electrical power supply means for powering the electronic module and connection means for connecting the electronic unit to the electronic module, these means extending onto a connection face forming part of the reception compartment and extending parallel to the insertion axis. An electronic module for mounting in a compartment of an electronic unit of the invention.

Abstract: Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.

Abstract: A multilayer substrate includes a differential line including first and second line conductors provided on or in a laminated body including base material layers. The differential line includes line portions and a connecting portion that connects the line portions. The connecting portion includes first parallel conductors extending in parallel or substantially in parallel with each other, first interlayer connecting conductors that connect the first parallel conductors in parallel, and connect the first line conductor to the first parallel conductors, second parallel conductors extending in parallel or substantially in parallel with each other, and second interlayer connecting conductors that connect the second parallel conductors in parallel, and connect the second line conductor to the second parallel conductors. The first parallel conductors cross the second parallel conductors as viewed in a laminating direction of the base material layers.

Abstract: A method of manufacturing an inkjet head substrate is provided. The inkjet head substrate includes an ink supply port having a through portion and a non-through portion, and the non-through portion is disposed at a position closer than the through portion to the energy generating element. The method includes disposing a mask having an opening that has a relatively large opening-width portion and a relatively small opening-width portion. The method also includes forming the through portion in the substrate at a position corresponding to the relatively large opening-width portion and the non-through portion in the substrate at a position corresponding to the relatively small opening-width portion by performing reactive ion etching on the substrate through the opening of the mask in one operation.

Abstract: A test apparatus includes a host compliance printed circuit board having a first circuit plane and a second circuit plane separated by at least one dielectric layer. A first row of surface mount pads are disposed on the first circuit plane. The first row of surface mount pads includes a first pad and a second pad. A second and third row of surface mount pads are disposed on the first circuit plane. A first and second differential pair of circuit lines is disposed on the first circuit plane. The first differential circuit line has one end coupled to the first pad. The second differential circuit line has one end coupled to the second pad. The first and second differential pair of circuit lines extend from the first and second pads and between the second and third rows of surface mount pads.

Abstract: An object is to provide the structure of an ECU enabling resin to be filled without deformation of an electronic circuit board. A resin-sealed vehicle-mounted control device includes: a circuit board; a base member housing the circuit board; and resin filled between the circuit board and the base member. The base member has: a base portion fixing the circuit board; and a side wall opposed to the side surface side of the circuit board. The resin is provided at least between the circuit board and the base portion. The side wall has an opening at any position on the side of the base portion from a position opposed to the side surface side of the electronic circuit board.

Abstract: A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.

Abstract: A flexible printed circuit board is disclosed, which includes a pad portion, wherein the pad portion includes a pair of first signal pads formed in a first conductor layer and respectively connected with a pair of signal wires, a pair of second signal pads formed in a second conductor layer and electrically separated from a grounding layer; a pair of first grounding pads formed in the first conductor layer and electrically separated from the pair of signal wires, wherein: the pair of first signal pads is sandwiched between the pair of first grounding pads, and a pair of second grounding pads formed in the second conductor layer and connected with the grounding layer, wherein the pair of second signal pads are sandwiched between the pair of second grounding pads. A width of the first and the second signal pads is larger than that of the signal wires.

Abstract: Some embodiments are directed to techniques for building single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while others use an intervening adhesion layer material. Some embodiments use different seed layer and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while others apply the materials in blanket fashion. Some embodiments remove extraneous material via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material.

Abstract: A driver circuit carrier, a display panel, and a manufacturing method are provided. The driver circuit carrier includes a substrate, and a number of first pins arranged on at least one surface of the substrate. The first pins are arranged along a first reference line. An imaginary extending line of at least one of the first pins intersects with a second reference line perpendicular to the first reference line.

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract: An apparatus includes a substrate mechanically and electrically connected on one side of the substrate to multiple metallic probes in one or more arrays and includes the multiple metallic probes in the one or more arrays. In a method, multiple pits may be formed in an array on a first substrate. The pits have a pyramidal shape. A release layer is formed on the first substrate and covers surfaces of the pits. Probe tips are formed in the pits on the first substrate. The probe tips are formed from rigid conductive material. Multiple pillars are formed from rigid conductive material. The pillars are electrically and mechanically connected to a second substrate and to the probe tips. Release is caused of the probe tips from the first substrate, wherein the pillars and probe tips are connected to the second substrate and together form an array of rigid and conductive probes.

Abstract: A high-frequency circuit board includes a first circuit structure, a second circuit structure, and a dielectric layer formed on the second circuit structure. The first circuit structure includes a first substrate layer and at least one first circuit layer. The at least one first circuit layer is formed on at least one surface of the first substrate layer. At least one receiving cavity is defined in the first substrate layer. A second circuit structure is embedded in the receiving cavity. The second circuit structure includes a second substrate layer, at least one second circuit layer embedded in the second substrate layer, and a plurality of support columns formed on the second substrate layer. A portion of the dielectric layer is filled into gaps between an inner wall of the receiving cavity and the second circuit structure. The support columns are embedded in the dielectric layer.

Abstract: Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.

Abstract: The embodiments of the present invention provide a substrate, a chip on film and an electronic equipment. The substrate includes a plurality of first bonding pads arranged side by side along a first direction. Each first bonding pad has a first side edge and a second side edge arranged oppositely, which are arranged along the first direction. A third side edge and a fourth side edge of the first bonding pad are arranged oppositely and arranged along a second direction perpendicular to the first direction. The first side edge and second side edge of each first bonding pad are not parallel to each other.

Abstract: A circuit board includes a board, circuitry provided on the board that supplies electric power to a motor, a positive-electrode-side power source terminal portion connected to a positive electrode terminal of the circuitry, and a negative-electrode-side power source terminal portion connected to a negative electrode terminal of the circuitry. The circuitry includes a first capacitor connected to the positive-electrode-side power source terminal portion, and a second capacitor connected to the negative-electrode-side power source terminal portion. The first and second capacitors are connected in series between the positive-electrode-side and the negative-electrode-side power source terminal portions. The board includes a through hole, at least a portion of which is between at least two of the first capacitor, the second capacitor, the positive-electrode-side power source terminal portion, and the negative-electrode-side power source terminal portion.

Abstract: A connection structure between a flat cable and an electronic circuit board includes an electronic circuit board; a cable connection hole formed to penetrate the electronic circuit board; a plurality of internal contacts provided on an inner surface of the cable connection hole; and a flat cable provided with a plurality of contacts which correspond to the plurality of internal contacts of the cable connection hole and are exposed to one side surface of the flat cable. When one end of the flat cable is inserted into the cable connection hole of the electronic circuit board, the plurality of contacts of the flat cable are in contact with the plurality of internal contacts of the cable connection hole, respectively.

Abstract: A vehicle frame construction or frame assembly and method for assembling a multi-material vehicle frame includes a first frame member formed of a first metal material and a second frame member formed of a second metal material that is dissimilar to the first metal material. The second frame member is joined to the first frame member via vaporizing foil actuator welding (VFAW).

Abstract: A touch sensor includes a sensing pattern which includes a first mesh pattern formed in a first direction and a second mesh pattern formed in a second direction, the second mesh pattern including isolated unit patterns, a bridge electrode connecting the neighboring isolated unit patterns of the second mesh patterns, an insulation layer disposed between the sensing pattern and the bridge electrodes, and an auxiliary mesh pattern disposed on or below at least one of the first mesh pattern and the second mesh pattern, the auxiliary mesh pattern being connected to at least one of the first mesh pattern and the second mesh pattern.

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

Abstract: A silicon interposer that includes an array, or pattern, of conductive paths positioned within a silicon substrate with a plurality of pins on the exterior of the substrate. Each of the pins is connected to a portion of the array of conductive paths. The array of conductive paths is configurable to provide a first electrical flow path through the substrate via a portion of the array of conductive paths or a second electrical flow path through the substrate. The electrical flow path through the substrate may be customizable for testing various die or chip layout designs. The electrical flow path through the substrate may be customizable by laser ablation of portions of the conductive paths, breaking of fuses along the conductive paths, and/or the actuation of logic gates connected to the conductive paths.

Abstract: Apparatuses and methods for forming serial advanced technology attachment (SATA) board edge connectors with electroplated hard gold contacts. One example method can include forming a tie bar on an inner layer of a printed circuit board (PCB), forming a trace on an outer layer of the PCB, forming a via, wherein the via electrically couples the tie bar to the trace, forming a contact coupled to the trace on the outer layer, and sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.

Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.

Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

Abstract: Display systems and related methods involving bus lines with low capacitance cross-over structures are provided. A representative display system includes: a first structure comprising: a plurality of scan lines extending in a first direction; and a plurality of data lines extending in a second direction and crossing over the scan lines at respective cross-over locations, each of the plurality of data lines having a pair of side walls spaced apart from each other at each of the cross-over locations, with each of the side walls exhibiting a height higher than portions of the data lines not located at the cross-over locations.