Abstract: A wiring board includes a core substrate having an opening portion and a through hole adjacent to the opening portion, a capacitor positioned in the opening portion, and a through-hole conductor formed in the through hole of the core substrate and having a conductor filling the through hole. The core substrate has a first surface and a second surface on the opposite side of the first surface, the opening portion of the core substrate penetrates from the first surface to the second surface, the through-hole conductor has a first conductive portion and a second conductive portion connected to the first conductive portion in the core substrate, the first conductive portion of the through-hole conductor becomes narrower from the first surface toward the second surface, and the second conductive portion of the through-hole conductor becomes narrower from the second surface toward the first surface.

Abstract: A substrate includes an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, a chromium conversion coating on at least a portion of the core, and an insulating coating on the chromium conversion coating. A method of making a substrate includes: providing an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, applying a chromium conversion coating on at least a portion of the core, and applying an insulating coating on the chromium conversion coating.

Abstract: A multi-layer printed circuit board including a core substrate, lower interlayer resin insulating layers formed on the surfaces of the core substrate, respectively, through-hole conductors formed in penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers, conductor circuits formed on the lower interlayer resin insulating layers, respectively, upper interlayer resin insulating layers formed on the conductor circuits and the lower interlayer resin insulating layers, respectively and via hole conductors formed in the upper interlayer resin insulating layers and positioned on the through-hole conductors, respectively.

Abstract: A multi-layer printed circuit board including a first insulating layer, a first conductor layer having circuits on one surface of the first insulating layer, a second conductor layer having circuits on the opposite surface of the first insulating layer, a second insulating layer on the second conductor and first insulating layers, and a third conductor layer having circuits on the second insulating layer on the opposite side of the second conductor layer. The first and second insulating layers have first and second via holes formed in openings of the first and second insulating layers and made of conductive materials filling the openings such that circuits in the first and third conductor layers are connected to one or more circuits in the second conductor layer, and the first and second via holes have bottom ends facing the second conductor layer and top ends larger than the bottom ends.

Abstract: A multi-layer printed circuit board includes a core structure including resin layers and conductor circuits sandwiched by the resin layers, the core structure having first and second surfaces, a first conductor layer including conductor circuits on the first surface of the core structure, and a second conductor layer including conductor circuits on the second surface of the core structure. The core structure includes first and via holes, and the first and second via holes include a metal filling up to the respective top of openings in the resin layers, respectively, sandwich one or more conductor circuits in the core structure and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and second conductor layers, and the first and second via holes are deviated from each other in a vertical direction.

Abstract: A Z-directed component for mounting in a mounting hole in a printed circuit board according to one example embodiment includes a body having a top surface, a bottom surface and a side surface. The body has a cross-sectional shape that is insertable into the mounting hole in the printed circuit board. A portion of the body is composed of an insulator. Four conductive channels extend through a portion of the body along the length of the body. The four conductive channels are spaced substantially equally around a perimeter of the body.

Abstract: A Z-directed component for mounting in a mounting hole in a printed circuit board according to one example embodiment includes a body having a top surface, a bottom surface and a side surface. The body has a cross-sectional shape that is insertable into the mounting hole in the printed circuit board. A portion of the body is composed of an insulator. A first conductive channel extends through an interior portion of the body along the length of the body from the top surface to the bottom surface. The first conductive channel forms a signal path through the body. A second conductive channel and a third conductive channel each extends through the interior portion of the body along the length of the body. The second and third conductive channels are positioned next to and on opposite sides of the first conductive channel.

Abstract: Lamination circuit board in which ground and conductor layers are laminated via an electrically insulating layer. Various configurations allow the ground layer to realize characteristic impedance matching in the circuit board: (a) One having at least a removal region where at least a projection region, being the conductor layer orthogonally projected onto the ground layer, is removed; (b) One in which in the lamination the conductor layer, a signal transmission line, and the ground layer are laminated in that order via the electrically insulating layer, and having at least a removal region where the conductor layer and the signal transmission line overlap; and (c) One in which in the lamination a signal transmission line, the ground layer, and the conductor layer are laminated in that order via the electrically insulating layer, and having at least a removal region where the conductor layer and the signal transmission line overlap.

Abstract: An interdigitated electrode film co-extruded with bus bars for thin film electronics or other devices. First electrode layers are located between first and second major surfaces of the film with a first bus bar electrically connecting and integrated with the first electrode layers. Second electrode layers are located between the first and second major surfaces with a second bus bar electrically connecting and integrated with the second electrode layers. The first electrode layers are interdigitated with the second electrode layers, and insulating layers electrically isolate the first bus bar and electrode layers from the second bus bar and electrode layers. The electrode films include multilayer films with vertical bus bars and multilane films with horizontal bus bars.

Abstract: A printed circuit board includes a base substrate, at least one through-hole in the base substrate, a connection tab extending through the through-hole, an electrical element on the base substrate and adjacent to the through-hole, and at least one groove portion in the base substrate and adjacent to the electrical element.

Abstract: A multilayer composite electronic structure comprising at least two feature layers extending in an X-Y plane and separated by a via layer comprising a dielectric material that is sandwiched between two adjacent feature layers, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, wherein a first via has different dimensions in the X-Y plane from a second via in the via layer.

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 ?m, the dielectric layer has a thickness of from 0.3 to 5 ?m, and the conductor layer has a thickness of from 0.3 to 10 ?m. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 ?m, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 ?m, and a minimum via pitch is from 100 to 350 ?m.

Abstract: A memory system is provided with a motherboard, and a memory controller and a plurality memory devices mounted on the motherboard. The motherboard comprises a unicursal-shape main wiring, and branch wirings branched from the main wiring to the respective memory devices. Further, the motherboard comprises an open stub wiring branched from a connecting point between a start end and a branch point of the main wiring. Thus, a ringing of a waveform of a signal received by a receiving circuit can be suppressed irrespective of a wiring length of the branch wiring.

Abstract: A wiring board includes a base in which plate wirings formed of a metal plate are integrally formed with an insulating portion made of resin or a resin composition and surface wirings electrically connected to the plate wirings. The base has first and second surfaces on which the surface wirings are formed. The surface wirings are thinner than the plate wirings, and the minimum wiring gap between the surface wirings is smaller than the minimum wiring gap between the plate wirings. One of the plate wirings has substantially the same shape as that of a region where the first top-surface wiring on the first surface and the first bottom-surface wiring on the second surface overlap with each other in the normal direction of the first surface. The first top-surface wiring and the first bottom-surface wiring are connected to each other through the above-mentioned one of the plate wirings.

Abstract: A circuit board is provided which includes a plurality of signal pairs of connectors. The signal pairs of connectors are disposed in a triangular grouping of three signal pairs of connectors such that a first connector of each signal pair is located at a vertex of the triangular grouping. A second connector of each signal pair is located at a side of the triangular grouping adjacent to the vertex of the first connector. The signal pairs may be differential pairs.

Abstract: An insulating layer is formed on a support substrate having a conductive property. Write wiring traces, read wiring traces, and first and second electrode pad pairs are formed on the insulating layer. The first electrode pad pair is connected to the write wiring traces. The second electrode pad pair is connected to the read wiring traces. Parts of regions of the support substrate, which overlap the electrode pads, are removed. Thus, openings are formed in the regions of the support substrate, which overlap the electrode pads.

Abstract: A method of manufacturing a multi-layer printed wiring board including forming a core substrate, forming a first interlayer insulation layer over the core substrate, forming a first filled via in the first interlayer insulation layer, the first filled via having a bottom portion having a first diameter, forming a second interlayer insulation layer over the first interlayer insulation layer, and forming a second filled via in the second interlayer insulation layer, the second filled via having a bottom portion having a second diameter smaller than the first diameter.

Abstract: A wiring board according to an embodiment includes an inorganic insulating layer provided with a via-hole which is a penetrating hole, and a via-conductor which is a penetrating conductor disposed inside the via-hole. The inorganic insulating layer includes first inorganic insulating particles connected to each other and second inorganic insulating particles that are larger in particle size than the first inorganic insulating particles and are connected to each other via the first inorganic insulating particles, and also has, at an inner wall of the via-hole V, a protrusion including at least part of the second inorganic insulating particle. The protrusion is covered with the via-conductor.

Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract: A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.

Abstract: There is provided a wiring board including a first stiffener, one face of which is bonded to a circuit board, a second stiffener having a disposition hole in which an electronic component is disposed, and a laminate that is formed by laminating a plurality of insulating layers and a plurality of wiring layers between the other face of the first stiffener and one face of the second stiffener, and includes a terminal connection part that is connected to the wiring layers, positioned in the disposition hole, and connected to a terminal part of the electronic component.

Abstract: A printed circuit board (PCB) includes a ground layer, a first layer, a second layer, a connector footprint, and a pair of differential signal lines. The connector footprint comprises first and second bonding pads. The PCB defines a first signal via in a central portion of a space bound by the first bonding pad, and a second signal via in a central portion of a space bound by the second bonding pad. A number of first ground vias on the first bonding pad and a number of second ground vias on the second bonding pad are electrically connected to the ground layer. First annular slots surrounding corresponding first ground via are defined in the ground layer. Second annular slots surrounding corresponding second ground vias are defined in the ground layer. Connection slots are defined in the ground layer and communicate between the first annular slots and the second annular slots.

Abstract: The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.

Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract: An improved multi-layered ceramic package includes a plurality of signal planes, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; and at least one reference mesh plane adjacent to one or more signal planes. The reference mesh plane includes spaced mesh lines that are separated by spaces that alternate in a narrow-wide or wide-narrow pattern. A multi-layered ceramic package using the mesh plane with alternating spaces generates significantly lower far-end (FE) noise in the ceramic package than a conventional mesh plane with constant spaces. The noise is further reduced by placing shield lines on opposite sides of signal lines in the signal plane.

Abstract: An electronic component that can be mounted with good balance includes a substrate, a plurality of first terminals located on a peripheral portion of one main surface of the substrate, a ground electrode located in a center of the one main surface of the substrate and including openings, and at least two second terminals located on the one main surface of the substrate and within the openings of the ground electrode and that are electrically isolated from the ground electrode. The second terminals are arranged at positions that are point symmetrical about a center of the ground electrode.

Abstract: A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.

Abstract: A wiring board includes a first wiring line and a second wiring line formed on a substrate, a first land and a second land respectively formed at a connection portion of the first wiring line and the second wiring line. A second wiring line has a longer wiring length than the first wiring line. The land is structured with a wiring pattern of a single wiring line. The wiring board also includes a first pad electrode and a second pad electrode respectively formed on the first land and a second land through an insulating film, a first interlayer connection via and a interlayer connection via embedded in the insulating film and electrically connecting the land to the pad electrode. And a wiring length of the wiring pattern of the first land is longer than the wiring length of the wiring pattern of the second land.

Abstract: A printed circuit board includes an upper circuit layer including a circuit pattern embedded in an upper part of an insulating layer, the circuit pattern being made of electroconductive metal; and a metal bump formed on the circuit pattern and the insulating layer

Abstract: A Z-directed signal delay line component for insertion into a printed circuit board while allowing electrical connection to internal conductive planes contained with the PCB. In one embodiment the Z-directed delay line component is housed within the thickness of the PCB allowing other components to be mounted over it. The delay line embodiments include a W-like line and a plurality of spaced apart, semi-circular line segment connected such that current flow direction alternates in direction between adjacent semi-circular line segments, each of which in other embodiments can be varied by use of shorting bars. Several Z-directed delay line components may be mounted into a PCB and serially connected to provide for longer delays. The body may contain one or more conductors and may include one or more surface channels or wells extending along at least a portion of the length of the body.

Abstract: A laminated composite assembly includes a layer having a first conductor with a first side and a second side. A first electric insulator is disposed between the first side of the first conductor and a second conductor such that a difference between a voltage associated with the first conductor and a voltage associated with the second conductor defines a voltage stress therebetween. The first electric insulator providing a first degree of electrical isolation based on the voltage stress. A second electric insulator is disposed between the second side of the first conductor and a third conductor such that a difference between the voltage associated with the first conductor and a voltage associated with the third conductor defines a second voltage stress therebetween. The second electric insulator providing a second degree of electrical isolation based on the second voltage stress.

Abstract: A wiring board with a built-in electronic component includes a substrate having an opening portion and having a first surface and a second surface on the opposite side of the first surface, and an electronic component having a third surface and a fourth surface on the opposite side of the third surface and positioned in the opening portion of the substrate such that the third surface faces the same direction as the first surface of the substrate. The electronic component has a curved surface joining the fourth surface and a side surface of the electronic component, and the opening portion of the substrate has a tapered portion formed by a tapered surface of the substrate joining an inner wall of the opening portion and the first surface and tapering from the first surface toward the second surface.

Abstract: A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Abstract: A motherboard includes a printed circuit board (PCB), a central processing unit (CPU), a regulator, a first memory adaptor, and a second memory adaptor. The PCB includes a top surface, a bottom surface, a plurality of first soldering pads and first leads arranged on the top surface, and a plurality of second leads arranged between the top surface and the bottom surface. The PCB defines a plurality of first vias, second vias, and power vias. The CPU is connected to the first vias. The voltage regulator is connected to the power vias. The first memory adaptor neighbors to the regulator and is surface-mount soldered to the first soldering pads. The first soldering pads are connected to the first vias by first leads. The second memory adaptor is soldered to the second vias. The second vias are connected to the first vias by the second leads.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: An electrical assembly having controlled impedance signal traces and a portable electronic device comprising an electrical assembly having controlled impedance signal traces are provided. In accordance with one embodiment, there is provided a portable electronic device, comprising an electrical assembly, comprising: a chassis made from a conductive material and forming a first ground plane; a first dielectric substrate layer overlaying the chassis; a first signal trace overlaying the first dielectric substrate layer; and a second dielectric layer overlaying the first signal trace.

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract: A wiring board includes a first substrate portion including a first feed-through conductor portion in a vertical direction, a second substrate portion provided on the first substrate portion and including a second feed-through conductor portion in a vertical direction of a corresponding part to the first feed-through conductor portion, and a feed-through electrode including the first feed-through conductor portion and the second feed-through conductor portion.

Abstract: An electronic product includes a case; a first board placed inside the case; and a second board having an Electromagnetic Band Gap (EBG) structure inserted therein. The second board is coupled to an inside of the case facing the first board so as to shield a noise radiated from the first board.

Abstract: The embodiments described herein provide for a packaging configuration that provides leads or connections for a packaging substrate from opposing surfaces of a package. Through silicon vias (TSV) are provided in order to accommodate additional input/output (I/O) pins that smaller dies are supporting. Various combinations of packages are enabled through the embodiments provided.

Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures.

Abstract: In the present invention, generation of occurrence of a wiring area is prevented, and a reflection by an inconsistency of a characteristic impedance of a high-speed signal line and a through hole connecting portion. By doing so, a conductor pattern of a raised shape is formed on each of front and back of a through hole, on a GND layer closest to the high-speed signal line in the vicinity of the connecting portion of the high-speed signal line and the through hole. Further, the conductor pattern is a trapezoidal shape, and is a shape which becomes wider as it becomes closer to the through hole.

Abstract: Methods for the formation of single-cap VIPs in a substrate are described herein. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.

Abstract: A method for manufacturing a printed wiring board includes preparing a metal sheet having metal members and connectors joining the metal members, forming a structure having core substrates which are connected through the connectors and which have insulation structure portions covering the metal members, respectively, cutting the connectors in the structure such that an independent core substrate having a recessed portion is formed and a respective one of the connectors is removed from the independent core substrate, and covering the recess portion of the independent core substrate with a resin. The covering of the recess portion includes either forming an interlayer insulation layer on a surface of the independent core substrate or forming interlayer insulation layers on opposing surfaces of the independent core substrate.

Abstract: A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

Abstract: A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

Abstract: The present invention relates to a circuit board. A circuit board in accordance with an embodiment of the present invention includes a base substrate; an interlayer insulating layer covering the base substrate; a via structure passing through at least the interlayer insulating layer of the base substrate and the interlayer insulating layer in the vertical direction; and an etch stop pattern disposed on the interlayer insulating layer in the horizontal direction to surround the via structure and made of an insulating material.