Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

Abstract: A battery pack configured to prevent excess solder material from flowing down onto a protective circuit module (PCM) is disclosed. According to some aspects, the battery pack includes at least one battery cell, a protective circuit module (PCM) electrically connected to the battery cell, and a conductive tab configured to electrically connect the battery cell to the PCM. A tapered through hole is formed in the PCM so that the conductive tab is inserted into and fixed to the through hole.

Abstract: An electronic apparatus (100) has an electronic device (151), a power supply plane (121) and a power supply plane (122) disposed with a gap (123) therebetween, a connection member (152) that electrically connects the power supply plane (122) and the electronic device (151), a ground plane (141) facing the power supply plane (121) or the power supply plane (122), a connection member (153) that electrically connects the ground plane (141) and the electronic device (151), a plurality of conductor elements (131) that is repeatedly arrayed, and open stubs (111) formed at a location overlapping the gap (123) included in an area surrounded by the conductor elements (131). In addition, at least some of the open stubs (111) face the power supply plane (122) which is not in contact with the open stubs (111).

Abstract: One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath.

Abstract: A lead electrode and a preparation method thereof are provided. The lead electrode includes an inner terminal, a lead, and an outer terminal, which are sequentially connected. The lead includes: an insulating substrate; an adhesive material coated on the insulating substrate, the adhesive material defining a trenched mesh; and a conductive material filled in the trenched mesh, wherein an angle formed by a grid line of the trenched mesh and a demolding direction is from 0° to 90°. Since the angle formed by the grid line and the demolding direction is very small, little adhesive material will be attached to the mold, such that the residues of the adhesive material are prevented.

Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.

Abstract: A wiring substrate is provided with a support substrate (31), an insulating layer (32), and a wiring layer (33). The support substrate (31) is formed with a hole (34) including an opening portion in one surface of the support substrate (31). The insulating layer (32) is formed on a surface of the support substrate (31) opposite to the one surface thereof including the opening portion. The wiring layer (33) includes a wiring pattern of a predetermined structure on the insulating layer (32). Further, an orthographic projection to be obtained when the wiring pattern is projected on a predetermined surface of the support substrate (31), and an orthographic projection to be obtained when the hole (34) is projected on the predetermined surface of the support substrate (31) include a shared portion.

Abstract: A multilayer printed wiring board includes a multilayered structure having conductor circuit layers and interlaminar insulative layers, the interlaminar insulative layers including an outermost interlaminar insulative layer, the conductor circuit layers including an outermost conductor circuit layer formed over the outermost interlaminar insulative, a filled-viahole formed in the outermost interlaminar insulative layer and having one or more metal plating fillings and completely closing a hole formed through the outermost interlaminar insulative layer such that the metal plating of the filled-viahole extends out of the hole and forms a substantially flat surface, and solder bumps including a first solder bump formed on the substantially flat surface of the filled-viahole and a second solder bump formed on a surface portion in the outermost conductor circuit layer.

Abstract: A wiring board for an electronic parts inspecting device that can be designed and produced relatively quickly, inexpensively, and with a few number of jigs is provided. In certain embodiments the wiring board comprises a board main body having a front surface, a probe pad area having probe pads located in a central portion of the front surface, an outer connecting terminal area having outer connecting terminals located in a peripheral portion of the front surface, and wherein probe pads are connected to outer connecting terminals by front surface wirings formed between the probe pad area and the outer connecting terminal area. While certain embodiments further comprise inner wirings and first via conductors to connect the probe pads and outer connecting terminals, it is preferable to have no or a minimal amount of such inner wirings. Lastly, a method of manufacturing the same is provided.

Abstract: A printed circuit board includes a line intensive distribution area, a line sparse distribution area, a solder mask layer, and a signal layer. A first signal line is laid on the signal layer. The first signal line crosses the line intensive distribution area and the line sparse distribution area. The first signal line is narrower in the line intensive distribution area than in the line sparse distribution area. The solder mask layer is thicker in the line intensive distribution area than in the line sparse distribution area.

Abstract: A method for manufacturing a printed circuit board with cavity includes following steps. First, a first substrate is provided. The first substrate includes a first electrically conductive layer defining an exposed portion and a laminating portion. Second, a second substrate is provided. The second substrate includes an unwanted portion corresponding to the exposed portion and a preserving portion. Third, a first annular bump surrounding the exposed portion is formed. Fourth, a second annular bump surrounding the unwanted portion is formed. Fifth, a first adhesive layer defining an opening is provided. Sixth, the first and second substrates are laminated to the first adhesive layer, the exposed portion and the unwanted portion are exposed in the opening, and the second annular bump is in contact with the first annular bump. Seventh, the unwanted portion is removed and a cavity is defined, the exposed portion is exposed in the cavity.

Abstract: Provided is a printed circuit board (PCB) used as a signal transmission line of a terminal, comprising a first ground layer elongating in one direction, a first dielectric layer deposited on a top of the first ground layer and elongating in the same direction as the first ground layer, a signal transmission line deposited on a top of the first dielectric layer and elongating in the same direction as the first dielectric layer, a ground pad elongating from one end of the first ground layer and in contact with an external ground, and a signal line pad extended from one end of the signal transmission line and in contact with an external signal line.

Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract: The described embodiments relate generally to electronic devices and to three dimensional modules for increasing useable space on a circuit board associated therewith. In some embodiments, the modules can have a cuboid geometry, and can include a number of surfaces having embedded circuit traces configured to interconnect electronic components arranged on various surfaces of the module. One of the surfaces of module can include at least one communication interface configured to interconnect the circuit traces on the module to associated circuit paths on a circuit board to which the module is coupled. In some embodiments the module can be operative as a standoff between the circuit board and another component of the electronic device.

Abstract: Printed circuits may be electrically and mechanically connected to each other using connections such as solder connections. A first printed circuit such as a rigid printed circuit board may have solder pads and other metal traces. A second printed circuit such as a flexible printed circuit may have openings. Solder connections may be formed in the openings to attach metal traces in the flexible printed circuit to the solder pads on the rigid printed circuit board. A ring of adhesive may surround the solder connections. The flexible printed circuit may be attached to the rigid printed circuit board using the ring of adhesive. An insulating tape may cover the solder connections. A conductive shielding layer with a conductive layer and a layer of conductive adhesive may overlap the solder joints. The conductive adhesive may connect the shielding layer to the metal traces on the rigid printed circuit board.

Abstract: A wiring board includes a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on a surface of the first substrate and including interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including conductive circuits for being connected to semiconductor elements, a filler filling the opening portion such that the interposer is held in the opening portion of the built-up layer, and mounting pads formed on the first substrate and positioned to mount the semiconductor elements. The mounting pads are positioned to form a matrix on the first substrate.

Abstract: An intercoupling component is provided which permits reliable, non-permanent electrical connection between a first substrate and a second substrate. The intercoupling component includes a socket terminal having a first end, and a second end opposed to the first end. An axial hole extends inward from the second end, and an electrically conductive core member is disposed within the axial hole. The core member is formed of a different material than the socket terminal body, and is sized and shaped to obstruct the hole. In addition, the first end of the socket terminal is configured to receive a pin terminal, and the second end of the socket terminal is configured to be received within a hole in a printed circuit board.

Abstract: A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.

Abstract: A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.

Abstract: Disclosed herein are a laminate for a printed circuit board, a printed circuit board using the same, and a method of manufacturing the same. The laminate for a printed circuit board includes: a first insulating film; and a second insulating film formed on the first insulating film, wherein a content of a reaction accelerator in the first insulating film is different from that of the second insulating film.

Abstract: A structure (10) includes: a molded object 2 having a through hole (1); a conduction pattern (3) electrically connecting two surfaces having respective openings of the through hole (1), the conductive body (3) being provided on an inner wall of the through hole (1); and an elastic body (4) being filled in the through hole (1), the elastic body (4) being made of a substance that is deformed by an external pressure more easily than the molded object (2).

Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.

Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.

Abstract: A device for screening an electronic module which has electronic components fixed to a printed circuit board and which is connected to a heat sink. The heat sink comprises an electrically conductive material. The printed circuit board has at least one layer composed of electrically conductive material. The heat sink and the printed circuit board serve as screening elements.

Abstract: A process of copper plating a through-hole in a printed circuit board, and the printed circuit board made from such process. The process comprises: providing a printed circuit board with at least two copper interconnect lines separated by an insulator in the vertical direction; providing a through-hole in the printed circuit board in the vertical direction such that the interconnect lines provide a copper land in the through-hole; applying a seed layer to an interior surface of the through-hole; removing an outermost portion of the seed layer from the interior surface of the through-hole with a laser; applying copper on the seed layer.

Abstract: A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed.

Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.

Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component (1) with contact terminals (2) and conducting lines (4) in a first wiring layer (3). There is also a dielectric (5) between the component (1) and the first wiring layer (3) such that the component (1) is embedded in the dielectric (5). Contact elements (6) provide electrical connection between at least some of the contact terminals (2) and at least some of the conducting lines (4). The electronic module also comprises a second wiring layer (7) inside the dielectric (5). The second wiring layer (7) comprises a conducting pattern (8) that is at least partly located between the component (1) and the first wiring layer (3) and provides EMI protection between the component (1) and the conducting lines (4).

Abstract: The present invention concerns a printed circuit board, PCB. The PCB comprises a number of signal layers comprising routing channels and at least one ground layer being adjacent to at least one signal layer. A number of via holes connects different signal layers of the PCB. In the signal layers the via holes are connected to pads and in the ground layers they are be surrounded by anti-pads. The pads are shaped such that at least a part of a via hole connected to the pad is on the outside of, or in close proximity to, the edge of the pad, irrespective of where on the pad the centre of the via hole is positioned.

Abstract: In a multilayer board, a stacked body includes thermoplastic resin films and low-fluidity resin films with conductive patterns, which are alternately stacked. The stacked body and a resin base film are integrated by hot pressing. The base film has a terminal-connecting through hole for receiving an electrode terminal of an electronic component to be connected to a conductive pattern of the low-fluidity resin film disposed at an end of the stacked body. An electronic component mounting section of the stacked body, which is an area corresponding to the electronic component mounted on the base film in a stacking direction, is configured such that a number of the conductive patterns located in a corresponding section that corresponds to the through hole in the stacking direction is greater than a number of the conductive patterns located in a non-corresponding section without corresponding to the through hole in the stacking direction.

Abstract: A printed circuit board (PCB) backdrilling method is disclosed, where a conductive layer is disposed between a surface of a PCB on an intended-for-backdrilling side of a plated through hole (PTH) and a target signal layer of the PCB, and the method includes: performing a first backdrilling on the PTH with a first preset depth starting from the surface of the PCB; controlling the backdrill bit to move along the drill hole formed in the first backdrilling toward the target signal layer; and when the backdrill bit is in contact with the conductive layer, completing a second backdrilling with a second preset depth starting from the conductive layer.

Abstract: The invention relates to a printed circuit for high-frequency signals, and more particularly to interconnect means between transmission lines situated on different faces of the printed circuit. According to the invention, in the vicinity of the interconnect means, the transmission lines each extend in a main direction. The interconnect means comprise two vias each extending along an axis. In a plane containing the main direction of a first of the transmission lines and perpendicular to the face bearing the first transmission line, an orthogonal fix is formed whose abscissa is borne by the main direction of the first transmission line. The abscissae of the axes of the vias or of their projection on the plane, perpendicularly to the plane, are separate.

Abstract: The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Abstract: A printed circuit board of the present invention includes a base body, a through-hole that penetrates through the base body in the thickness direction, and a through-hole conductor that covers an inner wall of the through-hole. The base body has a fiber layer including a plurality of glass fibers and a resin that covers the plurality of glass fibers. The glass fibers have a groove-shaped concavity on a surface exposed to the inner wall of the through-hole. The concavity is filled with a part of the through-hole conductor.

Abstract: A printed wiring board includes a substrate having an accommodation section having multiple opening portions, multiple electronic components accommodated in the opening portions, respectively, a filler resin provided in the opening portions in the substrate such that the electronic components are secured in the opening portions in the substrate, a resin insulation layer formed over the substrate and the electronic components, a conductive layer formed on the resin insulation layer, and via conductors formed in the resin insulation layer and connecting the conductive layer and the electronic components. The opening portions are connected to each other.

Abstract: In some embodiments, a printed circuit board, configured to be coupled to electronic components, includes a first material portion and any number of second material portions. Each second material portion is sized and spaced apart from an adjacent second material portion such that electromagnetic waves associated with the operation of the electronic components are substantially not reflected. The first material portion defines a first dielectric constant and the second material portion defines a second dielectric constant that is different than the value of the first dielectric constant.

Abstract: A method, and structures for implementing enhanced interconnects for high conductivity applications. An interconnect structure includes an electrically conductive interconnect member having a predefined shape with spaced apart end portions extending between a first plane and a second plane. A winded graphene ribbon is carried around the electrically conductive interconnect member, providing increased electrical current carrying capability and increased thermal conductivity.

Abstract: An EMI noise reduction package board, having a top layer and a bottom layer, one of which having a semiconductor device mounted thereon, can include: a first area having a signal layer arranged on one surface thereof; and a second area placed on a lateral side of the first area and having unit structures arranged repeatedly therein, the unit structures configured for inhibiting EMI noise from being radiated to an outside through the lateral side of the first area. The unit structure can include: a top conductive plate and a bottom conductive plate, formed, respectively, on the top layer and the bottom layer of the second area to face each other in a pair; and a via, connecting the top conductive plate with the bottom conductive plate.

Abstract: A component-incorporated wiring substrate is provided. Some embodiments include a plate-like component incorporated in a core substrate and a build-up layer having an insulation layer and a conductor layer disposed in alternating layers. The component has terminal electrodes formed at its opposite ends having a side surface and a main surface. An insulation layer disposed on the main surface of the component has via conductors formed therein which are connected to the side surfaces and the main surfaces of the respective terminal electrodes. The via conductors are tapered, such that their via diameter decreases in a direction toward the terminal electrode, and their via diameter at a position where they connect to the main surface is greater than a length of the main surface. Accordingly, the area of connection between the via conductors and the corresponding terminal electrodes is increased, improving connection reliability through enhancement of tolerance for positional deviation.

Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal carrier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

Abstract: An electric connecting structure comprising preferred oriented Cu6Sn5 grains and a method for fabricating the same are disclosed. The method of the present invention comprises steps: (A) providing a first substrate; (B) forming a first nano-twinned copper layer on part of a surface of the first substrate; (C) using a solder to connect the first substrate with a second substrate having a second electrical pad, in which the second electrical pad comprises a second nano-twinned copper layer, and the solder locates between the first nano-twinned copper layer and the second nano-twinned copper layer; and (D) reflowing at the temperature of 200° C. to 300° C. to transform at least part of the solder into an intermetallic compound (IMC) layer, in which the IMC layer comprises plural Cu6Sn5 grains with a preferred orientation; wherein at least 50% in volume of the first and second nano-twinned copper layer comprises plural grains.

Abstract: Embodiments of the present invention provide a multi layered printed circuit board, PCB, with via holes connecting different signal layers of the PCB. The via holes are connected to pads in the signal layers and are surrounded by anti-pads in the ground layers. In accordance with further embodiments of the invention the pads have a shape wherein a first path, stretching from the center of the pad and substantially in a direction in which adjacent routing channels extend, to a first point located on the edge of the pad, is longer than a second path, stretching from the center of the pad and substantially in a direction towards the adjacent routing channels to a second point located on the edge of the pad.

Abstract: A structural body includes: a first conductor and a second conductor of which at least portions are opposite to each other; a third conductor, interposed between the first conductor and the second conductor, of which at least a portion is opposite to the first conductor and the second conductor, and has a first opening; an interconnect provided in the inside of the first opening; and a conductor via which is electrically connected to the first conductor and the second conductor and is electrically insulated from the third conductor, wherein the interconnect is opposite to the first conductor and the second conductor, one end thereof being electrically connected to the third conductor at an edge of the first opening and an other end thereof being formed as an open end.

Abstract: A printed circuit board (PCB) structure comprises two signal layers with and a ground layer sandwiched between the two signal layers, and at least two adjacent vias. Each of the signal layers comprises a plurality of signal traces. The via through the PCB structure is used for connecting signal traces on different signal layers together. The ground layer comprises at least one insulation region. Each of the vias comprises at least two pads and a connecting portion connecting the at least two pads together. The pads are respectively mounted on the at least two signal layer. Projections of the adjacent pads on the ground layer are contained in the same insulation region.

Abstract: A high-frequency signal transmission line includes a dielectric element assembly including a plurality of dielectric layers laminated on each other, a linear signal line provided at the dielectric element assembly, and a first ground conductor provided on a first side in a direction of lamination relative to the signal line and including a plurality of openings arranged along the signal line. The dielectric layer positioned at an end of the first side in the direction of lamination includes an undulating portion provided on a first principal surface located on the first side in the direction of lamination, such that the undulating portion overlaps with the openings when viewed in a plan view in the direction of lamination.

Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.

Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.

Abstract: The method for producing a patterned layer of first material on a surface of a substrate comprises the following successive steps: arranging a particle on the surface of the substrate; depositing a resin by spin coating on the surface of the substrate so as to form the patterned layer of first material and a hole passing through the layer of first material and opening onto the particle; the material of the particle and the resin being chosen such that the particle exerts a repulsive interaction with respect to the resin.

Abstract: Disclosed herein is a printed circuit board having electronic components embedded therein. The printed circuit board having electronic components embedded therein includes: a metal core layer connected to a ground terminal of an external power supply to be grounded and having a cavity or a groove part formed thereon; an electronic component accommodated in the cavity and having a plurality of terminals, a ground terminal included in the plurality of terminals being connected to the metal core layer; an internal insulating layer stacked on both sides of the metal core layer; and circuit patterns formed on an external surface of the internal insulating layer.