Feedthrough Patents (Class 174/262)
  • Publication number: 20150027769
    Abstract: The method for producing a patterned layer of first material on a surface of a substrate comprises the following successive steps: arranging a particle on the surface of the substrate; depositing a resin by spin coating on the surface of the substrate so as to form the patterned layer of first material and a hole passing through the layer of first material and opening onto the particle; the material of the particle and the resin being chosen such that the particle exerts a repulsive interaction with respect to the resin.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Thomas SEBASTIEN, Messaoud BEDJAOUI, Aboubakr ENNAJDAOUI
  • Patent number: 8942004
    Abstract: Disclosed herein is a printed circuit board having electronic components embedded therein. The printed circuit board having electronic components embedded therein includes: a metal core layer connected to a ground terminal of an external power supply to be grounded and having a cavity or a groove part formed thereon; an electronic component accommodated in the cavity and having a plurality of terminals, a ground terminal included in the plurality of terminals being connected to the metal core layer; an internal insulating layer stacked on both sides of the metal core layer; and circuit patterns formed on an external surface of the internal insulating layer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: January 27, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Chang Hong, Bong Kyu Choi, Je Gwang Yoo, Sang Wuk Jun, Sang Kab Park, Jung Soo Byun
  • Patent number: 8941016
    Abstract: A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the conductor circuit by allowing electrodes of the electronic component to be connected to the conductors; an embedding member arranged around the electronic components so that the electronic component is embedded therein; and a second substrate having an adhesive layer laminated to face the adhesive layer of the first substrate and sandwich the electronic component and the embedding member, wherein each of the electrodes of the electronic component is continuous with the conductor circuit through two or more of the conductors.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 27, 2015
    Assignee: Fujikura Ltd.
    Inventor: Masahiro Okamoto
  • Publication number: 20150021074
    Abstract: Disclosed herein is a printed circuit board capable of implementing slimness by decreasing the number of entire layers through an asymmetrical build-up structure in which an electric device is embedded, the printed circuit board including: a core layer including a cavity formed therein so that an electric device is embedded and a circuit pattern and a pad formed on upper and lower surfaces thereof; a through via formed in the core layer so as to connect the upper and the lower pads of the core layer to each other; a plurality of insulating layers built-up on the core layer and including a plurality of vias so as to be electrically connected to the through via; and a solder resist layer applied onto a lower portion of the core layer so that a lower surface of the through via is partially exposed.
    Type: Application
    Filed: June 6, 2014
    Publication date: January 22, 2015
    Inventors: Sang Hoon KIM, Tae Hong MIN, Jung Han LEE, Hye Jin KIM
  • Publication number: 20150021084
    Abstract: Disclosed herein are a copper clad laminate, a printed circuit board, and a method of manufacturing the same. The copper clad laminate includes: an insulating layer having one surface and the other surface; and first and second copper foil layers having one surface, which is a smooth surface, and the other surface, which is a rough surface having a roughness larger than that of the smooth surface, respectively, wherein one surface of the insulating layer contacts the rough surface of the first copper foil layer and the other surface of the insulating layer contacts the smooth surface of the second copper foil layer.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 22, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Ho Ko, Chang Jae Lee, Jun Ho Kang, Seok Jun Ahn
  • Patent number: 8937255
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 20, 2015
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Publication number: 20150014042
    Abstract: A laminated electronic component is configured such that insulator layers and conductor patterns are laminated and a coil is formed in a laminate of the insulator layers and the conductor patterns by connecting the conductor patterns among the insulator layers, where the coil includes conductor pattern pairs each composed of two conductor patterns arranged so as to sandwich each insulator layer, and includes a first connecting portion connecting both end portions of the two conductor patterns so as to connect the two connecting patterns in parallel and a second connecting portion connecting a plurality of the conductor pattern pairs in series, where the first connecting portion and the second connecting portion are arranged so as to be displaced from each other in a direction of a line length of a coil pattern.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 15, 2015
    Inventors: Yutaka Noguchi, Makoto Yamamoto, Takeshi Kobayashi
  • Publication number: 20150016082
    Abstract: A printed circuit board includes an insulating layer; a via in the insulating layer, a first circuit layer formed at a first side of the insulating layer and having a portion buried in the via; a second circuit layer formed at a second side of the insulating layer and electrically connected with the portion of the first circuit layer in the via.
    Type: Application
    Filed: June 10, 2014
    Publication date: January 15, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Jae Soo LEE
  • Patent number: 8933556
    Abstract: A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from the first surface toward the second surface. The first insulation layer has a first hole which penetrates through the first insulation layer and includes a first conductor made of a plating in the first hole. The second insulation layer has a second hole which penetrates through the second insulation layer and includes a second conductor made of a conductive paste in the second hole. The third insulation layer has a third hole which penetrates through the third insulation layer and includes a third conductor made of a plating in the third hole. The first, second and third conductors are positioned along the same axis and are electrically continuous with each other.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: January 13, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Nobuyuki Naganuma, Michimasa Takahashi, Masakazu Aoyama
  • Patent number: 8933345
    Abstract: A silicon interposer has a plurality of conductive vias extending from a first side of a silicon substrate to an opposite side of the silicon substrate. A plurality of first side scan chain links are disposed on the first side of the silicon substrate. Each scan chain link electrically connects two conducting vias of the plurality of the conductive vias together. In some cases, a test fixture connects the opposite side of the conductive vias together and continuity or resistance is measured. In other cases, scan chain links are formed on the opposite side of the wafer to form a scan chain, which is electronically tested.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 13, 2015
    Assignee: Xilinx, Inc.
    Inventor: Arifur Rahman
  • Publication number: 20150008023
    Abstract: A conducting film or device electrode includes a substrate and two transparent or semitransparent conductive layers separated by a transparent or semitransparent intervening layer. The intervening layer includes electrically conductive pathways between the first and second conductive layers to help reduce interfacial reflections occurring between particular layers in devices incorporating the conducting film or electrode.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Manoj Nirmal, Stephen P. Maki, Jason C. Radel, Robert L. Brott, Donald J. McClure, Clark I. Bright
  • Patent number: 8929092
    Abstract: A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: January 6, 2015
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Patent number: 8927879
    Abstract: A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jinwoo Choi, Sungjun Chun, Jason L. Frankel, Paul R. Walling, Roger D. Weekly
  • Patent number: 8929091
    Abstract: A method of manufacturing a printed circuit board (PCB) having an embedded bare chip includes attaching a tape to one side of an insulated substrate having a penetration hole formed therein, and attaching the bare chip onto the tape inside the penetration hole such that electrode pads of the bare chip face the tape; filling up the penetration hole with a filler, and removing the tape; laminating a metal layer onto a surface of the filler and the insulated substrate from which the tape is removed; and forming electrode bumps by removing portions of the metal layer. The forming of electrode bumps further includes simultaneously removing portions of the metal layer and forming an circuit pattern on one side of the insulated substrate. The circuit pattern is formed directly on the upper side of the insulated substrate and the electrode bumps are formed on the surface of the electrode pads.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 6, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyung-Jin Han, Hyung-Tae Kim, Moon-Il Kim, Jae-Kul Lee, Doo-Hwan Lee
  • Patent number: 8929090
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventors: Yoshiki Nakashima, Shintaro Yamamichi, Katsumi Kikuchi, Kentaro Mori, Hideya Murai
  • Publication number: 20150000969
    Abstract: An array substrate, comprising: a substrate; a metal pattern formed on the substrate; an insulation layer formed on the metal pattern and formed with a via therein; and a transparent conductive pattern formed on the insulation layer and electrically connected to the metal pattern through the via, wherein the via has a cross section exhibiting an irregular geometry shape having a curved side edge.
    Type: Application
    Filed: March 11, 2014
    Publication date: January 1, 2015
    Applicants: BOE Technology Group Co., LTD., Hefei BOE Optoelectronics Technology Co., LTD.
    Inventors: Qingchao Meng, Kiyoung Kwon, Chengda Zhu, Baoquan Zhou
  • Publication number: 20150000970
    Abstract: A wiring board includes an insulating layer having a lower layer conductor on a lower surface thereof, a plurality of semiconductor element connection pads arranged in a lattice pattern in a semiconductor element mounting portion 1a having a quadrangular shape on the insulating layer, a via hole formed in the insulating layer below each of the semiconductor element connection pads, and a via conductor filled in the via hole and formed integrally with each of the semiconductor element connection pads. The wiring board includes a reinforcing via hole formed in the insulating layer in an outer region outside an arrangement region of the semiconductor element connection pads in corner portions of the semiconductor element mounting portion, and a reinforcing via conductor formed in the reinforcing via hole.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Applicant: KYOCERA SLC Technologies Corporation
    Inventors: Masakazu IINO, Teruya FUJISAKI, Takafumi OYOSHI
  • Patent number: 8918990
    Abstract: A method of forming solder-less printed wiring boards includes attaching a electronic components to a workpiece using an adhesive material. A mold material is added to partially cover the electronic components to form a sub-assembly including the electronic components attached to the mold material and a planar surface on the workpiece side. At least tops of the electronic components extend beyond a height of the mold material. The adhesive material is removed to separate the workpiece and sub-assembly. A first prepreg dielectric is attached to the planar surface of the mold material. First vias are formed in the first prepreg dielectric to expose bondable contacts of the electronic components. The first vias are filled with electrically conductive plugs to provide connections to the bondable contacts of the electronic components. A circuit layer is formed on a surface of the first prepreg dielectric to provide contact to the first plugs.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: December 30, 2014
    Assignee: Lockheed Martin Corporation
    Inventor: Gary J. Schreffler
  • Patent number: 8918991
    Abstract: The present invention relates to circuit boards and, more specifically, a process for providing electrical connections with reduced via capacitance on circuit boards. In one embodiment, the present invention provides a method for providing an electrical connection between traces disposed on different layers of a circuit board, the method comprising forming in the board a via hole that extends between the different layers and interconnects a pair of electrically conductive traces disposed on the different layers. An inner sidewall of the via hole includes electrically conductive material thereon. The method further comprises removing a first portion of the conductive material from the inner sidewall by removing a first portion of the inner sidewall. A remaining portion of the conductive material on a remaining portion of the inner sidewall interconnects the pair of traces and has a corresponding width that is substantially similar to a width of each trace.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: December 30, 2014
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventor: Eric R. Ao
  • Patent number: 8923007
    Abstract: In at least one embodiment, a circuit board assembly that includes a printed circuit board is provided. The printed circuit board includes a top surface and a bottom surface for supporting at least one through-hole electrical component. The printed circuit board defines at least one component hole extending from the top surface to the bottom surface for receiving the at least one through-hole electrical component. The at least one component hole includes a first section having a first diameter and a second section having a second diameter. The first diameter is different from the second diameter. Each of the first and the second sections are configured to receive solder paste for forming a solder joint with the at least one through-hole electrical component.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: December 30, 2014
    Assignee: Oracle America, Inc.
    Inventors: Michael Francis Sweeney, Jorge Eduardo Martinez-Vargas, Jr., Michael Clifford Freda
  • Patent number: 8922234
    Abstract: A probe card for conducting an electrical test on a test subject includes a substrate body including a first surface, which faces toward the test subject, and a second surface, which is opposite to the first surface. A through electrode extends through the substrate body between the first surface and the second surface. A contact bump is formed in correspondence with the electrode pad and electrically connected to the through electrode. An elastic body is filled in an accommodating portion, which is formed in the substrate body extending from the first surface toward the second surface. The contact bump is formed on the elastic body.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 30, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akinori Shiraishi, Hideaki Sakaguchi, Mitsutoshi Higashi
  • Patent number: 8921700
    Abstract: A hermetic feed-through includes a housing body defining a hollow space, a plurality of conductive pins and a seal structure. The plurality of conductive pins extend through the hollow space. The seal structure is provided in the hollow space and includes a single-piece glass component. The single-piece glass component hermetically seals at least two conductive pins to the housing body and electrically insulates the at least two conductive pins from the housing body.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: December 30, 2014
    Assignee: Emerson Electric Co.
    Inventors: Brian VandenEynden, Prasad S. Khadkikar, Scott Schuckmann, Jian Sun, Gabe Lakner
  • Patent number: 8921707
    Abstract: A suspension substrate according to the present invention includes an insulating layer and a metallic support layer provided on the actuator element's side of the insulating layer. On the other side of the insulating layer, a wiring layer is provided. This wiring layer includes a plurality of wirings and a wiring connection section that can be electrically connected with the actuator element via a conductive adhesive. The outer periphery of the metallic support layer in a connection structure region is positioned outside relative to the outer periphery of the insulating layer and the outer periphery of the wiring connection section of the wiring layer.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: December 30, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Masao Ohnuki
  • Patent number: 8923008
    Abstract: A circuit board includes an insulation layer having a first surface and a second surface on the opposite side of the first surface, an electronic component positioned in the insulation layer and having a terminal, a conductive pattern formed on the second surface of the insulation layer and electrically connected to the terminal, and an insulative film formed on the second surface of the insulation layer and on the conductive pattern. The terminal of the electronic component has a protruding portion which protrudes from the second surface of the insulation layer.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 30, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Kazuhiro Yoshikawa, Toshiki Furutani
  • Patent number: 8916781
    Abstract: An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: December 23, 2014
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Cyprian Emeka Uzoh
  • Patent number: 8916782
    Abstract: An electro-static discharge (ESD) protection structure includes a first insulation layer (having a first surface, a second surface opposite to the first surface, and a through hole), a patterned conductive layer (located on the first surface), an electro-static releasing layer (located on the second surface), and a solder mask layer. At least one portion of the patterned conductive layer surrounds the through hole. The electro-static releasing layer is electrically insulated from the patterned conductive layer. At least one portion of the electro-static releasing layer is around the through hole. The solder mask layer covers the first insulation layer and a portion of the patterned conductive layer and exposes a portion of the patterned conductive layer surrounding the through hole. A multi-layered circuit board including a second insulation layer, a power supply layer, a third insulation layer and the ESD protection structure is also provided.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 23, 2014
    Assignee: Au Optronics Corporation
    Inventors: Hsin-Ting Wu, Kai-Yuan Siao
  • Publication number: 20140371744
    Abstract: The present invention relates to an electronic circuit arrangement (10) comprising: a substrate (12) having a first surface (12a) and a second surface (12b), an electronic circuit, an electrical connection part (16) for providing an electrical connection to the electronic circuit and being arranged on the first surface (12a), and at least one electrical wire (18). The electrical wire (18) comprises at least one conductive core (20) and an isolation (22) surrounding the conductive core (20). An end portion (18a) of the electrical wire (18) is an isolation-free portion for allowing access to the conductive core (20), wherein the end portion (18a) of the electrical wire (18) is connected to the electrical connection part (16). At least one through-hole (24) extending from the first surface (12a) to the second surface (12b) is provided in the substrate (12), wherein the electrical wire (18) is arranged through the through-hole (24).
    Type: Application
    Filed: February 20, 2013
    Publication date: December 18, 2014
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Ronald Dekker, Vincent Adrianus Henneken, Marcel Mulder
  • Patent number: 8913401
    Abstract: A multilayer wiring board includes a signal electrode, a first power supply electrode, and a ground electrode, which are connected to a first element that outputs a signal, an electrode connected to a second element that receives the signal, a ground layer that serves as a return path for a return current of the signal, a first power supply layer that is disposed adjacent to the ground layer with a dielectric layer interposed therebetween and supplies electric power to the first element, and a second power supply layer that is provided independently of the first power supply layer and supplies electric power to the second element. The first power supply layer causes the return current to return to the first element through the first power supply electrode as a displacement current between the ground layer and the first power supply layer.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: December 16, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Daisuke Iguchi
  • Patent number: 8912452
    Abstract: A Z-directed component for mounting in a mounting hole in a printed circuit board according to one example embodiment includes a body having a top surface, a bottom surface and a side surface. The body has a cross-sectional shape that is insertable into the mounting hole in the printed circuit board. A first portion of the body is composed of a first dielectric material having a first dielectric constant and a second portion of the body is composed of a second dielectric material having a second dielectric constant that is higher than the first dielectric constant. A conductive channel extends through a portion of the body forming a signal path.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: December 16, 2014
    Assignee: Lexmark International, Inc.
    Inventor: Keith Bryan Hardin
  • Patent number: 8912451
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 16, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Publication number: 20140360770
    Abstract: An exemplary printed circuit board includes a planar base, a first signal via defined in the base, a second signal via defined in the base, a first ground via defined in the base adjacent to the first signal via, a second ground via defined in the base adjacent to the second signal via, a first through hole defined in the base between the first signal via and the first ground via, and a second through hole defined in the base between the second signal via and the second ground via.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 11, 2014
    Inventors: WEN-CHIEH TSAI, FANG-YI LIN
  • Patent number: 8908377
    Abstract: A wiring board has a first rigid wiring board having an accommodation portion, a second rigid wiring board accommodated in the accommodation portion, an insulation layer formed over the first rigid wiring board and the second rigid wiring board, and a joint conductor extending in a direction from a first surface of the first rigid wiring board to a second surface of the first rigid wiring board on the opposite side of the first surface of the first rigid wiring board such that the joint conductor is penetrating through the boundary between the first rigid wiring board and the second rigid wiring board and joining the first rigid wiring board and the second rigid wiring board.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: December 9, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Nobuyuki Naganuma, Michimasa Takahashi
  • Patent number: 8907227
    Abstract: The present invention relates to a device with portions of the device on plural substrate surfaces. The device includes a low resistivity substrate having first and second surfaces with a first electrically-conductive device component disposed over a first surface. An intermediate electrically-insulating layer may be disposed between the electrically-conductive component and the low resistivity substrate. A second electrically-conductive component is disposed over the second surface of the low resistivity substrate. A cavity formed in the low resistivity substrate is at least partially filled with a high resistivity material. One or more electrically-conducting pathways are formed in the high resistivity material electrically connecting the first electrically conductive component and the second electrically-conductive component to form a device. Exemplary devices include inductors, capacitors, antennas and active or passive devices incorporating such devices.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: December 9, 2014
    Assignee: Hong Kong Science and Technology Research Institute Company Limited
    Inventors: Ruonan Wang, Yan Liu, Song He, Tingting Wang
  • Patent number: 8907354
    Abstract: The present disclosure relates to an optoelectronic device, in particular to an arrangement for contacting an optoelectronic device. The optoelectronic device (200) includes an elastic electrode (208). A method for forming the elastic electrode (208) is described.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andrew Ingle
  • Publication number: 20140353025
    Abstract: A printed circuit board includes a first insulating layer; a pad formed on the first insulating layer; a second insulating layer covered on the first insulating layer having the pad thereon; and a via hole formed in the second insulating layer. The pad has a surface that is non-planar.
    Type: Application
    Filed: March 25, 2014
    Publication date: December 4, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Deok Suk JANG, Yong Sam Lee
  • Publication number: 20140353019
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventors: Deepak Arora, Daniel N. Sobieski, Dilan Seneviratne, Ebrahim Andideh, James C. Meyer
  • Publication number: 20140353026
    Abstract: A wiring board according to the present invention includes an insulating layer 3, a semiconductor element mounting portion 1a, semiconductor element connection pads 11, via holes 8, and via conductors 10. The semiconductor element connection pads 11 aligned on the semiconductor element mounting portion 1a include first semiconductor element connection pads 11a and other second semiconductor element connection pads 11b, and the diameters of the via conductors 10 connected to the first semiconductor element connection pads 11a are larger than the diameters of the via conductors 10 connected to the second semiconductor element connection pads 11b.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 4, 2014
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Seiji HATTORI
  • Patent number: 8898891
    Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: December 2, 2014
    Assignee: Force10 Networks, Inc.
    Inventors: Joel R. Goergen, Yi Zheng
  • Patent number: 8901434
    Abstract: A board unit includes a board that has a through hole penetrating the board from a first side of the board to a second side of the board and having a conductive inner wall surface a first electronic component that has a first connection pin to be press-fitted in the through hole from the first side of the board, and a conductive member that is disposed in the through hole to connect the inner wall surface of the through hole to the first connection pin.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Akihiro Yasuo, Koji Kuroda
  • Publication number: 20140345916
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention includes a base substrate; a through via formed to penetrate through the base substrate; and circuit patterns formed on one side and the other side of the base substrate and formed to be thinner than an inner wall of the through via.
    Type: Application
    Filed: January 30, 2014
    Publication date: November 27, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim
  • Patent number: 8895872
    Abstract: The printed circuit board comprises two first signal traces, a first grounding layer, two first signal traces, a second grounding layer, two signal conductive pillars and two grounding conductive pillars. The first signal traces are formed on a first surface of a substrate. The first grounding layer is formed on the first surface. The second signal traces are formed on a second surface of the substrate. The second grounding layer is formed on the second surface. The signal conductive pillars are extended to the second surface from the first surface and each signal conductive pillar connects the corresponding first signal trace and second signal trace. The grounding conductive pillars are extended to the second surface from the first surface and each grounding conductive pillar connects the first grounding layer and the second grounding layer. Each grounding conductive pillar and the corresponding signal conductive pillar are disposed in pairs.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: November 25, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventor: Yu-Chang Pai
  • Patent number: 8895868
    Abstract: A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the wiring insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked without the adhesive layer interposed between the electrode layer and the wiring layer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Masahiro Sunohara
  • Patent number: 8895871
    Abstract: A circuit board has a plurality of circuit board layers that are arranged one over the other, and that each include an electrically insulating base material having a glass transition temperature greater than or equal to 170° C. The circuit board layers each further have at least one thermally conductive layer applied to the base material. Several vias extend through respective ones of the circuit board layers to connect thermally conductive layers of different circuit board layers, such that the vias and the thermally conductive layers form a thermally conductive bridge from a topmost circuit board layer to a bottommost circuit board layer.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: November 25, 2014
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Juergen Sauerbier, Wolfgang Gruebl, Bernhard Schuch, Hubert Trageser, Hermann-Josef Robin
  • Patent number: 8895863
    Abstract: A multilayer printed circuit board includes an insulating substrate, circuit layers arranged in the insulating substrate, an electronic component, an electrode disposed on the circuit layer exposed from a surface of the insulating substrate and including a soldered portion at which a terminal of the electronic component is soldered, an internal layer conductor disposed on the circuit layer located inside the insulating substrate and defining through holes in a radial manner centering on the soldered portion, a heat releasing conductor disposed on the circuit layer next to the circuit layer on which the internal layer conductor is disposed, and connection vias inserted in the through holes and coupling the electrode and the heat releasing conductor so as to enable a heat transfer between the electrode and the heat releasing conductor. The internal layer conductor and the heat releasing conductor overlap a whole area of the soldered portion.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: November 25, 2014
    Assignee: DENSO CORPORATION
    Inventors: Masashi Inaba, Akito Itou
  • Patent number: 8890001
    Abstract: A wiring board of the present invention includes a substrate including a woven fabric formed of a plurality of glass fibers and a resin covering the woven fabric; a plurality of through holes T penetrating through the substrate in a thickness direction thereof; and a plurality of through hole conductors adhered to inner walls of the through holes T respectively. The through holes T include a first through hole and a second through hole, and, in the woven fabric, the number of the glass fibers through which the first through hole penetrates is larger than the number of the glass fibers through which the second through hole penetrates. In the first and second through holes, portions thereof having narrowest widths are surrounded by the woven fabric, and the narrow width portion of the first through hole is smaller than the narrow width portion of the second through hole.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Kyocera SLC Technologies Corporation
    Inventors: Takayuki Nejime, Masaaki Harazono, Yoshihiro Hosoi
  • Patent number: 8889994
    Abstract: A single layered printed circuit board and a method of manufacturing the same are disclosed. In accordance with an embodiment of the present invention, the method can include forming a bonding pad, a circuit pattern and a post on a surface of an insulation film, in which one end part of the post is electrically connected to at least a portion of the circuit pattern, pressing an insulator on the surface of the insulation film, in which the circuit pattern and the post are buried in the insulator, selectively etching the insulator such that the other end part of the post is exposed, and opening a portion of the insulation film such that at least a portion of the bonding pad is exposed.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: November 18, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young-Ji Kim, Kyung-Ro Yoon, Sang-Duck Kim, Jung-Hyun Park, Nam-Keun Oh, Jong-Gyu Choi, Ji-Eun Kim
  • Patent number: 8889999
    Abstract: A printed circuit board (PCB) stack-up has a signal via configured to transmit a signal through at least two different layers of the PCB stack-up, a reference structure that is at least a portion of a return path for the signal; and an unplated via disposed in an area surrounding the signal via. The unplated via is disposed in the area surrounding the signal via to improve the characteristic impedance of the signal via.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 18, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Aritharan Thurairajaratnam, David Senk
  • Patent number: 8891245
    Abstract: A printed wiring board includes a core substrate having a penetrating hole, a first conductive layer on a first surface of the substrate, a second conductive layer on a second surface of the substrate, a first electronic component having an electrode and accommodated in the hole such that the electrode faces the first surface, a first structure on the first surface and including a pad for mounting a second electronic component on the first structure and a via conductor connected to the electrode, and a second structure on the second surface. The electrode has an upper surface facing toward the first surface, the first layer has an upper surface facing away from the first surface, and the first component is positioned in the hole such that the upper surface of the electrode forms a gap with the upper surface of the first layer.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 18, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventors: Toshiki Furutani, Yukinobu Mikado, Mitsuhiro Tomikawa
  • Patent number: 8890000
    Abstract: A printed wiring board has an insulating resin substrate having a first surface and a second surface, the insulating resin substrate having one or more penetrating-holes passing through the insulating resin substrate from the first surface to the second surface, a first conductor formed on the first surface of the insulating resin substrate, a second conductor formed on the second surface of the insulating resin substrate, and a through-hole conductor structure formed in the penetrating-hole of the insulating resin substrate and electrically connecting the first conductor and the second conductor. The penetrating-hole has a first portion having an opening on the first surface and a second portion having an opening on the second surface. The first portion and the second portion are connected such that the first portion and the second portion are set off from each other.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 18, 2014
    Assignee: Ibiden Co., Ltd.
    Inventor: Tomoyuki Ikeda
  • Publication number: 20140332258
    Abstract: An object of the present invention is to provide a double-sided printed wiring board in which a blind via hole can be easily and reliably formed, which can be accurately applied to lands of a surface-mounted component that are arranged at a narrow pitch, and in which an impedance mismatch can be effectively suppressed. The double-sided printed wiring board according to the present invention includes a substrate having an insulating property, a first conductive pattern stacked on a surface of the substrate and having a first land portion, a second conductive pattern stacked on another surface of the substrate and having a second land portion opposing the first land portion, and a blind via hole penetrating through the first land portion and the substrate, in which an average diameter of an outer shape of the first land portion is larger than an average diameter of an outer shape of the second land portion.
    Type: Application
    Filed: August 20, 2013
    Publication date: November 13, 2014
    Inventors: Yoshifumi Uchida, Yoshio Oka, Takashi Kasuga