Abstract: A semiconductor package structure includes a first dielectric layer, a conductive element, a first circuit structure, a semiconductor die and an encapsulant. The first dielectric layer defines at least one through hole. The conductive element is disposed in the through hole and including a first portion and a second portion. A first surface of the first portion is substantially coplanar with a first surface of the first dielectric layer, and a portion of a first surface of the second portion is recessed from the first surface of the first dielectric layer. The first circuit structure is disposed on the first dielectric layer. The semiconductor die is electrically connected to the first circuit structure. The encapsulant covers the semiconductor die.

Abstract: A wiring board includes an insulating resin layer including resin material and filler, and a conductive circuit layer laminated on a surface of the insulating resin layer and having wiring patterns. The filler has particle diameters of 15% or less of a minimum width of the wiring patterns when the particle diameters of the filler is measured in a unit range defined such that the unit range has a width and a length where the length is measured from the surface of the insulating resin layer and is selected from a smaller of twice the minimum width of the wiring patterns and a plate thickness of the insulating resin layer, and the width is twice the minimum width of the wiring patterns.

Abstract: According to one embodiment, a semiconductor device includes a substrate, semiconductor chips mounted on the substrate, a sealing resin layer that seals the semiconductor chips, and a film covering at least an upper surface of the sealing resin layer, the film made from a material selected from the group consisting of zinc, aluminum, manganese, alloys thereof, metal oxides, metal nitrides, and metal oxynitrides.

Abstract: A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Abstract: A multilayer printed circuit board comprising: i) a plurality of circuit board layers disposed in parallel planes to one another; ii) an outer via forming an electrical connection between a conductor contact on a first circuit board layer and a conductor contact on a second circuit board layer, wherein the outer via has a hollow central core; and iii) an inner via formed within the hollow central core of the outer via. The inner via forms an electrical connection between a conductor contact on a third circuit board layer and a conductor contact on a fourth circuit board layer. The inner via and the outer via are substantially concentric cylinders.

Abstract: A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

Abstract: A method of manufacturing a conductive layer on a support body includes a first process of forming a precursor layer containing at least one of metal particles and metal oxide particles on the support body; a second process of forming a sintering layer by irradiating an electromagnetic wave pulse on the precursor layer; and a third process of compressing the sintering layer. The conductive layer is formed by repeating the first to third processes “N” times, where “N” denotes a natural number equal to or greater than 2, on the same location of the support body, and the third process performed in the first to (N?1)th operations includes forming a surface of the sintering layer in an uneven shape.

Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component with contact terminals and conducting lines in a first wiring layer. There is also a dielectric between the component and the first wiring layer such that the component is embedded in the dielectric. Contact elements provide electrical connection between at least some of the contact terminals and at least some of the conducting lines. The electronic module also comprises a second wiring layer inside the dielectric. The second wiring layer comprises a conducting pattern that is at least partly located between the component and the first wiring layer and provides EMI protection between the component and the conducting lines.

Abstract: A circuit board comprises a third conductive circuit layer, a third insulating layer, a first insulating layer, a first conductive circuit layer, a substrate, a second conductive circuit layer, a second insulating layer, a fourth insulating layer, and a fourth conductive circuit layer in that order from top to bottom. The circuit board defines at least one first conductive hole and at least one second conductive hole. Each one of the first conductive hole comprises a first conductive blind hole, and a third conductive blind hole aligned with and electrically connected to the first conductive blind hole. Each one of the second conductive hole comprises a second conductive blind hole, and a fourth conductive blind hole aligned with and electrically connected to the second conductive blind hole. A method for making the circuit board is also provided.

Abstract: A connector module includes a substrate including stacked magnetic layers, a first principal surface, and a second principal surface opposite to the first principal surface, a surface mount connector mounted on mounting electrodes on the first principal surface of the substrate, external mounting electrodes disposed on the second principal surface of the substrate, and inductors inside the substrate and each connected at a first end thereof to a corresponding one of the mounting electrodes and connected at a second end thereof to a corresponding one of the external mounting electrodes.

Abstract: The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.

Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.

Abstract: A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel including at least one PCB. The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB. A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.

Abstract: In order to provide a substrate for light emitting devices having high heat radiating properties, dielectric strength voltage properties, light reflectivity, and excellent mass productivity, a substrate (5) includes an intermediate layer (11) containing ceramic which is formed on the surface of the aluminum base (10) by using an aerosol deposition method.

Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

Abstract: A printed board includes: a base member; a recess portion provided in the base member; a heat dissipation member fitted into the recess portion; and a wiring pattern provided on an upper side of the base member and the heat dissipation member via an insulator. A contact portion in which an inner circumferential surface of the recess portion and an outer circumferential surface of the heat dissipation member contact each other and a separation portion in which those do contact each other are formed. A gap between the recess portion and the heat dissipation member is filled with thermosetting resin of the base member melted by heating. At least a partial portion in a width direction of the wiring pattern passes through a position vertically overlapping the separation portion while an entire portion thereof does not pass through a position vertically overlapping the contact portion.

Abstract: A circuit board includes a substrate, two signal lines, two ground lines and two ground vias. The substrate includes a signal layer, a ground layer and an insulation layer. The signal layer is spaced apart from the ground layer. The signal lines are disposed on the signal layer with a first distance between the signal lines. The two signal lines are symmetrical about a reference line. The ground lines are disposed on the signal layer with a second distance between the first signal line and the first ground line. The second ground lines are disposed on the signal layer with one of the ground lines including two line portions having different widths. One of the ground vias is located at a joint between the two line portions. The two ground vias are symmetrical about the reference line.

Abstract: A bond ply, comprising a first outer layer comprising a thermosetting composition and a filler composition; a second outer layer comprising a thermosetting composition and a filler composition that is of the same type as that of the first outer layer; and an intermediate layer disposed between the first and the second outer layers, and comprising a thermosetting composition and a filler composition that is of the same type as the first and second outer layers, wherein the thermosetting composition of the intermediate layer has a degree of cure that is greater than a degree of cure for each of the thermosetting compositions of the first and the second outer layers.

Abstract: A wiring board includes an insulating layer, a first wiring layer, and a second wiring layer. The first wiring layer is formed in a first surface of the insulating layer, and includes a pad on which a semiconductor chip is to be mounted and a wiring pattern. The second wiring layer is formed on a second surface of the insulating layer opposite to the first surface. The roughness of a surface of the first wiring layer exposed at the first surface of the insulating layer is smaller than the roughness of a surface of the second wiring layer exposed on the second surface of the insulating layer.

Abstract: An object of the present invention is to provide an anisotropic conductive member capable of achieving excellent conduction reliability and a multilayer wiring substrate using the same. The anisotropic conductive member of the present invention includes an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each of the conductive paths has a protrusion which protrudes from the surface of the insulating base, and an end of the protrusion of each of the conductive paths is exposed or protrudes from the surface of the pressure sensitive adhesive layer.

Abstract: One object is to prevent electromagnetic wave interference between electronic components with restricted increase of the size of a circuit module. A circuit module according to an embodiment includes a circuit board, a plurality of electronic components provided on the circuit board, a resin mold provided on the circuit board so as to seal the plurality of electronic components in an insulating manner, a conductive shield covering the top surface and the side surfaces of the resin mold, and a plurality of conductive poles having a columnar shape provided in the resin mold and connecting the top surface of the conductive shield and the ground of the circuit board. The resonance caused by frequencies equal to or less than a predetermined maximum usable frequency is restricted.

Abstract: A display device including a flexible substrate that includes a display part to display an image; a driving integrated chip (IC) that supplies a driving voltage to the display part; a flexible printed circuit (FPC) attached to an outer side portion of the substrate; and a printed circuit board (PCB) attached to the FPC, the PCB transferring the driving voltage to the driving IC through the FPC, wherein the FPC includes attachment parts at ends thereof, the attachment parts of the FPC being attached to pad parts at the outer side portion of the substrate and to pad parts of the PCB, and the attachment parts include slits therein.

Abstract: A high bandwidth signal probe device and a method of probing a high bandwidth signal are provided. The high bandwidth signal probe device includes a probe tip for probing a stub of a backdrilled via of a printed circuit board. The probe tip is adapted to fit in the backdrilled via. The probe tip has a length adapted to reach the stub of the backdrilled via. The probe tip is adapted to contact a plated portion of the stub of the backdrilled via. A resistive element is associated with the probe tip. The method includes inserting a probe tip of a signal probe device in the backdrilled via, placing the probe tip in contact with a plated portion of the stub of the backdrilled via, and receiving an electrical signal through a path which includes a resistive element of the probe tip of the signal probe device.

Abstract: In a printed wiring board on which an electronic component comprising electrode terminal rows on four peripheral sides or two opposite sides thereof is mounted, each of pads at the both ends of pad rows corresponding to the electrode terminal rows extend outwardly relative to the other pads in the direction of arrangement of the pads and has a shape obtained by diagonally cutting a corner located farthest from the center of the electronic component.

Abstract: Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.

Abstract: In the present invention, a surface mount technology (SMT) connector for a printed circuit board (PCB) or a flexible printed circuit (FPC) includes a body formed of a non-conductive material, a connection member disposed on the body and adapted to engage the body with a mating surface and at least one terminal disposed on the body, the at least one terminal formed from a conductive polymer.

Abstract: A semiconductor device includes: a first semiconductor chip including a first terminal at a first face side, a first load whose one end is connected to the first terminal, another end of the first load being to be connected to a power source potential, a second terminal at a second face side, a second load whose one end is connected to the second terminal, another end of the second load being to be connected to a ground potential, a first detection circuit that detects generation of potential difference at the first load, and a second detection circuit that detects generation of potential difference at the second load; and a second semiconductor chip including a connection terminal disposed at a face facing the first semiconductor chip; wherein the power source potential or the ground potential is to be connected through the connection terminal to the first or second terminal.

Abstract: A multilayer printed circuit board is provided. The multilayer printed circuit board includes a core, a first conductive layer coupled to the core, an insulating layer covering the first conductive layer, and a second conductive layer spaced from the first conductive layer by the insulating layer. The first conductive layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The second conductive layer is electrically coupled to the second portion of the first conductive layer by a conductive via extending through the insulating layer.

Abstract: A method reduces an area of a mounting electrode provided on a first surface of a multilayer body and connected to a specific component is reduced and decreases a pitch between mounting electrodes. A plating film is formed on the mounting electrodes with the reduced area. The mounting electrodes for connection to specific components are defined by first end surfaces of first via conductors, and hence, the areas of the mounting electrodes are significantly reduced, and the pitch between the mounting electrodes is significantly decreased. Also, the mounting electrodes defined by the first end surfaces of the first via conductors are connected to plane electrodes at end surfaces of second via conductors exposed from a surface of the multilayer body with internal wiring electrodes interposed therebetween. Thus, a plating film is able to be reliably provided on the mounting electrodes.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; an upper wiring layer with one or more wiring structures, located above the first wiring layer; a blocking material which contacts at least one of the wiring structures of the upper wiring layer; a skip via with metallization, the skip via passes through the upper wiring layer and makes contact with the one or more wiring structures of the first wiring layer; and a conductive material in the skip via above the metallization and in a via interconnect above the blocking material.

Abstract: A method for manufacturing an interconnect structure and an interconnect structure are provided. The method includes: forming an opening in a substrate; forming a low-k dielectric block in the opening; forming at least one via in the low-k dielectric block; and forming a conductor in the via. The interconnect structure includes a substrate, a dielectric block, and a conductor. The substrate has an opening therein. The dielectric block is present in the opening of the substrate. The dielectric block has at least one via therein. The dielectric block has a dielectric constant smaller than that of the substrate. The conductor is present in the via of the dielectric block.

Abstract: A wiring substrate is manufactured by attaching an adhesive protective film to a metal-foiled laminate sheet, forming bottomed via holes by partially removing the film and an insulating film, filling conductive pastes into the holes, and peeling the film. A wiring substrate is manufactured by forming an adhesive protective layer so as to cover a patterned metal foil on a metal-foiled laminate sheet, forming bottomed step via holes by partially removing the layer and an insulating film, filling conductive pastes into the holes, and peeling off a protective film. The wiring substrate and the second wiring substrate are laminated in such a way that protruding parts of the pastes come into contact with respective protruding parts of the pastes.

Abstract: A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.

Abstract: The structural body related to the present disclosure includes a substrate having insulation properties arranged with a first surface and a second surface opposing the first surface, a through hole passing through the first surface and the second surface of the substrate, and a through electrode including a conductive material arranged within the through hole, the through electrode conducting the first surface and the second surface of the substrate and including a projection part exposed from the second surface to the outside of the through hole, wherein at least a part of the through hole is gradually increasing in size approaching the second surface in a thickness direction of the substrate, and forming a depression part keeping a gap between the through hole and the through electrode.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: In a leaded electronic component mounting structure in which the effect of reducing the occurrence of a blow hole is not impaired even if resin of a lead-inserted component is softened by heat during soldering and which can reduce a load placed on a lead when an external force acts, the lead of the lead-inserted component is inserted into a through hole provided in a base material of a printed wiring board, soldering is performed by immersing into molten solder, and a surface mount component and a surface mount component pad form an air vent tunnel. The air vent tunnel does not come into direct contact with the lead-inserted component, and therefore is not blocked even if the resin of the lead-inserted component softens due to soldering. Thus, the effect of reducing the occurrence of a blow hole is not impaired.

Abstract: A test carrier includes a base member that holds a die and a cover member. The base member includes a board having a wiring line that is electrically connected to the die. The wiring line includes a wiring line and a resistive portion having a resistance value that is higher than the resistance value of the wiring line.

Abstract: A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side, opposite to the first side. The RDL interposer comprises a first passivation layer, at least one dielectric layer on the first passivation layer, a metal layer in the at least one dielectric layer, a second passivation layer on the at least one dielectric layer, and a plurality of ball pads in the first passivation layer. At least one semiconductor die is mounted on the first side of the RDL interposer. A solder mask covers a lower surface of the first passivation layer and exposes the plurality of ball pads through a plurality of openings in the solder mask. An under-bump mettalization (UBM) layer is disposed at a bottom of each of the plurality of openings. A solder bump or solder ball is disposed on the UBM layer in each of the plurality of openings.

Abstract: An electric element-embedded multilayer substrate, which is a multilayer substrate including an electric element embedded therein and a plurality of base material layers having flexibility, the electric element including a main surface and being embedded in the multilayer substrate to be sandwiched between the base material layers, and a slide member provided between the main surface of the electric element and the base material layer.

Abstract: A printed circuit board comprises a base material containing at least one conductor path and at least one heat-conducting path forming a heating layer embedded in the base material for generating and conducting heat. The circuit board is characterized in that the heat-conducting path comprises a PTC thermistor with a constant voltage applied thereto. The invention further relates to a plug-in module comprising such a circuit board, and additionally to a field device comprising such a circuit board and/or such a plug-in module.

Abstract: A printed circuit board for mobile platforms includes a core substrate having a first side, a ground plane covering on the first side, a first insulating layer covering the ground plane, and a plurality of first signal traces and a plurality of first ground traces, alternatively arranged on the first insulating layer, a second insulating layer connecting to the first insulating layer, and a plurality of second signal traces separated from each other, disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto, wherein coverage of the ground plane is corresponding to disposition of the first signal trace, the first ground trace, the second signal trace and the second ground trace.

Abstract: An IHS chassis defines an IHS housing that houses a plurality of IHS components. The IHS chassis includes an outer surface located opposite the IHS chassis from the IHS housing. A first layer of the IHS chassis provides the outer surface of the IHS chassis. The first layer includes a first layer oxidized surface located opposite the first layer from the outer surface of the chassis base. A second layer of the chassis base is located immediately adjacent the IHS housing. The second layer includes a carbide-based composite material that provides a thermal conductivity of less than 1 watt per meter-kelvin in a direction that is generally perpendicular to the outer surface of the IHS chassis, while providing a thermal conductivity of at least 100 W/mK in directions that are generally parallel to the outer surface of the IHS chassis.

Abstract: A wiring substrate includes a core layer having a penetrating hole, a first insulating layer disposed on a first surface of the core layer and having a first opening at a position of the penetrating hole, the first insulating layer containing no filler, a penetrating electrode disposed in the penetrating hole and in the first opening, and a first wiring layer laminated both on the first insulating layer at a first surface thereof facing away from the core layer and on an end face of the penetrating electrode, wherein the first surface of the first insulating layer and the end face of the penetrating electrode are planarized.

Abstract: This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.

Abstract: A wiring board includes plural terminals, an insulating layer, and recess portions. Each terminal includes a roughened upper surface and a roughened side surface. The insulating layer is formed between the terminals. The upper surfaces of the terminals are exposed. An upper surface of the insulating layer is a concave curved surface. The recess portions are formed in the insulating layer around the terminals so as to partially expose the side surfaces of the terminals.

Abstract: Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.

Abstract: A multilayer electronic support structure including at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one constructional element through the dielectric material spanning between said pair of adjacent feature layers in a Z direction perpendicular to the X-Y plane; wherein said at least one constructional element is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane and wherein the at least one constructional element is fully encapsulated within the dielectric material and is electrically isolated from its surrounding.

Abstract: A heat dissipation printed circuit board includes a metal core, lower and upper insulating layers, first lower and first upper circuit patterns, and second lower and second upper circuit patterns. The lower and upper insulating layers are disposed at a lower side and an upper side of the metal core, respectively. The first lower and first upper circuit patterns are disposed at a lower side of the lower insulating layer and at an upper side of the upper insulating layer, respectively. The second lower and second upper circuit patterns are disposed at a lower side of the first lower circuit pattern and at an upper side of the first upper circuit pattern, respectively. An etching portion in the first lower circuit pattern is filled with the lower insulating layer and an etching portion in the first upper circuit pattern is filled with the upper insulating layer.