Abstract: A printed wiring board has thereon an electronic component having a heat radiation pad, and an electrolytic capacitor provided for the electronic component. The printed wiring board further has thereon another electronic component having another heat radiation pad and exhibiting a higher heat value than that of the electronic component, and another electrolytic capacitor provided for the other electronic component. The heat radiation pad of the electronic component, a ground terminal of the electrolytic capacitor, the other heat radiation pad for the other electronic component, and another ground terminal of the other electrolytic capacitor are connected by using a ground conductor. In the ground conductor, a thermal resistance between the other heat radiation pad and other ground terminal is lower than the thermal resistance between the heat radiation pad and the ground terminal.

Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures.

Abstract: A dielectric line includes a line portion and a surrounding dielectric portion. The line portion is formed of a first dielectric having a first relative permittivity. The surrounding dielectric portion is formed of a second dielectric having a second relative permittivity. The line portion propagates one or more electromagnetic waves of one or more frequencies within the range of 1 to 10 GHz. In a cross section orthogonal to the direction of propagation of the one or more electromagnetic waves through the line portion, the surrounding dielectric portion is present around the line portion. The first relative permittivity is 1,000 or higher. The second relative permittivity is lower than the first relative permittivity.

Abstract: An elastic wave device includes elastic wave filters connected in parallel between an input and an output, and has reduced size and insertion loss, and improved electric power handling capability. An elastic wave filter chip is mounted on a die-attach surface of a wiring board and includes an input signal terminal and output signal terminals. At least one of the input and output signal terminals includes a plurality of signal terminals. A common connection wiring line to commonly connect the plurality of signal terminals of the elastic wave filter chip is provided in the wiring board.

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.

Abstract: A system for transmitting or receiving signals may include a dielectric substrate having a major face, a communication circuit, and an electromagnetic-energy directing assembly. The circuit may include a transducer configured to convert between RF electrical and RF electromagnetic signals and supported in a position spaced from the major face of the substrate operatively coupled to the transducer. The directing assembly may be supported by the substrate in spaced relationship from the transducer and configured to direct EM energy in a region including the transducer and along a line extending away from the transducer and transverse to a plane of the major face.

Abstract: A highly thermally conductive printed circuit board prevents electrochemical migration by inhibiting elution of copper ions. The printed circuit board is a metal-base printed circuit board including a metal base plate having an insulating resin layer and a copper foil layer stacked thereon in this order. In the printed circuit board, the insulating resin layer contains a first inorganic filler made of inorganic particles having particle diameters of 0.1 nm to 600 nm with an average particle diameter (D50) of 1 nm to 300 nm, and a second inorganic filler made of inorganic particles having particle diameters of 100 nm to 100 ?m with an average particle diameter (D50) of 500 nm to 20 ?m, and the first inorganic filler and the second inorganic filler are uniformly dispersed in the insulating resin layer.

Abstract: The embodiments of the present invention provide a display panel and a display apparatus having the display panel. The display panel includes: an array substrate, a printed circuit board, a chip on film. One end of the chip on film is attached to a connection region of the array substrate, and the other end of the chip on film is attached to the printed circuit board, and the surface of the chip on film disposed with a chip faces the array substrate, and the connection region is disposed at a side of the array substrate away from a light-emitting surface.

Abstract: An electrical connector footprint on a printed circuit board (PCB) can include vias and antipads surrounding those vias. While conventional antipads surrounding vias are large in order to improve impedance of the PCB, the presence of the antipads can compromise the integrity of the ground plane and can permit cross talk to arise between differential pairs on different layers in the PCB. Antipads can be constructed and arranged so as to limit cross talk between layers in a PCB, while also maximizing impedance.

Abstract: In an integrated circuit package that houses radio-frequency (RF) circuits or components using wafer-level packaging (WLP), an RF-signal transmission structure includes a signal-carrying conductive line positioned between grounded conductive lines to avoid undesirable coupling between the signal-carrying conductive line and other RF circuits or components in the same package.

Abstract: Disclosed herein are a printed circuit board including an electronic component embedded therein and a method for manufacturing the same. The printed circuit board including an electronic component embedded therein includes: a core formed with a cavity which is formed of a through hole and has a side wall formed with an inclined surface having a top and bottom symmetrically formed based on a central portion thereof; an electronic component embedded in the cavity; insulating layers stacked on upper and lower portions of the core including the electronic component; and external circuit layers formed on the insulating layers.

Abstract: A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.

Abstract: A method for manufacturing circuit component package is disclosed. The method first forms copper circuits on a single-sided printed circuit board, and prints an electrically conductive paste on a plurality of predetermined locations on the copper circuits before positioning circuit dice of the circuit components on the locations printed with the electrically conductive paste. The method then forms a plurality of surface copper bumps on a copper plate, and prints the electrically conductive paste on each of the copper bumps. Then position and fit the printed circuit board on which the circuit dice are positioned relative to the copper plate on which the electrically conductive paste is printed such that each of the circuit dice aligns with the corresponding copper bump printed with the electrically conductive paste.

Abstract: Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines.

Abstract: A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.

Abstract: An integrated circuit packaging system, and a method of manufacture thereof, includes: a support structure having: an internal insulation layer having a hole, a device connection side, and a removal mark characteristic of a conductive seed layer removed at the device connection side, a first conductive pad in the hole at the device connection side, and an exterior insulation layer over the first conductive pad at the device connection side; an integrated circuit over the exterior insulation layer; and an encapsulation over the integrated circuit.

Abstract: A method of manufacture of a carrier system includes: providing a carrier base; forming a recess in the carrier base with the recess around a planar surface; forming a first barrier on the planar surface; forming a second barrier on the carrier base in the recess; forming a first post on the first barrier; and forming a second post on the second barrier.

Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Abstract: There is provided a conductive material which has a rapid reaction rate and is high in fluxing effect. The conductive material according to the present invention includes a conductive particle having solder at at least an external surface, an anionically hardenable compound, an anionic hardener, and an organic acid having a carboxyl group and having a functional group that is an esterified carboxyl group.

Abstract: The present invention relates to a test socket having a high-density conductive unit, and to a method for manufacturing same, whereby an elastic conductive sheet is arranged at a position corresponding to the terminal of the device, and includes a first conductive unit arranged in the thickness direction of an elastic material and an insulating support unit for supporting the first conductive unit. A support sheet is attached to the elastic conductive sheet and has through-holes corresponding to the terminal of the device. A second conductive unit is arranged in the through-holes of the support sheet in the thickness direction in an elastic material.

Abstract: A printed circuit board includes a first dielectric layer, a first ground layer, a second dielectric layer, a first power layer, a first via hole and a ground hole extending through the printed circuit board. A first signal line is laid on the first dielectric layer. A third signal line is laid on the second dielectric layer. The first and third signal lines are electrically connected to the first via hole. An extending direction of the first signal line on the first dielectric layer is the same as an extending direction of the third signal line is laid on the second dielectric layer. A first void area is defined in the first ground layer around the first via hole. A second void area is defined in the first power layer around the first via hole. The ground hole is outside the first void area and the second void area.

Abstract: A flex-rigid wiring board includes a flexible substrate, a non-flexible substrate positioned such that the non-flexible substrate is extending in horizontal direction of the flexible substrate, a first wiring layer formed on first surfaces of the flexible and non-flexible substrates, a second wiring layer embedded in second surfaces of the flexible and non-flexible substrates, a first insulating layer covering the first surfaces of the flexible and non-flexible substrates and having an opening exposing a portion of the first surface of the flexible substrate, and a second insulating layer covering the second surfaces of the flexible and non-flexible substrates and having an opening exposing a portion of the second surface of the flexible substrate. The first wiring layer includes non-embedded wirings on the first surfaces of the flexible and non-flexible substrates, and the second wiring layer includes embedded wirings in the second surfaces of the flexible and non-flexible substrates.

Abstract: A multilayer circuit substrate has a high frequency switch embedded therein. In the multilayer circuit substrate, a first conductive layer that faces a main surface of the high frequency switch through an insulating layer has circuit patterns formed therein so as to be connected to input/output terminals through via conductors. The first conductive layer has an opening pattern in which a ground conductor is not present in a region that faces the main surface of the high frequency switch and that is outside of the circuit patterns. In a third conductive layer disposed outer side of the first conductive layer with respect to the high frequency switch, a ground conductor is formed at least in a region where the main surface of the high frequency switch is projected in the thickness direction.

Abstract: A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.

Abstract: A coplanar waveguide electronic device is formed on a substrate. The waveguide includes a signal ribbon and a ground plane. The signal ribbon is formed of two or more signal lines of a same level of metallization that are electrically connected together. The ground plane is formed of an electrically conducting material which includes rows of holes.

Abstract: Provided is a printed circuit board, including a plurality of buried circuit patterns which are formed in an active area; and a plurality of buried dummy patterns which are uniformly formed in a dummy area except the active area. Thus, since when the circuit patterns are formed, the dummy patterns are also uniformly formed, a difference in plating can be reduced. Also, since the dummy patterns are uniformly formed in the dummy area, a difference in grinding between the dummy area and the active area can be reduced, thereby enabling the circuit patterns to be formed in the active area without the occurrence of over-grinding.

Abstract: The test socket includes: an elastic conductive sheet including a conductive portion and an insulating supporting portion; a sheet type connector including an electrode portion that is disposed on the conductive portion and is formed of a metal, and a sheet member that supports the electrode portion, wherein the sheet member comprises a cut portion formed by cutting at least a portion of the sheet member between adjacent electrode portions; and an electrode supporting portion including an upper supporting portion that contacts an upper edge of the electrode portion to support the electrode portion and exposes an upper center portion of the electrode portion to be open and an electrode supporting portion including a connection supporting portion that connects the upper supporting portion and the insulating supporting portion.

Abstract: A module includes an insulating substrate that is a first base material; a cover member having a cavity section and a second recess section that form an internal space between the cover member and the insulating substrate, which is a second base material bonded to the insulating substrate on a first surface thereof; an element piece that is a first functional element, accommodated in the internal space; a recess section formed on a second surface that is a rear surface of the first surface of the cover member; and a semiconductor device that is a second functional element, connected in the recess section.

Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.

Abstract: The present disclosure relates to an interposer structure and a manufacturing method thereof. The interposer structure includes a first dielectric layer, a conductive pad, and a bump. The conductive pad is disposed in the first dielectric layer, wherein a top surface of the conductive pad is exposed from a first surface of the first dielectric layer, the conductive pad further includes a plurality of connection feet, and the connection feet protrude from a bottom surface of the conductive pad to a second surface of the first dielectric layer. The bump is disposed on the second surface of the first dielectric layer, and the bump directly contacts to the connection feet. Through the aforementioned interposer structure, it is sufficient to achieve the purpose of improving the electrical performance of the semiconductor device and avoiding the signal being loss through the TSV.

Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.

Abstract: Integrated circuits and processes for manufacturing integrated circuits are described that use printed wiring board substrates having a core layer that is part of the circuit of the printed wiring board. In a number of embodiments, the core layer is constructed from a carbon composite. In several embodiments, techniques are described for increasing the integrity of core layers in designs calling for high density clearance hole drilling. One embodiment of the invention includes a core layer that includes electrically conductive material and at least one build-up wiring portion formed on an outer surface of the core layer. In addition, the build-up portion comprises at least one micro wiring layer including a circuit that is electrically connected to the electrically conductive material in the core layer via a plated through hole.

Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

Abstract: A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

Abstract: In one embodiment, an electronic package structure includes a substrate having one or more conductive plane layers formed therein. The substrate also includes a plurality of conductive pads on major surface configured to provide electrical interconnects to a next level of assembly. At least one conductive plane layer is configured to have cut-outs above the solder pads so that at least portions of the solder pad are not overlapped by the conductive plane layer.

Abstract: An electronic component having: a laminate formed by laminating a plurality of insulator layers; and a coil consisting of linear coil conductor layers that are laminated along with the insulator layers, the coil having a spiral form or a helical form that windingly extends in a direction of lamination. In a cross section perpendicular to a direction in which the coil conductor layers extend, the coil conductor layers have recesses provided in their surfaces directed toward an inner circumference side of the coil, the recesses being set back toward an outer circumference side of the coil.

Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

Abstract: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Abstract: An electrically conductive path is configured from a first copper plate, a second copper plate, and solder. The first copper plate has a first bent section extended from a first joining section joined to an electrically insulative board and bent toward the rear surface of the electrically insulative board. The second copper plate has a second bent section which is extended from a second joining section joined to the electrically insulative board, is bent toward the front surface of the electrically insulative board, and is disposed so as to cover, together with the first bent section, the inner wall surface of a base-material through-hole. Through-holes are provided in the portions of the second copper plate which face the inside of the base-material through-hole. Solder is filled between the first bent section and the second bent section.

Abstract: Electronic devices including intermetallic columns within vias are provided. Vias are filled with one or more pastes containing metal particles. Thermal treatment of the pastes within the vias converts the particles within the pastes to one or more intermetallic compounds that do not melt during next level packaging.

Abstract: A multilayered substrate and a method of manufacturing the same. The multilayered substrate includes a plurality of wiring layers and reinforcing layers disposed at the outermost portions of both surfaces of the multilayered substrate, respectively, in order to decrease warpage of the multilayered substrate and has wiring patterns optimized depending on a scheme in which external electrodes are formed on an electronic component.

Abstract: The method of manufacturing a substrate includes: forming a penetrating hole in a base layer; inserting a metal dummy part in the penetrating hole; forming an insulating portion made of synthetic resin to fill a ring-shaped gap between the penetrating hole and the dummy part; forming lower insulating layers, covering the bottom surface of the dummy part, that are made of synthetic resin on the bottom surface of the base layer to be continuous with the insulating portion; forming upper insulating layers, covering the top surface of the dummy part, that are made of synthetic resin on the top surface of the base layer to be continuous with the insulating portion; forming an exposing hole by routing in the upper insulating layers to expose the top surface of the dummy part; and forming a cavity by removing the dummy part exposed through the exposing hole by etching.

Abstract: An electronic device has a display mounted in a housing using a plastic display frame. The display has an active area and an inactive area. A display cover layer may have polymer coating layers in the inactive area. The display frame may lie under the inactive area. A patterned metal coating layer may be formed on the display frame. The patterned metal coating layer may have portions that form adhesion promotion structures for promoting adhesion between the frame and the adhesive. The patterned metal coating layer may also have portions that form antenna structures. The antenna structures may be used to transmit and receive radio-frequency signals and may be used as adhesion promotion structures. Adhesive may be interposed between the polymer coating layers and the metal coating layer on the display frame to attach the display cover layer and the display to the display frame.

Abstract: A process of repairing defects on a carbon fiber reinforced plastic (CFRP) component wherein defects on a surface of a CFRP component are selectively repaired by electrodeposition coating. With this process a reduction of coating material and work force as well as weight of the repaired CFRP component can be achieved.

Abstract: A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces.

Abstract: There is provided that a substrate comprising a glass substrate 2 constituted by a glass including a silicon oxide. The glass substrate has a through-hole 3 communicating with a front surface and a rear surface of the glass substrate, and filled with a metal material. The substrate is realized by forming an anchor part by selectively etching a silicon oxide on a sidewall surrounding an inside of said through-hole 3 before filling the metal material and by filling the inside of said through-hole 3 with the metal material after forming the anchor part.

Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and a close contact portion. The dielectric layer includes a first surface, a second surface facing the first surface, and a plurality of through-holes communicating between the first surface and the second surface. The first internal electrode portion is provided on a first through-hole portion. The second internal electrode portion is provided on a second through-hole portion. The close contact portion brings at least one of the first external electrode layer and the second external electrode layer into close contact with the dielectric layer, the close contact portion being provided on a third through-hole portion, the third through-hole portion being the remaining portion of the plurality of through-holes.

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate, a first stamp, and a different multi-level second stamp. A curable bottom layer is provided over the substrate. One or more bottom-layer micro-channel(s) are imprinted in the curable bottom layer with the first stamp and a bottom-layer micro-wire formed in each bottom-layer micro-channel. A curable multi-layer is formed adjacent to and in contact with the cured bottom layer. First and second multi-layer micro-channels and a top-layer micro-channel are imprinted in the curable multi-layer with the multi-level second stamp. Either two bottom-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a top-layer micro-wire or two top-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a bottom-layer micro-wire.

Abstract: A manufacturing method of an embedded wiring board is provided. The method includes the following steps. First, an insulation layer and a lower wiring layer are provided, wherein the insulation layer includes a polymeric material. Then, the plural catalyst grains are distributed in the polymeric material. A groove and an engraved pattern are formed on the upper surface. A blind via is formed on a bottom surface of the groove to expose the lower pad. An upper wiring layer is formed in the engraved pattern. Some catalyst grains are exposed and activated in the groove, the engraved pattern and the blind via. A first conductive pillar is formed in the groove. Finally, a second conductive pillar is formed in the blind via.

Abstract: A mount for a semiconductor device, the mount comprising: an insulating substrate having first and second parallel face surfaces, an edge surface that connects the parallel surfaces and having formed therein a recess having an opening on the first face surface; an electrically conductive plug seated in the recess and having a first exposed surface on or near the edge surface and a second exposed surface on or near the first face surface.