Application Of Energy To The Gaseous Etchant Or To The Substrate Being Etched Patents (Class 216/63)
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Patent number: 7303690Abstract: In a method for forming microlenses, an etching process is performed by using a processing gas on an object to be processed provided with a substrate, a lens material layer formed on the substrate and a mask layer of a lens shape formed on the lens material layer to etch the lens material layer and the mask layer, so that the lens shape of the mask layer is transcribed to the lens material layer. The processing gas is a gaseous mixture of a gas containing fluorine atoms but no carbon atoms and a fluorocarbon-based gas having a ratio of the number of carbon atoms to the number of fluorine atoms which is greater than or equal to 0.5, the gaseous mixture having no oxygen gas.Type: GrantFiled: August 31, 2005Date of Patent: December 4, 2007Assignee: Tokyo Electron LimitedInventors: Hiroki Amemiya, Akihiro Kikuchi
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Patent number: 7301159Abstract: A focused ion beam apparatus having two pieces of probers brought into contact with two points of a surface of a sample, a voltage source for applying a constant voltage between the two points with which the probers are brought into contact, and an ammeter for measuring a current flowing between the two points, in which a conductive film is formed to narrow a gap thereof between the two points by operating a deflection electrode and a gas gun and the current flowing between the two points is monitored, and when the current becomes a predetermined value, a focused charged particle beam irradiated to the surface of the sample is made OFF by the blanking electrode.Type: GrantFiled: August 3, 2005Date of Patent: November 27, 2007Assignee: Riken & SII NanoTechnology Inc.Inventors: Toshiaki Fujii, Masao Abe, Kunji Shigeto, Minuru Kawamura, Alekber Yu Kasumov, Kazuhito Tsukagoshi, Yoshinobu Aoyagi
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Patent number: 7284307Abstract: A method for manufacturing a wiring board, comprising the steps of: forming a first electrode layer having first and second opening portions, forming a dielectric layer formed on the first electrode layer and having third and fourth opening portions, forming a second electrode layer formed on the dielectric layer and having fifth and sixth opening portions, wherein the first electrode layer, the dielectric layer, and the second electrode layer form a capacitor; forming an insulating layer inside a first opening defined by the first, third, and fifth opening portions, and a second opening defined by the second, fourth, and sixth opening portions; using a laser beam having a processing diameter to form first and second via holes extending through the insulating layer formed inside the first and second openings, respectively; and forming first and second via wiring portions in the first and second via holes, respectively.Type: GrantFiled: October 19, 2005Date of Patent: October 23, 2007Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tomoo Yamasaki, Noriyoshi Shimizu, Kiyoshi Oi
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Patent number: 7262139Abstract: A method for etching metal deposited on a substrate, the method comprising: depositing a metal layer above a substrate; coating at least a portion of the deposited metal layer with a photo-resist; pattering the photo-resist; etching the deposited metal layer with an inert gas plasma at an energy density of less than 0.5 Watt/cm2, the substrate being maintained at a temperature of less than 50° C.; and ashing a resultant crust with an ashing gas, the ashing gas comprising CF4 and O2.Type: GrantFiled: May 18, 2005Date of Patent: August 28, 2007Assignee: AVX Israel, Ltd.Inventors: Eitan Avni, Elad Irron, Avi Neta
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Patent number: 7237315Abstract: A method for fabricating a quartz nanoresonator which can be integrated on a substrate, along with other electronics is disclosed. In this method a quartz substrate is bonded to a base substrate. The quartz substrate is metallized so that a bias voltage is applied to the resonator, thereby causing the quartz substrate to resonate at resonant frequency greater than 100 MHz. The quartz substrate can then be used to drive other electrical elements with a frequency equal to its resonant frequency. The quartz substrate also contains tuning pads to adjust the resonant frequency of the resonator. Additionally, a method for accurately thinning a quartz substrate of the resonator is provided. The method allows the thickness of the quartz substrate to be monitored while the quartz substrate is simultaneously thinned.Type: GrantFiled: April 30, 2003Date of Patent: July 3, 2007Assignee: HRL Laboratories, LLCInventors: Randall L. Kubena, David T. Chang, Jinsoo Kim
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Patent number: 7238294Abstract: The invention refers to a procedure for etching of materials at the surface by focussed electron beam induced chemical reactions at said surface. The invention is characterized in that in a vacuum atmosphere the material which is to be etched is irradiated with at least one beam of molecules, at least one beam of photons and at least one beam of electrons, whereby the irradiated material and the molecules of the beam of molecules are excited in a way that a chemical reaction predetermined by said material and said molecules composition takes place and forms a reaction product and said reaction product is removed from the material surface-irradiation and removal step.Type: GrantFiled: May 2, 2003Date of Patent: July 3, 2007Assignees: NaWoTec GmbH, University of MarylandInventors: Hans Wilfried Peter Koops, Klaus Edinger
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Patent number: 7214325Abstract: Forming low contract resistance metal contacts on GaN films by treating a GaN surface using a chlorine gas Inductively Coupled Plasma (ICP) etch process before the metal contacts are formed. Beneficially, the GaN is n-type and doped with Si, while the metal contacts include alternating layers of Ti and Al. Additionally, the GaN film is dipped in a solution of HCl:H2O prior to metal contact formation.Type: GrantFiled: March 22, 2002Date of Patent: May 8, 2007Assignee: LG Electronics Inc.Inventors: Jong Lam Lee, Ho Won Jang, Jong Kyu Kim, Changmin Jeon
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Patent number: 7205237Abstract: Apparatus for exposure and probing of features in a semiconductor workpiece includes a hollow concentrator for covering a portion of the workpiece connected by a gas conduit to a supply of etchant gas. A stage supports and positions the semiconductor workpiece. Control means moves the stage and the semiconductor workpiece to the series of positions sequentially. An energy beam source directs a focused energy beam through an aperture through the concentrator onto a region on the surface of the workpiece in the presence of the etchant gas. The control means moves the stage to a series of positions with respect to the concentrator and the energy beam to direct the energy beam in the presence of the etchant gas to expose a series of regions on the surface of the semiconductor workpiece positioned below the hollow interior space of the concentrator, sequentially.Type: GrantFiled: July 5, 2005Date of Patent: April 17, 2007Assignee: International Business Machines CorporationInventors: Andrew Deering, Terence L. Kane, Philip V. Kaszuba, Leon Moszkowicz, Carmelo F. Scrudato, Michael Tenney
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Patent number: 7201852Abstract: A method for eliminating eruptions, impurities, and/or damage in a crystal lattice by selectively etching silicon elements of surface-plated and sawn-out parts of a silicon wafer. At least areas of the silicon elements are brought into contact with a gaseous etching medium that etches silicon selectively in a chemical reaction, and gaseous reaction products are produced during etching. An interhalogen or fluorine-noble gas compound that is in a gaseous state or was converted to the gaseous phase may be used as the etching medium. The method is believed to be suitable for producing power diodes sawn from a wafer or for overetching fully mounted individual diodes.Type: GrantFiled: April 26, 2000Date of Patent: April 10, 2007Assignee: Robert Bosch GmbHInventors: Richard Spitz, Helga Uebbing, Doerte Eimers-Klose, Franz Laermer, Andrea Schilp
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Patent number: 7169440Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.Type: GrantFiled: September 30, 2002Date of Patent: January 30, 2007Assignee: Tokyo Electron LimitedInventors: Vaidyanathan Balasubramaniam, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
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Patent number: 7166233Abstract: In a method for performing a plasma-assisted treatment on a substrate in a reactor chamber by: introducing at least one process gas into the reactor chamber; and creating a plasma within the reactor chamber by establishing an RF electromagnetic field within the chamber and allowing the field to interact with the process gas, the electromagnetic field is controlled to have an energy level which varies cyclically between at least two values each sufficient to maintain the plasma, such that each energy level value is associated with performance of a respectively different treatment process on the substrate.Type: GrantFiled: February 15, 2002Date of Patent: January 23, 2007Assignee: Tokyo Electron LimitedInventors: Wayne L. Johnson, Eric J. Strang
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Patent number: 7148151Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.Type: GrantFiled: January 20, 2004Date of Patent: December 12, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Yamashita, Takao Yamaguchi, Hideo Niko
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Patent number: 7144521Abstract: A method for etching a high aspect ratio feature through a mask into a layer to be etched over a substrate is provided. The substrate is placed in a process chamber, which is able to provide RF power at a first frequency, a second frequency different than the first frequency, and a third frequency different than the first and second frequency. An etchant gas is provided to the process chamber. A first etch step is provided, where the first frequency, the second frequency, and the third frequency are at power settings for the first etch step. A second etch step is provided, where the first frequency, the second frequency, and the third frequency are at a different power setting.Type: GrantFiled: December 15, 2003Date of Patent: December 5, 2006Assignee: Lam Research CorporationInventors: Camelia Rusu, Rajinder Dhindsa, Eric A. Hudson, Mukund Srinivasan, Lumin Li, Felix Kozakevich
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Patent number: 7135123Abstract: The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.Type: GrantFiled: January 14, 2004Date of Patent: November 14, 2006Assignee: Credence Systems CorporationInventors: Mark Alan Thompson, Erwan Le Roy, Theodore Lundquist, William B. Thompson, Catherine Kardach
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Patent number: 7128842Abstract: A layer of polyimide or polysilicon is used as a mask in vapor hydrogen fluoride etching. Both non-photosensitive and photosensitive type polyimide may be used. A non-photosensitive polyimide mask requires the use of photoresist for patterning with a lithographic mask. Alternatively, photosensitive type polyimide may be patterned directly with the use of a lithographic mask. The resulting polyimide mask enables the etching of very small features with great uniformity. Such etching may be used to expose micropoint emitters of field emission devices.Type: GrantFiled: November 27, 2000Date of Patent: October 31, 2006Inventors: Tianhong Zhang, John K. Lee
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Patent number: 7122125Abstract: An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.Type: GrantFiled: November 4, 2002Date of Patent: October 17, 2006Assignee: Applied Materials, Inc.Inventors: Shashank C. Deshmukh, Thorsten B. Lill
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Patent number: 7096873Abstract: A method for manufacturing a group III nitride compound semiconductor device includes irradiating a surface of a wafer with ultraviolet rays to thereby clean a resist residue from the surface of the wafer, the surface including a group III nitride compound semiconductor. The ultraviolet rays cause a reaction of oxygen molecules to form stimulated oxygen atoms having a strong oxidative power at the surface.Type: GrantFiled: August 24, 2001Date of Patent: August 29, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Naoki Nakajo
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Patent number: 7060196Abstract: Apparatus and processes are disclosed for milling copper adjacent to organic low-k dielectric on a substrate by directing a charged-particle beam at a portion of the copper and exposing the copper to a precursor sufficient to enhance removal of the copper relative to removal of the dielectric, wherein the precursor contains an oxidizing agent, has a high sticking coefficient and a long residence time on the copper, contains atoms of at least one of carbon and silicon in amount sufficient to stop oxidation of the dielectric, and contains no atoms of chlorine, bromine or iodine. In one embodiment, the precursor comprises at least one of the group consisting of NitroEthanol, NitroEthane, NitroPropane, NitroMethane, compounds based on silazane such as HexaMethylCycloTriSilazane, and compounds based on siloxane such as Octa-Methyl-Cyclo-Tetra-Siloxane. Products of the processes are also disclosed.Type: GrantFiled: October 3, 2003Date of Patent: June 13, 2006Assignee: Credence Systems CorporationInventors: Vladimir V. Makarov, Theodore R. Lundquist
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Patent number: 7026252Abstract: After etching a Si-containing low permittivity insulating film with chlorine based gas, the etched wafer is subjected to an etching aftertreatment process comprising introducing oxygen gas to a vacuum processing chamber with a pressure as low as 0.2 Pa to 1 Pa and a flow rate as low as 5 cc to 20 cc/min, generating plasma within the chamber, heating the wafer 2 being subjected to aftertreatment between 50° C. and 200° C., applying a wafer bias power within the range of 50 W to 200 W, and exposing the wafer to the generated plasma, thereby simultaneously removing the photoresist components, the antireflection film components and the halogen components.Type: GrantFiled: February 25, 2003Date of Patent: April 11, 2006Assignee: Hitachi High-Technologies CorporationInventors: Michinobu Mizumura, Ryouji Fukuyama, Mamoru Yakushiji, Yutaka Ohmoto, Katsuya Watanabe
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Patent number: 7007374Abstract: A narrow track width read sensor having a high magnetoresistive sensitivity is made using a self-aligned process which requires the use of only a single resist mask. A plurality of sensor layers is deposited over a substrate. After forming a resist mask in the central region, first lead layers are deposited in the end regions and over the resist mask. Using the resist mask, ion milling is performed such that the first lead layers and sensor layers in the end regions are substantially removed but sensor layers in the central region remain, to thereby form a read sensor having lead overlays on the edges thereof. Hard bias and second lead layers are then deposited in the end regions and over the resist mask. After the resist mask is removed, the top of the read sensor may be oxidized through an exposure to oxygen plasma.Type: GrantFiled: August 9, 2002Date of Patent: March 7, 2006Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventor: Jeffrey Scott Lille
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Patent number: 7005081Abstract: This invention discloses an ingot cutting apparatus, wherein a crystalline ingot is positioned within an etching gas and a component of the etching gas is excited by illumination of light from a light source onto the crystalline ingot, thereby making a component of the etching gas react chemically with the component of the crystalline ingot and volatilizing the component of the crystalline ingot to cut the crystalline ingot and obtain wafers and wherein light from a light source is guided to the crystalline ingot via a sheet-like, bar-like, or fiber-like optical wave guide.Type: GrantFiled: July 3, 2002Date of Patent: February 28, 2006Assignee: Canon Kabushiki KaishaInventors: Nobuo Kawase, Masakatsu Ohta, Nobuyoshi Tanaka
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Patent number: 7001698Abstract: A chromium-containing half-tone phase-shift photomask comprising coarse and dense patterns coexisting in a plane is prepared by a series of pattern-forming steps including forming a resist layer on a photomask blank, exposing and patterning said resist layer, developing, etching said photomask blank and removing said resist layer. Patterns for transferring onto a wafer are formed on the photomask blank by a dry-etching method comprising dry-etching a chromium-containing half-tone phase-shift film utilizing etching gas comprised of mixed gas including (a) reactive ion etching gas, containing an oxygen-containing gas and a halogen-containing gas, and (b) reducing gas added to the gas component (a).Type: GrantFiled: November 14, 2003Date of Patent: February 21, 2006Assignees: Ulvac Coating Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Takaei Sasaki, Noriyuki Harashima, Satoshi Aoyama, Shouichi Sakamoto
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Patent number: 6998221Abstract: The present invention provides a method for forming a via (e.g., a trench, via or contact) in a substrate. The method, in one embodiment of the invention, includes patterning an opening 220 in a photoresist layer 210 located over an intermediate layer located over a substrate. In that particular embodiment the opening 220 has a predetermined width 230. The method may further include etching into the intermediate layer 120 such that an intermediate opening 310 is formed, the intermediate opening 310 having a decreasing width that terminates at a targeted width 320 less than the predetermined width 230. Additionally, the method may include continuing the etching within the intermediate opening 310 and at least partially into the substrate 110 to form a via opening 510 in the substrate. In this particular embodiment, the width 520 of the via opening 510 is substantially equal to the targeted width 320.Type: GrantFiled: May 23, 2003Date of Patent: February 14, 2006Assignee: Texas Instruments IncorporatedInventor: Karen H R Kirmse
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Patent number: 6981508Abstract: Provided herein is a method for cleaning a process chamber for semiconductor and/or flat panel display manufacturing. This method comprises the steps of converting a non-cleaning feed gas to a cleaning gas in a remote location and then delivering the cleaning gas to the process chamber for cleaning. Such method may further comprise the step of activating the cleaning gas outside the chamber before the delivery of the gas to the chamber. Also provided is a method of eliminating non-cleaning feed gas from the cleaning gas by cryo condensation.Type: GrantFiled: May 27, 2004Date of Patent: January 3, 2006Assignee: Applied Materials, Inc.Inventors: Quanyuan Shang, Sanjay Yadav, William R. Harshbarger, Kam S. Law
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Patent number: 6949202Abstract: Processes for the addition or removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the use of recirculation of the process gas. Recirculation is effected by a pump that has no sliding or abrading parts that contact the process gas, nor any wet (such as oil) seals or purge gas in the pump. Improved processing can be achieved by a process chamber that contains a baffle, a perforated plate, or both, appropriately situated in the chamber to deflect the incoming process gas and distribute it over the workpiece surface. In certain embodiments, a diluent gas is added to the recirculation loop and continuously circulated therein, followed by the bleeding of the process gas (such as an etchant gas) into the recirculation loop. Also, cooling of the process gas, etching chamber and/or sample platen can aid the etching process. The method is particularly useful for adding to or removing material from a sample of microscopic dimensions.Type: GrantFiled: August 28, 2000Date of Patent: September 27, 2005Assignee: Reflectivity, INCInventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Niles K. MacDonald
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Patent number: 6944939Abstract: A GMR sensor having improved longitudinal biasing is provided as is a method of forming it. The improved biasing is provided by longitudinal biasing structures in which a soft magnetic layer is interposed between a hard magnetic biasing layer and the lateral edge of the GMR sensor element. The soft magnetic layer eliminates the need for a seed layer directly between the hard magnetic layer and the GMR element and provides improved coupling to the free layer of the GMR element and a substantial reduction in random domain variations.Type: GrantFiled: March 21, 2003Date of Patent: September 20, 2005Assignee: Headway Technologies, Inc.Inventors: Yimin Guo, Li-Yan Zhu
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Patent number: 6942813Abstract: A method for etching magnetic and ferroelectric materials using a pulsed substrate biasing technique (PSBT) that applies a plurality of processing cycles to the substrate, where each cycle comprises a period of plasma etching without substrate bias and a period of plasma etching with the substrate bias. In exemplary applications, the method is used for fabricating magneto-resistive random access memory (MRAM) and ferroelectric random access memory (FeRAM) devices.Type: GrantFiled: March 5, 2003Date of Patent: September 13, 2005Assignee: Applied Materials, Inc.Inventors: Chentsau Ying, Padmapani C. Nallan, Ajay Kumar, Xiaoyi Chen
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Patent number: 6942892Abstract: The present invention provides a method for efficiently and completely removing a film deposited inside a film forming chamber. In addition, the invention provides a CVD apparatus using heating element which an in-situ cleaning method can be applied and its in-situ leaning method. The removal method of this invention comprises a method for removing a film deposited inside a chamber which can be exhausted and/or on a member placed in the chamber, wherein after the chamber is exhausted, a heating element, at least the surface of which is composed of platinum, disposed in said vacuum chamber, is heated at a prescribed temperature and a cleaning gas which is decomposed and/or activated by the heating element to generate an activated species that converts the deposited film into gaseous substance is introduced into the chamber.Type: GrantFiled: August 4, 2000Date of Patent: September 13, 2005Assignee: Anelva CorporationInventor: Keiji Ishibashi
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Patent number: 6902629Abstract: Methods and apparatus for cleaning deposition chambers are presented. The cleaning methods include the use of a remote plasma source to generate reactive species from a cleaning gas to clean deposition chambers. A flow of helium or argon may be used during chamber cleaning. Radio frequency power may also be used in combination with a remote plasma source to clean deposition chambers.Type: GrantFiled: April 12, 2002Date of Patent: June 7, 2005Assignee: Applied Materials, Inc.Inventors: Yi Zheng, Vinita Singh, Srinivas D. Nemani, Chen-An Chen, Ju-Hyung Lee, Shankar Venkataraman
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Patent number: 6902683Abstract: A method of plasma-processing is provided which includes placing a sample on one of electrodes provided in a vacuum processing chamber and holding the sample onto the electrodes by an electrostatic attracting force. A processing gas is introduced into an environment in which said sample is placed, and the environment is evacuated to a pressure condition for processing said sample. The processing gas is then formed into a plasma under the pressure condition, the sample is processed by the plasma, and a pulse bias voltage having a pulse cycle of 0.1 ?m to 10 ?m is applied to the sample.Type: GrantFiled: May 5, 2000Date of Patent: June 7, 2005Assignee: Hitachi, Ltd.Inventors: Tetsunori Kaji, Shinichi Tachi, Toru Otsubo, Katsuya Watanabe, Katsuhiko Mitani, Junichi Tanaka
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Patent number: 6880561Abstract: A process for removing residue from the interior of a semiconductor process chamber using molecular fluorine gas (F2) as the principal precursor reagent. In one embodiment a portion of the molecular fluorine is decomposed in a plasma to produce atomic fluorine, and the resulting mixture of atomic fluorine and molecular fluorine is supplied to the chamber whose interior is to be cleaned. In another embodiment the molecular fluorine gas cleans the semiconductor process chamber without any plasma excitation. Molecular fluorine gas has the advantage of not being a global warming gas, unlike fluorine-containing gas compounds conventionally used for chamber cleaning such as NF3, C2F6 and SF6.Type: GrantFiled: May 5, 2003Date of Patent: April 19, 2005Assignee: Applied Materials, Inc.Inventors: Haruhiro Harry Goto, William R. Harshbarger, Quanyuan Shang, Kam S. Law
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Patent number: 6874510Abstract: A method for performing the edge clean operation on a semiconductor wafer. A laser beam is used to accurately clean the edge of the wafer. The wafer is clamped concentrically to a chuck and rotated at a selectable speed, preferably in the range of 10 rpm to 1,000 rpm. A laser beam of variable power is directed onto toward the edge of the wafer at an oblique angle through a nozzle through which an inert purge gas is simultaneously passed. The laser beam removes unwanted deposits at the edge of the wafer and the gas is used to blow away the residue and prevent slag buildup on other parts of the wafer. The process is preferably carried out in an exhausted chamber.Type: GrantFiled: February 7, 2003Date of Patent: April 5, 2005Assignee: LSI Logic CorporationInventors: Steven Reder, Michael Berman, Rennie Barber
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Patent number: 6863835Abstract: A plasma chamber apparatus and method employing a magnet system to block the plasma within the chamber interior from reaching the exhaust pump. An exhaust channel between the chamber interior and the pump includes a magnet and at least one deflector that creates turbulence in the flow of exhaust gases. The magnetic field and the turbulence produced by the deflector both increase the rate of recombination of charged particles in the gases, thereby reducing the concentration of charged particles sufficiently to quench the plasma downstream of the magnet and deflector, thereby preventing the plasma body within the chamber from reaching the exhaust pump. The plasma confinement effect of the magnetic field permits the use of a wider and/or less sinuous exhaust channel than would be required to block the plasma without the magnetic field.Type: GrantFiled: April 25, 2000Date of Patent: March 8, 2005Inventors: James D. Carducci, Hamid Noorbakhsh, Evans Y. Lee, Hongqing Shan, Siamak Salimian, Paul E. Luscher, Michael D. Welch
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Patent number: 6858153Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: November 5, 2001Date of Patent: February 22, 2005Assignee: Applied Materials Inc.Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Patent number: 6843858Abstract: A method of operating a substrate processing chamber. In one embodiment the method includes processing one or more substrates in the substrate processing chamber and subsequently cleaning the chamber using a dry cleaning process. This substrate processing and dry cleaning sequence is then repeated multiple times before chamber is further cleaned by flowing a cleaning gas into the chamber and forming a plasma within the chamber from the cleaning gas in an extended cleaning process. During the extended cleaning process the plasma is maintained within the chamber for a total of at least 5 minutes before the chamber is reused to process a substrate.Type: GrantFiled: April 2, 2002Date of Patent: January 18, 2005Assignee: Applied Materials, Inc.Inventor: Kent Rossman
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Patent number: 6843258Abstract: Provided herein is a method for cleaning a process chamber for semiconductor and/or flat panel display manufacturing. This method comprises the steps of converting a non-cleaning feed gas to a cleaning gas in a remote location and then delivering the cleaning gas to the process chamber for cleaning. Such method may further comprise the step of activating the cleaning gas outside the chamber before the delivery of the gas to the chamber. Also provided is a method of eliminating non-cleaning feed gas from the cleaning gas by cryo condensation.Type: GrantFiled: December 19, 2000Date of Patent: January 18, 2005Assignee: Applied Materials, Inc.Inventors: Quanyuan Shang, Sanjay Yadav, William R. Harshbarger, Kam S. Law
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Patent number: 6840249Abstract: In order to clean a semiconductor device having a dielectric layer deposited on a top surface of a lower metal wiring of the semiconductor device, and a contact hole or a via hole formed in the dielectric layer to expose the lower metal line therethrough, the semiconductor device is located within a radio frequency (RF) cleaning chamber. A gas mixture of HCl and H2O is introduced into the RF cleaning chamber and Ar gas plasma is generated in the RF cleaning chamber to excite HCl gas so that the HCl gas and an excited HCl gas are used to remove carbon radicals and metal particles.Type: GrantFiled: December 26, 2002Date of Patent: January 11, 2005Assignee: Dongbu Electronics Co., Ltd.Inventor: Bo Min Seo
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Publication number: 20040265703Abstract: A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibit a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the higher selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Joseph Dalton, Thomas Benjamin Faure, Michelle Leigh Steen
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Patent number: 6835317Abstract: A slider prevent the phenomenon of sticking and reduce entrapping of foreign particles between sliding surfaces. A method for making micro-protrusions or micro-cavities on a surface of a substrate comprises placing the substrate in a process chamber, supporting a mask member having a micro shielding surface independent of and in front of the substrate, and irradiating fast atomic beams onto the surface of the substrate through the mask member.Type: GrantFiled: August 30, 2001Date of Patent: December 28, 2004Assignees: Ebara CorporationInventors: Yotaro Hatamura, Masayuki Nakao
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Patent number: 6824699Abstract: This invention relates to a method of heating an insulating layer, such as is found in semiconductor devices, in which a formation has been etched through a layer of resist comprising reactive etching the resist, inhibiting absorption of or removing water vapour and/or oxygen at the exposed surfaces of the etched formation and filling the formation with conductive metal in the absence of said water vapour and/or oxygen.Type: GrantFiled: May 16, 2003Date of Patent: November 30, 2004Assignee: Trikon Holdings Ltd.Inventor: Christopher David Dobson
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Patent number: 6810577Abstract: The present invention provides a method of efficiently manufacturing a dielectric waveguide with high reliability and precision. In the method, a resist material is formed on the outer surface of a green compact provided with a removal inhibiting layer, and predetermined portion of the green compact defined by the resist material is removed by the sand blasting method using the resist material as a mask, until the removal inhibiting layer is exposed to obtain a shaped green compact structure. The thus-obtained structure is fired to obtain a sintered body which comprises a dielectric strip and a wing.Type: GrantFiled: February 25, 2003Date of Patent: November 2, 2004Assignee: Murata Manufacturing Co. Ltd.Inventor: Toshikazu Takeda
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Patent number: 6808647Abstract: A method and apparatus for reducing the sensitivity of semiconductor processing to chamber conditions is provided. Process repeatability of common processes are affected by changing surface conditions which alter the recombination rates of processing chemicals to the chamber surfaces. In one aspect of the invention, a composition of one or more etchants is selected to optimize the etch performance and reduce deposition on chamber surfaces. The one or more etchants are selected to minimize buildup on the chamber surfaces, thereby controlling the chamber surface condition to minimize changes in etch rates due to differing recombination rates of free radicals with different surface conditions and achieve etch repeatability. In another embodiment, the etchant chemistry is adjusted to reduce the change to internal surface conditions after a cleaning cycle. In another embodiment, a process recipe is selected to reduce the sensitivity of the etch process to the chamber conditions.Type: GrantFiled: July 12, 1999Date of Patent: October 26, 2004Inventors: Songlin Xu, Zhiwen Sun, Dragan Podlesnik, Xueyu Qian
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Patent number: 6806038Abstract: A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrained chlorine gas. The substrate is heated on a chuck in a reaction chamber. A remote plasma is generated from ammonia gas and oxygen gas. The substrate is contacted with the ammonia and oxygen plasma, thereby withdrawing a substantial portion of the entrained chlorine gas from the polymer layer. A radio frequency potential is applied to the chuck on which the substrate resides, thereby creating a reactive ion etchant from the ammonia and oxygen plasma in the reaction chamber and removing the polymer layer from the top surface of the photoresist mask. The photoresist mask is thus exposed, and then removed in an ashing process.Type: GrantFiled: July 8, 2002Date of Patent: October 19, 2004Assignee: LSI Logic CorporationInventors: Shiqun Gu, Hong Lin, Ryan Tadashi Fujimoto
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Patent number: 6802944Abstract: A method of depositing a film on a substrate. In one embodiment, the method includes depositing a first portion of the film using a high density plasma to partially fill a gap formed between adjacent features formed on the substrate. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step that forms a plasma from a sputtering agent introduced into the processing chamber and biases the plasma towards the substrate and a subsequent chemical etch step that forms a plasma from a reactive etchant gas introduced into the processing chamber. After the etching sequence is complete, a second portion of the film is deposited over the first portion using a high density plasma to further fill the gap.Type: GrantFiled: October 23, 2002Date of Patent: October 12, 2004Assignee: Applied Materials, Inc.Inventors: Farhan Ahmad, Michael Awdshiew, Alok Jain, Bikram Kapoor
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Publication number: 20040173570Abstract: A method for etching magnetic and ferroelectric materials using a pulsed substrate biasing technique (PSBT) that applies a plurality of processing cycles to the substrate, where each cycle comprises a period of plasma etching without substrate bias and a period of plasma etching with the substrate bias. In exemplary applications, the method is used for fabricating magneto-resistive random access memory (MRAM) and ferroelectric random access memory (FeRAM) devices.Type: ApplicationFiled: March 5, 2003Publication date: September 9, 2004Applicant: Applied Materials, Inc.Inventors: Chentsau Ying, Padmapani C. Nallan, Ajay Kumar, Xiaoyi Chen
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Patent number: 6787054Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.Type: GrantFiled: February 3, 2003Date of Patent: September 7, 2004Inventors: Xikun Wang, Scott Williams, Shaoher X. Pan
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Patent number: 6780341Abstract: A shaper for an ion beam gun has a thin, flat plate with a non-symmetrical profile including notches and tabs. The shaper is mounted to the surface of an ion beam grid having an array of holes. The shaper is oriented radially on the grid and covers some of the holes in the grid. The grid is mounted to an ion beam gun above a specimen that is rotated beneath the ion beam gun. The ion beam is filtered into smaller ion beamlets by the grid. The ion beamlets permeate the holes in the grid that are not covered by the shaper. The ion beamlets reach the specimen to etch it more uniformly than a grid that does not have a shaper. The shaper may be further optimized for a particular grid via a trial-and-error process to even further refine the uniformity of etching depth.Type: GrantFiled: August 6, 2003Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: David Garcia, Cherngye Hwang, Uriel Ortiz, Nick K. Karmaniolas
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Patent number: 6758224Abstract: A method of cleaning a CVD vacuum vessel which has an electrically conductive partition plate which divides an interior of the vacuum vessel into a plasma generating space and a film-deposition processing space, and in the electrically conductive partition plate there is a plurality of through-holes connecting the plasma generating space to the film-deposition processing space, the method includes the steps of feeding a cleaning gas into the plasma-generating space; generating active seeds by applying high-frequency electric power to electrodes arranged in the plasma-generating space; feeding the generated active species into the film-deposition processing space through the plurality of through-holes in the electrically conductive partition plate; and cleaning the film-deposition processing space by the active seeds which have been fed into this film-deposition processing space.Type: GrantFiled: January 14, 2002Date of Patent: July 6, 2004Assignee: Anelva CorporationInventor: Hiroshi Nogami
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Publication number: 20040126704Abstract: A method for manufacturing thin-film chip resistors, in which method a resistor layer (14) and a contact layer (15, 16) are applied onto the upper surface of a substrate (10) and structured using laser light so as to form on said substrate (10) a plurality of adjacent, separate resistor lands (24) having a predetermined approximate resistance value, allows the simplified and cheap manufacturing by performing the electrical insulation of the resistor elements (24) and the structuring of the individual resistor lands (24) for the entire resistor land simultaneously by means of a laser-lithographic direct exposure method.Type: ApplicationFiled: August 26, 2003Publication date: July 1, 2004Inventors: Wolfgang Werner, Horst Wolf, Reiner Wilhelm Kuehl
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Patent number: 6746616Abstract: In one illustrative embodiment, a system is comprised of a semiconductor processing tool, an etcher, a metrology tool, and a controller. The semiconductor processing tool is capable of forming a process layer above a semiconducting substrate. The etcher is capable of removing at least a portion of the process layer. The metrology tool is capable of measuring a first depth of the etch at a first location in a first preselected region of the semiconducting substrate. The controller is capable of comparing the first depth to a desired depth, and varying the temperature of a subsequently processed semiconducting substrate in a region corresponding to the first preselected region in response to the first depth being different from the desired depth.Type: GrantFiled: March 27, 2001Date of Patent: June 8, 2004Assignee: Advanced Micro Devices, Inc.Inventors: H. Jim Fulford, Jeremy Lansford