Abstract: Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway.

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract: A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.

Abstract: An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n? epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.

Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.

Abstract: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 ?m technology. Self-aligned processing can be used.

Abstract: A vertical four-quadrant triac wherein the gate region, arranged on the side of a front surface, includes a U-shaped region of a first conductivity type, the base of the U lying against one side of the structure, the main front surface region of the second conductivity type extending in front of the gate region and being surrounded with portions of the main front surface region of the first conductivity type.

Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.

Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.

Abstract: A gate amplification triac including in a semiconductor substrate of a first conductivity type a vertical triac and a lateral bipolar transistor having its emitter connected to the triac gate, its base connected to a control terminal, and its collector connected to a terminal intended to be connected to a first reference voltage, the main terminal of the triac on the side of the transistor being intended to be connected to a second reference voltage, the transistor being formed in a first well of the second conductivity type and the triac comprising on the transistor side a second well of the second conductivity type, the first and second wells being formed so that the substrate-well breakdown voltage of the transistor is greater than the substrate-well breakdown voltage of the triac by at least the difference between the first and second reference voltages.

Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.

Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract: According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.

Abstract: A battery can be fabricated from a substrate including silicon. This allows the battery to be produced as an integrated unit. The battery includes a anode formed from an array of spaced elongated structures, such as pillars, which include silicon and which can be fabricated on the substrate. The battery also includes a cathode which can include lithium.

Abstract: A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.

Abstract: A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.

Abstract: The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising triggerable elements (TRi) coupled with triggering means, the said modules being connected between two terminals by the intermediary of a resistive network (R). A common semiconductor layer contacts all of the modules, each triggerable element (TRi) having at least one gate (GHi), and the triggering means comprise a single triggering circuit (TC) common to all of the triggerable elements and whose output is connected to the gates of all of the triggerable elements.

Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).

Abstract: A vertical four-quadrant triac wherein the gate region, arranged on the side of a front surface, includes a U-shaped region of a first conductivity type, the base of the U lying against one side of the structure, the main front surface region of the second conductivity type extending in front of the gate region and being surrounded with portions of the main front surface region of the first conductivity type.

Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: The invention relates to a method for producing a switch element. The invention is characterized in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode.

Abstract: A switching element includes a first electrode having a first surface; a second electrode having a second surface which stands off from the first surface; and a channel region constituted by a plurality of unit channels, each unit channel having opposite ends thereof being in contact with the first electrode and the second electrode, and including fine particles which are aligned in lines in a first direction from the first surface of the first electrode to the second surface of the second electrode, and the unit channels being separated from one another in a second direction across the first direction.

Abstract: A bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss.

Abstract: In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.

Abstract: A bidirectional switch controllable by a voltage between its gate and rear electrode and including an N-type semiconductor substrate surrounded with a P-type well; on the front surface side, a P-type well in which is formed a first N-type region; on the rear surface side, a P-type layer in which is formed a second N-type region. The well is doped to less than 1016 at./cm3, the exposed surfaces of this well being heavily P-type doped. At least a third P-type region, of same doping level as the well, is formed on the front surface side in the substrate, and contains at least a fourth N-type region of a doping level lower than 1017 at./cm3, on which is formed a Schottky contact.

Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).

Abstract: An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate.

Abstract: The invention relates to a method for producing a switch element. The invention is characterized in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode.

Abstract: A high-voltage vertical power component including a lightly-doped semiconductor substrate of a first conductivity type and, on the side of an upper surface, an upper semiconductor layer of the second conductivity type which does not extend all the way to the component periphery, wherein the component periphery includes, on the lower surface side, a ring-shaped diffused region of the second conductivity type extending across from one third to half of the component thickness; and on the upper surface side, an insulated ring-shaped groove crossing the substrate to penetrate into an upper portion of ring-shaped region.

Abstract: An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.

Abstract: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges.

Abstract: The invention relates to a method for producing a switch element. The invention is characterised in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode.

Abstract: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P? layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P? layer through a P well.

Abstract: Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.

Abstract: A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0° and 90° to the PMOS fin and includes a second surface of a second crystal orientation.

Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.

Abstract: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P? layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P? layer through a P well.

Abstract: An HF control bi-directional switch component of the type having its gate referenced to the rear surface formed in the front surface of a peripheral well of the component, including two independent gate regions intended to be respectively connected to terminals of a transformer having a midpoint connected to the rear surface terminal of the component.

Abstract: An NLDMOS SCR device based on an LDMOS fabrication process includes a dual gate to provide controllable switching characteristics to allow it to be used for ESD protection of fast switching voltage regulators.

Abstract: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P? layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P? layer through a P well.

Abstract: A thyristor-based memory device may comprise two base regions of opposite type conductivity formed between a cathode-emitter region and an anode-emitter region. A junction defined between the p-base region and the cathode-emitter region of the thyristor may be “treated” with a high ionization energy acceptor such as indium in combination with carbon as an activation assist species. These two implants may form complexes that may extend across the junction region.

Abstract: A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well.

Abstract: The invention relates to a lateral semiconductor diode, in which contact metal fillings (6, 7), which run in trenches (3, 4) in particular in a silicon carbide body (1, 2), are interdigitated at a distance from one another, and a rectifying Schottky or pn junction (18) is provided.

Abstract: A semiconductor device is provided which comprises a periphery region 23a extending downward from a third semiconducting region 23, enveloping an outer surfaces 21a and 22b of first and second semiconducting regions 21 and 22. A PN junctions is formed between second and third semiconducting regions 22, 23 inside of periphery region 23a perfectly away from side surfaces 28 of semiconductor substrate 27 to exert no adverse effect on breakdown by crystal defect in and foreign matters attached to side surfaces of semiconductor substrate 27. As periphery region 23a has the thinner diffusion concentration of impurity with the deeper area of periphery region 23a to widely spread depletion layer on boundary of the periphery region 23a with increase electric resistance.