Abstract: A semiconductor power device, e.g., an Insulated Gate Bi-polar Transistor (IGBT) or a Metal-Oxide Field Effect Transistor (MOSFET) may be constructed in a reusable and repairable cost-effective sealed shell. The switch may be provided with direct-pressure-contact caps which may perform as electrical conductors for a semiconductor die of the switch and also as thermal heat-sink contacts for the device. The switch may be provided with internal self-powered gate driving control and PHM incorporated in sealed shell. Embodiments of the switch may be constructed with no external gating/PHM connection pin penetrations through the shell.

Abstract: Two operation channels CH1 and CH2 of a bidirectional photothyristor chip 31 are disposed away from each other so as not to intersect with each other. In between a P-gate diffusion region 23 on the left-hand side and a P-gate diffusion region 23? on the right-hand side on an N-type silicon substrate, and in between the CH1 and the CH2, a channel isolation region 29 comprised of an oxygen doped semi-insulating polycrystalline silicon film 35a doped with phosphorus is formed. Consequently, a silicon interface state (Qss) in the vicinity of the channel isolation region 29 on the surface of the N-type silicon substrate increases, so that holes or minority carriers in the N-type silicon substrate are made to disappear in the region. This makes it possible to prevent such commutation failure that when a voltage of the inverted phase is applied to the CH2 side at the point of time when the CH1 is turned off, the CH2 is turned on without incidence of light, and this allows a commutation characteristic to be enhanced.

Abstract: The present invention is to provide a semiconductor device including: a semiconductor layer that has a first-conductivity-type region, a second-conductivity-type region, a first-conductivity-type region, and a second-conductivity-type region that are adjacent to each other in that order; first and second electrodes that are connected to the first-conductivity-type region and the second-conductivity-type region, respectively, at both ends of the semiconductor layer; and a gate electrode that is coupled to the second-conductivity-type region or the first-conductivity-type region in an intermediate area of the semiconductor layer, the gate electrode being provided over a plurality of faces of a semiconductor layer portion serving as the second-conductivity-type region or the first-conductivity-type region in the intermediate area.

Abstract: A surface-emitting type device includes a substrate including a first face, a second face that is tilted with respect to the first face and has a plane index different from a plane index of the first face, and a third face that is tilted with respect to the second face and has a plane index equal to the plane index of the first face, an emission section formed above the first face, and a rectification section formed above each of the second face and the third face, wherein the emission section includes a first semiconductor layer of a first conductivity type, an active layer formed above the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed above the active layer, the rectification section includes a first semiconductor layer of the second conductivity type formed above the second face, and a second semiconductor layer of the first conductivity type formed continuously with the first semiconductor layer above the third face, at least a portion of the first semico

Abstract: The invention concerns an asymmetric diac comprising a highly-doped substrate (21) of a first type of conductivity, a lightly-doped epitaxial layer (22) of the second type of conductivity on the upper surface of the substrate (21), a highly-doped region (24) of the first type of conductivity on the side of the upper surface of the epitaxial layer, a region (23) of the second type of conductivity more doped than the epitaxial layer beneath the region (24) of the first type of conductivity and not overlapping relative thereto, a channel retaining ring (25) of the second type of conductivity more doped than the epitaxial layer, outside the first region, and a wall (26) of the first type of conductivity outside said ring, joining the substrate.

Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: A high-frequency switching transistor comprises a collector area, which has a first conductivity type, a first barrier area bordering on the collector area, which has a second conductivity type which differs from the first conductivity type, and a semiconductor area bordering on the first barrier area, which has a dopant concentration which is lower than a dopant concentration of the first barrier area. Further, the high-frequency switching transistor has a second barrier area bordering on the semiconductor area, which has a first conductivity type, as well as a base area bordering on the second barrier area, which has a second conductivity type. Additionally, the high-frequency switching transistor comprises a third barrier area bordering on the semiconductor area, which has the second conductivity type and a higher dopant concentration than the semiconductor area. Further, the high-frequency switching transistor has an emitter area bordering on the third barrier area, which has the first conductivity type.

Abstract: In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to the ports that are to be protected.

Abstract: A vertical SCR-type switch including a control area having a first control region forming a first diode with a first neighboring region or layer, and a second control region forming a second diode with a second neighboring region or layer. A contact is formed on each of the first and second control regions and on each of the first and second neighboring regions or layers. The contacts are connected to terminals of application of an A.C. control voltage so that, when an A.C. voltage is applied, each of the two diodes is alternately conductive.

Abstract: A channel isolation region 42 is formed over the entire width of an N-type silicon substrate 41, and photothyristors, in each of which an anode diffusion region 43, a P-gate diffusion region 44, a cathode diffusion region 45 are formed parallel to the channel isolation region 42 over almost the entire width of the N-type silicon substrate 41, are formed in a left-hand portion 40a and in a right-hand portion 40b and are wired inversely parallel. Thus, the inter-channel movement of residual holes during commutation is restrained by the channel isolation region 42, by which commutation failure is suppressed to improve a commutation characteristic. Further, an operating current large enough for controlling a load current of approx. 0.2 A is obtained although a chip is divided by the channel isolation region 42. Therefore, using this bidirectional photothyristor chip makes it possible to implement an inexpensive SSR with a main thyristor eliminated.

Abstract: Fabrication processes for manufacturing and connecting a semiconductor switching device are disclosed, including an embodiment for dicing a wafer into individual circuit die by sawing the interface between adjacent die with a saw blade that has an angled configuration across its width, preferably in a generally V-shape so that the adjacent die are severed from one another while simultaneously providing a beveled surface on the sides of each separated die. Another embodiment relates to the manner in which damage to a beveled side surface of the individual die can be smoothed by a chemical etching process.

Abstract: The invention concerns a voltage-controlled triac-type component, formed in a N-type substrate (1) comprising first and second vertical thyristors (Th1, Th2), a first electrode (A2) of the first thyristor, on the front side of the component, corresponding to a first N-type region (6) formed in a first P-type box (5), the first box corresponding to a first electrode (A2) of the second thyristor, the first box containing a second N-type region (8); and a pilot structure comprising, above an extension of a second electrode region (4) of the second thyristor, a second P-type box (11) containing third and fourth N-type regions, the third region (12) and a portion of the second box (11) being connected to a gate terminal (G), the fourth region (13) being connected to the second region (8).

Abstract: A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1?xGex, where 0.5<x?1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).

Abstract: The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) includes at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V?), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V?) together with the substrate potential (Vo).

Abstract: A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

Abstract: A semiconductor device includes a thyristor having at least one body region thereof disposed in a substrate, and a filled trench having a conductive material. According to an example embodiment of the present invention, a conductive material having a narrow upper portion over a relatively wide lower portion is in a filled trench adjacent to at least one thyristor body region in a substrate. In one implementation, a thyristor control port is located over the wide lower portion and adjacent to the narrow upper portion of the conductive shunt and is adapted for capacitively coupling to the thyristor body region in the substrate for controlling current in the thyristor. In another implementation, the conductive material is electrically coupled to a buried emitter region of the thyristor and arranged for shunting current between the buried emitter region and a circuit node near an upper portion of the conductive material.

Abstract: A method and apparatus for opening a fuse formed on a semiconductor substrate. The apparatus comprises a thyristor formed from CMOS device regions and having a one or two control terminals for permitting current to flow through the thyristor into the fuse, for opening the fuse.

Abstract: A Schottky barrier diode 44 is formed between a P-gate diffusion region 33 and an N-type silicon substrate 31 in a photothyristor on a CH1 side and a photothyristor on a CH2 side. With this arrangement, the injection of minority carriers from the P-gate diffusion region 33 to the N-type silicon substrate 31 is restrained to reduce the amount of remaining carriers, and an excessive amount of carriers remaining in the N-type silicon substrate 31 during commutation has a reduced chance of moving toward the opposite channel side, allowing the commutation characteristic to be improved. Therefore, by a combination with an LED, there can be provided a light-fired coupler for firing and controlling the load.

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port.

Abstract: The invention concerns a pulsed bistable bidirectional electronic switch comprising a monolithic semiconductor circuit formed from a substrate (1) whereof the rear surface (A2) is coated with a metallization connected to earth. Said circuit comprises a vertical bidirectional switch (T1, T2) provided with a first gate terminal (M3), whereof the main electrode (A1) on the side of the front surface is connected to a load and an alternating current supply; a horizontal thyristor (T3) comprising an upper layer (4) of the vertical bidirectional switch, a first P-type region (11), and a second N-type region (12) formed in the first region; a second gate terminal (G1) connected to one of the first and second regions, the other being connected to earth. A capacitor (C) is connected to the first gate terminal (G3) and to the alternating current supply (VAC).

Abstract: A monolithic bidirectional switch formed in an N-type semiconductor substrate, including, in a first area, a first vertical thyristor adjacent to a second vertical thyristor; a triggering area arranged on the front surface side, apart from the first area, including a P-type well in which is formed an N-type region; a first metallization covering the rear surface; a second metallization on the front surface layers of the first and second thyristors; a third gate metallization on said well; on the rear surface side, an additional P-type region and an insulating layer interposed between this additional region and the first metallization, the additional region extending under the triggering area; and a fourth metallization on the region.

Abstract: The invention concerns a bidirectional electronic switch of the pulse-controlled bistable type comprising a monolithic semiconductor circuit including a vertical bidirectional switch structure (TR; ACS) provided with a gate terminal (G1), first (Th1) and second (Th2) thyristor structures whereof the anodes are formed on the front face side, the first thyristor anode region containing a supplementary P-type region (6), and a metallization (A1, A2) connected to the main surface of the front face of the vertical bidirectional component and to the second thyristor anode; a capacitor (C) connected to the first thyristor anode and to the second thyristor supplementary N-type region; and a switch (SW) for short-circuiting the capacitor.

Abstract: An edge-emitting thyristor having an improved external luminous efficiency and a self-scanning light-emitting device array comprising the edge-emitting thyristor are disclosed. To improve the external luminous efficiency of an edge-emitting light-emitting thyristor, a structure where the current injected from an electrode concentrates on and near the edge of the light-emitting thyristor is adopted.

Abstract: The IGBT (insulated gate bipolar transistor) has a weakly doped drift zone of a first conductivity formed in a weakly doped semiconductor substrate of the same conductivity. A highly doped first well zone of the first conductivity and a highly doped second well zone of a second conductivity are arranged between the drift zone and the semiconductor substrate.

Abstract: A bidirectional switch for switching an A.C. voltage at a load, including a monolithic component, formed in an N-type substrate, including a first vertical thyristor; a second vertical thyristor; a P-type triggering region formed opposite to the cathode of the first thyristor and an N-type triggering region formed in the P-type triggering region, the P-type triggering region being intended to receive a control signal in a negative halfwave of the A.C. voltage to trigger the first thyristor; a resistive element connected to the P-type triggering region and to the anode of the first thyristor; and a capacitor having a terminal connected to the N-type triggering region and its other terminal intended to be connected to the reference voltage.

Abstract: A gate driver includes a control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch. The gate control signal generator is provided proximate a high side of the gate driver. A first sub-circuit has a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. A comparator is configured to receive signals from the high side. The comparator is provided proximate a low side of the gate driver.

Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).

Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.

Abstract: A semiconductor device has a semiconductor substrate, several cell blocks provided on the semiconductor substrate, several gate electrodes electrically independent of one another and respectively provided in the cell blocks, and several gate pads respectively connected with the gate electrodes. In this construction, the cell blocks can be determined whether they are defective or not by utilizing the gate pads easily. Therefore, the semiconductor device can be operated only with non-defective cell blocks.

Abstract: In order to provide a reliable surge protective component with a straightforward manufacturing process, first and second buried layers are diffused over the entire inside surfaces of a semiconductor substrate, and first and second base layers are then diffused over the entire inside surfaces of the first and second buried layers. First and second emitter layers are then partially diffused at the inside of the first and second base layers. The peripheries of the first and second emitter layers are then surrounded by first and second moats, the bottoms of which reach the first and second buried layers. A PN junction formed between the first and second base layers and first and second buried layers is then simply a planar junction.

Abstract: A light emitting diode (LED) packaging structure with built-in rectification circuit is disclosed. The LED packaging structure includes an LED and a rectification circuit is formed inside the LED. Thus, the LED packaging structure is capable to receive an alternate current from an electrical main by the rectification circuit which converts the alternate current into a direct current for the LED whereby the LED can be directly connected to the electrical main and powered thereby without use of additional and external rectification device.

Abstract: An MIS gate type semiconductor device having a low resistive loss in the ON state and a wide safe operation region is disclosed. In this semiconductor device, the p-base layer of the thyristor and the emitter electrode are connected together using a suitable nonlinear device. As a result, lower loss and higher capacity of the semiconductor device can be realized in order not only to make it easy to turn ON the thyristor but also to make the safe operation region wide.

Abstract: A bidirectional semiconductor component having two symmetrical MOS transistor structures integrated laterally in a substrate and connected antiserially, their drain terminals being connected to one another. A zone having the same type of conductivity as the drain region yet a higher doping than that of the drain region is situated upstream from a pn junction of one of the MOS transistors in a junction area with the drain region.

Abstract: A bidirectional switch for switching an A.C. voltage at a load, comprising a monolithic component, formed in an N-type substrate, comprising a first vertical thyristor; a second vertical thyristor; a P-type triggering region formed opposite to the cathode of the first thyristor and an N-type triggering region formed in the P-type triggering region, the P-type triggering region being intended to receive a control signal in a negative halfwave of the A.C. voltage to trigger the first thyristor; a resistive element connected to the P-type triggering region and to the anode of the first thyristor; and a capacitor having a terminal connected to the N-type triggering region and its other terminal intended to be connected to the reference voltage.

Abstract: A gate driver includes a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch and a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay.

Abstract: A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotropic second etch procedure for definition of the titanium nitride gate structure shape, is employed.

Abstract: A self-scanning light-emitting element array using an end face light-emitting thyristor having improved external emission efficiency is provided. To improve the external emission efficiency of the end face light-emitting thyristor, the present invention adopts such structure that the current injected from an anode is concentrated to near the end face of the light-emitting thyristor. A self-scanning light-emitting element array is implemented by using such end face light-emitting thyristor.

Abstract: The invention concerns a pulsed bistable bidirectional electronic switch comprising a monolithic semiconductor circuit formed from a substrate (1) whereof the rear surface (A2) is coated with a metallization connected to earth. Said circuit comprises a vertical bidirectional switch (T1, T2) provided with a first gate terminal (M3), whereof the main electrode (A1) on the side of the front surface is connected to a load and an alternating current supply; a horizontal thyristor (T3) comprising an upper layer (4) of the vertical bidirectional switch, a first P-type region (11), and a second N-type region (12) formed in the first region; a second gate terminal (G1) connected to one of the first and second regions, the other being connected to earth. A capacitor (C) is connected to the first gate terminal (G3) and to the alternating current supply (VAC).

Abstract: Semiconductor structure configured as a semiconductor switch that can be used in various forms to switch currents. Semiconductor switch comprising non-doped or very lightly doped semiconductor crystal for switching currents in at least one direction at higher to high voltages which are significantly higher than the operating voltages of gate circuits, comprising an active region and a termination portion, wherein at least one opposite surface of the active region is provided with fine structures distributed over a wide area, which structures are substantially uniformly configured and include one conductive terminal surface each, by which charge carriers can be moved in a controlled manner into the active region of the semiconductor crystal via the fine structures in order to control a concentration of the charge carriers in the active region and thus the off-state and/or on-state of the semiconductor switch.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: A bidirectional switch, including a first bidirectional switch between two power terminals of the switch, a low-voltage storage element between a first power terminal and a control terminal of the switch, and a control stage adapted to cause, upon each halfwave beginning of an A.C. supply voltage applied between the power terminals and when the switch is on, the charge of the storage element with a biasing depending on the sign of the halfwave.

Abstract: A monolithic component including two thyristors of a composite bridge connected to an A.C. voltage terminal by a common terminal corresponding to a common rear surface metallization forming an electrode of opposite biasing of each thyristor. An isolating wall separates a substrate in two portions, a first portion includes on its lower surface side an anode region and on its upper surface side a cathode region, the second portion includes on its lower surface side a cathode region and on its upper surface side an anode region. The isolating wall surrounding each of the components extending towards the main electrode on the side which carries no common metallization and including in this extended region an N-type area, the two areas being connected together to a common control terminal.

Abstract: A silicon controlled rectifier includes a pair of complementary bipolar transistors. At least one of the pair of transistors exhibits a reach-through effect that occurs prior to the avalanche junction voltage breakdown.

Abstract: An insulating wall of a second conductivity type intended for separating elementary components formed in different wells of a semiconductive layer of a first conductivity type, a component located in one at least one of the wells being capable of operating with a high current density. The insulating wall includes at least two elementary insulating walls separated by a portion of the wafer material and, in operation, this portion is connected to a reference potential.