Abstract: A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p-type deep guard ring and a heavily doped p-type shallow impurity region are formed in said lightly doped semiconductor layer in such a manner that a diode has a major p-n junction between the heavily doped n-type impurity region and the heavily doped p-type shallow impurity region and other p-n junction between the lightly doped n-type semiconductor layer and the lightly doped p-type guard ring, wherein the other p-n junction is wider in area than the major p-n junction so that the breakdown voltage is adjustable without increase of parasitic capacitance dominated by the other p-n junction.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

Abstract: The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.

Abstract: A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configuration has a drive circuit for driving the power switches, and an inductive element that is connected to output terminals of the bridge circuit. At least one power switch is designed as a field-effect controllable, integrated transistor in accordance with the principle of charge carrier compensation or at least one power switch has deep pn junctions.

Abstract: A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Abstract: The invention relates to a component having a rectifying function, fulfilled by means of charge transfer by ions. To this end, the component is composed of multiple layers which have, successively, an asymmetric energy level course, and an electric field applied to these multiple layers.

Abstract: A rectifier structure that exhibits a low turn-on voltage and allows rapid switching without ringing is provided. The structure utilizes a thin epitaxial layer interposed between the two layers comprising the rectifier junction. Preferably the epitaxial layer is of the same conductivity as the underlying layer while being comprised of the same material as the outermost layer.

Abstract: A circuit arrangement, in particular for triggering an ignition output stage, having a power switching transistor and a switchable freewheeling circuit or an auxiliary channel. The freewheeling circuit or the auxiliary channel may be constituted by a triggerable four-layer element.

Abstract: In order that the threshold value of a cell separated from an emitter wire bonding portion (W1, W2) be larger than that of a cell immediately below the emitter wire bonding portion, the area of a diffusion layer (8a) of a cell separated from the wire bonding portion is made larger than that of a diffusion layer (8) for connecting an emitter electrode (2) and a base region (7) in a cell immediately below the wire bonding portion. This allows a hole current to be discharged outside via an emitter wire within a short time period, without adversely affecting the operating characteristics and the steady loss, in a position where this hole current readily remains upon turn-off in a conventional IGBT. This shortens the fall time and reduces the switching loss.

Abstract: A semiconductor rectifier includes a substrate of a first conductivity type; a current path layer of the first conductivity type formed near the surface of the substrate; a current block layer of a second conductivity type laterally enclosing the current path layer and extending to a depth deeper than the current path layer; and first and second metal layers formed respectively contacting upper and lower surfaces of the substrate. The current path layer has an impurity concentration higher than that of the substrate, and the current block layer has an impurity concentration higher than that of the current path layer. The current path layer is small enough for the portion below the current path layer to be completely blocked by the depletion region formed around the current block layer when a reverse bias or no is applied to the rectifier.

Abstract: An electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the apparatus. Using silicon on insulator technique, a bottom layer, a P-well, a first source/drain region, a second source/drain region and a gate are formed. A selective epitaxial growth region is selectively formed on the first source/drain region, and an N+ region is formed on the bottom layer. The lower portion of the N+ region is then adjacent to the P-well, and the upper portion of the N+ region is adjacent to the gate. Thus, a PNPN silicon control rectifier is formed, and the silicon on insulation CMOS technique is effectively transplanted into the electrostatic discharge apparatus.

Abstract: A wide bandgap semiconductor single crystal is applied as a semiconductor substrate material of a semiconductor surge absorber, and a surge absorption operation starting voltage is set by a punchthrough of a pn junction, to obtain a semiconductor surge absorber with a repetitive operation and a high surge endurance.

Abstract: A monolithic component including two thyristors of a composite bridge connected to an A.C. voltage terminal by a common terminal corresponding to a common rear surface metallization forming an electrode of opposite biasing of each thyristor. An isolating wall separates a substrate in two portions, a first portion includes on its lower surface side an anode region and on its upper surface side a cathode region, the second portion includes on its lower surface side a cathode region and on its upper surface side an anode region. The isolating wall surrounding each of the components extending towards the main electrode on the side which carries no common metallization and including in this extended region an N-type area, the two areas being connected together to a common control terminal.

Abstract: An AC switch device of the present invention comprises an n− region formed on a p-type semiconductor substrate, first and second p-type regions separately formed in the n− region, a first source region (n+ region) and a first sense region (n+ region) separately formed in the first p-type region, a second source region (n+ region) and a second sense region (n+ region) separately formed in the second p-type region, first and second channel regions formed in upper parts of the first and second p-type regions located between the first source region (n+ region) and the first sense region (n+ region), on the one hand, and the second source region (n+ region) and the second sense region (n+ region), on the other, a first gate electrode formed above the first channel region with a gate insulating film interposed, and a second gate electrode formed above the second channel region with a gate insulating film interposed.

Abstract: The invention provides a signal processing apparatus comprising clamp capacitance means for receiving, at one electrode thereof, first and second signals outputted from a signal source, a signal transfer transistor of which one main electrode is connected to an other electrode of the clamp capacitance means, signal accumulating capacitance means connected to an other main electrode of the signal transfer transistor, and reset means for fixing the potential of the signal accumulating capacitance means, wherein the potential of the signal accumulating capacitance means is fixed by the reset means while the first signal is outputted from the signal source and the signal accumulating capacitance means is maintained in a floating state while the second signal is outputted from the signal source, and the signal transfer transistor is controlled in such a manner that the potential of the main electrode of the signal transfer transistor and that of the other main electrode thereof show different saturation operations

Abstract: A TRIAC which is one species of chip-type semiconductors includes an element body made of silicon, electrodes provided on one face of the element body, a molybdenum plate provided on one of the electrodes by an alloy plate made of aluminum and silicon, a molybdenum plate provided on the other face of the element body by a similar alloy plate, and nickel layers provided on connection faces of the molybdenum plates to outer electrode plates, so that the electrode and molybdenum plate are firmly connected without conventional high-temperature solder which includes a great amount of lead, and that the alloy plate never melt even when newly developed low-temperature institute is employed, and that the operation of the molybdenum plates is sufficiently realized.

Abstract: An ESD protection circuit is fabricated on a semiconductor block on an insulating layer overlying a supporting substrate. The ESD protection circuit comprises a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region sequentially formed in the semiconductor block, and a stacked structure overlying the first P-type doped region and the second N-type doped region, wherein the first N-type doped region is more heavily doped than the second N-type doped region and the first P-type doped region is more lightly doped than the second P-type doped region.

Abstract: The present invention relates to an isolating wall for separating elementary components formed in different wells, a component located in at least one of the wells being capable of operating with a high current density. The isolating wall exhibits in its median portion a concentration of carriers higher than 1016 atoms/cm3. Preferably, the width of the openings from which the dopant diffusions are formed in the upper and lower surfaces of the substrate is higher than 1.3 times the half-thickness of the substrate.

Abstract: A high power rectifier device has an − drift layer on an N+ layer. A number of trench structures are recessed into the drift layer opposite the N+ layer; respective mesa regions separate each pair of trenches. Each trench structure includes oxide side-walls and an oxide bottom, and is filled with a conductive material. A metal layer contacts the trench structures and mesa regions, forming Schottky contacts at the metal-mesa interface. Shallow P regions extend from the bottom of each trench into the drift layer. Forward conduction occurs when the Schottky contact's barrier height is overcome. When reversed-biased, depletion regions form around the shallow P regions and the oxide side-walls which provide potential barriers across the mesa regions that shield the Schottky contacts from high electric fields, providing a high reverse blocking voltage and reducing reverse leakage current.

Abstract: A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed.

Abstract: An improved bond pad structure for semiconductor devices provides improved electrical isolation between adjacent bond pads by incorporating a pair of pn junctions between the pad and substrate. The pn junctions are defined by a first well of either P of N type material, formed within a substrate, and a second well or region of a P or N type material formed wholly within the first well. A bond wire is secured to an upper surface of the second region such that the wire, first and second regions and substrate are connected in electrical series relationship and provide an equivalent circuit of two series connected diodes reversed in polarity so as to block both negative and positive components of an applied voltage, thus providing electrical isolation for the bond pad structure.

Abstract: A thyris a thyristor is provided in which a lifetime of a minority carrier is controlled to improve the trade-off relationship between an ON-state voltage and a turn-off time and attain a high frequency and a low loss. Shielding members formed of metal plates are provided respectively in spaces above a plane on which a cathode electrode is provided and a plane on which an anode electrode is provided.

Abstract: To provide for fast switching at high powers while relieving stress on a mechanical switch, an electric switching device comprising a mechanical electric switch and an irradiation source and at least one switching element sensitive to irradiation is adapted to create an electrically well conducting current path by-passing the mechanical switch upon irradiation of the switching element by the irradiation source. The switching element assumes an electrically insulating state in the absence of irradiation thereof. The switching element includes rectifiers adapted to be reverse biased when not irradiated and conducting as a consequence of generation of free charge carriers therein through irradiation by the irradiation source.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region.

Abstract: A specification is given of a bidirectionally controllable thyristor which is distinguished by improved decoupling between the two thyristor structures. In particular, the intention is that the switched-off structure cannot be triggered in an uncontrolled manner by undesirable migration of charge carriers. This is achieved by virtue of the fact that the degree of shorting of the cathode region increases toward the isolation region. In particular, this can be achieved by virtue of the fact that the density per unit area of the short-circuit regions tends to a maximum value toward the isolation region. The use of a linear, continuous short-circuit region running along the isolation region is particularly favorable. (FIG. 1).

Abstract: A direct-current power supply unit is provided for applying forward bias to a pn junction between an n emitter region and a p base region. A switch is provided between the direct-current power supply unit and a first metal electrode layer or a second metal electrode layer. A switch control circuit is connected to the switch. A gate control circuit is connected to the switch control circuit. Accordingly, ON voltage of an IGBT can be reduced while latch-up is avoided.

Abstract: In a bidirectional photothyristor formed on a single N type silicon substrate, a distance between a P-gate diffusion region of one thyristor and an anode diffusion region of another thyristor opposed thereto is set to be 40 to 1,000 .mu.m, preferably, 70 to 600 .mu.m, thereby eliminating a malfunction caused by a noise due to a differentiation circuit which is composed of parasitic resistors and junction capacitances. In a field portion between the P-gate diffusion region and the anode diffusion region, an oxygen-doped semi-insulating film is formed via an SiO.sub.2 film, and an Al conductor is removed to form a field light receiving portion. Unlike a P-gate light receiving portion formed in the P-gate diffusion region, the field light receiving portion does not involve a junction capacitance. Therefore, a light sensitivity can be enhanced without lowering a dV/dt resistance.

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a double RESURF structure to provide high voltage blocking in both directions. The IGBT is symmetrical, having an N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type drift region, having a portion more heavily doped with P-type dopants. The double RESURF structure can be provided by a buried oxide layer, a floating doped region, or a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Abstract: A semiconductor component includes an insulating housing. A plurality of sheet-metal mounting plates are disposed in one and the same plane and are electrically separated from one another in the housing. Semiconductor switches of a rectifier bridge are electrically conductively secured to the mounting plates. Sheet-metal connection leads are electrically connected to the semiconductor switches. At least one sheet-metal connection lead is electrically connected to the mounting plates.

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a RESURF operation to provide high voltage blocking in both directions. The IGBT is symmetrical, having N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type-drift region, having a portion more heavily doped with P-type dopants. The RESURF operation can be provided by a buried oxide layer or by a P substrate or by a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Abstract: One embodiment of a metal oxide semiconductor controlled thyristor in accordance with the present invention has a semiconductor wafer with opposing first and second surfaces. The wafer includes first through sixth sequential regions which are disposed one above the other. The first region includes the second surface of the wafer and each of the second through sixth regions has at least a portion which extends up to the first surface. The first, third, and sixth regions have a first type of conductivity and the second, fourth, and fifth regions have a second type of conductivity. A trench with a bottom and sidewalls extends from the first surface and passes through the fourth, fifth, and sixth regions and into the third region. A dielectric material coats the bottom and sidewalls of the trench and a conductive material fills the remainder of the trench.

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.

Abstract: A bidirectional semiconductor switch employs two insulated gate semiconductor devices such as insulated gate bipolar transistors (IGBTs) that are connected oppositely in parallel, with the collector of one of the IGBTs being connected to the emitter of the other. The gates of the IGBTs are biased by gate controllers that are potentially independent of each other. The semiconductor switch is capable of controlling a direct current as well as an alternating current at a low ON-state voltage, reducing a conduction loss, and improving efficiency.

Abstract: A voltage-controlled power monolithic bidirectional switch has two main terminals and includes a control electrode whose voltage is referenced to one of the main terminals. The switch includes a lateral P-channel MOS transistor; a vertical N-channel MOS transistor, the source well of the vertical N-channel MOS transistor also constituting the source of the lateral transistor; a lateral thyristor whose first three regions correspond to the source, drain and channel of the lateral MOS transistor; a first vertical thyristor disposed in parallel with the lateral thyristor; and a second vertical thyristor having a polarity opposite to the first polarity and disposed in parallel with the vertical MOS transistor.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: High withstand voltage, low on-voltage, low turn-off loss, and high switching speed are realized in semiconductor bidirectional switches in which the potential of the substrate is floating. A switch has a p-type substrate without an electrode, and an n-layer on the substrate. At least one pair of p-well regions and at least one p-region are formed in a surface layer of the n-layer. An n.sup.+ region is formed in the p-well region, and a gate electrode is fixed via an insulation film to the p-well region. A main electrode is fixed to a part of the surface of the n.sup.+ region and the surface of a p.sup.+ contact region in the p-well region.

Abstract: This invention relates to an improved laser printer power supply that maintains 24-, 12-, and 5 volt DC power to run exhaust fans for a brief period after the power switch is turned off. These fans remove undesirable ozone from the photo-conducting print drum so as to extend the life of the photo-conductor. The circuits utilize a timer circuit and an optically isolated photo-diac to turn a power triac on and off.

Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.

Abstract: A semiconductor device is fabricated which has reduced power dissipation when the device is turned on and runs cooler in surge suppressor applications. This result is achieved by fabricating a device where the breakdown action takes place preferentially under cathode region. The lower power dissipated during the turn-on action enables the device to operate in environmental conditions from -20.degree. C. to 65.degree. C.

Abstract: An overvoltage protection device having multiple shorting dots in the emitter region and multiple buried regions substantially aligned with these shorting dots. The placement, number, and area of these buried regions reduce and more accurately set the overshoot voltage value of the device while maintaining the high surge capacities of the device. Further, doping types and concentrations have been modified from that known in the prior art to reduce overshoot providing a more accurate and sensitive overvoltage protection device than that known previously in the prior art.

Abstract: A gate turn-off thyristor having a p-emitter layer in the anode side, an n-base layer, a p-base layer and an n-emitter layer in the cathode side. The n-base layer is composed of a first layer portion adjacent to the p-emitter layer, a second layer portion adjacent to the p-base layer and having a lower impurity concentration than the first layer portion, and is constituted by a structure which alters a travelling path of positive holes injected from the p-emitter layer.

Abstract: Disclosed is a semiconductor device comprising an output Triode AC switch with a vertical structure, which is provided in a silicon substrate and has a gate, a first output terminal and a second output terminal, and an input/driving photo Triode AC switch, which is provided in the substrate and has a light-receiving portion, a first terminal connected to the gate and a second terminal connected to the second output terminal. The output Triode AC switch with a vertical structure is turned on when light is input to the photo Triode AC switch.

Abstract: In a bidirectional semiconductor switch which can be switched on and off, printed conductors which form the main term terminals (1, 2) and the control terminals (3, 4) are applied to a baseplate (9). Applied to the printed conductors, which form the main terminals (1, 2), are at least two reverse-blocking semiconductor components (5a-h) which can be switched on and off. The control electrodes (8a, 8e) and the second main electrodes (7a, 7e) of the semiconductor components (5a-h) are interconnected in such a way that the semiconductor switch has the required bidirectional switching function.

Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary driving gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation.

Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.