Abstract: An image sensor provides high scalability and reduced image lag. The sensor includes a first imaging pixel that has a first photodiode region formed in a substrate of the image sensor. The sensor also includes a first vertical transfer transistor coupled to the first photodiode region. The first vertical transfer transistor can be used to establish an active channel. The active channel typically extends along the length of the first vertical transfer transistor and couples the first photodiode region to a floating diffusion.

Abstract: A method and device is disclosed for reducing noises in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes a black light filter layer and an opaque layer covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer where the light blocking portion is desired but not over the active section.

Abstract: A solid-state image sensor includes: four or more photoelectric conversion units having spectral sensitivity characteristics different from one another; an amplifier unit disposed in correspondence to each group of photoelectric conversion units among N groups (N represents an integer less than a quantity of the four or more photoelectric conversion units and equal to or greater than one), the four or more photoelectric conversion units being divided into the N groups; and transfer units, each disposed in correspondence to one of the four or more photoelectric conversion units, which transfer a signal generated at the photoelectric conversion unit to the amplifier unit disposed for the group to which the photoelectric conversion unit belongs.

Abstract: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels.

Abstract: A CMOS image sensor with a many million pixel count. Applicants have developed techniques for combining its continuous layer photodiode CMOS sensor technology with CMOS integrated circuit lithography stitching techniques to provide digital cameras with an almost unlimited number of pixels. A preferred CMOS stitching technique exploits the precise alignment accuracy of CMOS stepper processes by using specialized mask sets to repeatedly produce a single pixel array pattern many times on a single silicon wafer with no pixel array discontinuities. The single array patterns are stitched together lithographically to form a pixel array of many million pixels. A continuous multilayer photodiode layer is deposited over the top of the many million pixel array to provide a many million pixel sensor with a fill factor of 100 percent or substantially 100 percent.

Abstract: A pixel is formed in a semiconductor substrate (S) with a plane surface for use in a photodetector. It comprises an active region for converting incident light (In) into charge carriers, photogates (PGL, PGM, PGR) for generating a lateral electric potential (?(x)) across the active region, and an integration gate (IG) for storing charge carriers generated in the active region and a dump site (Ddiff). The pixel further comprises separation-enhancing means (SL) for additionally enhancing charge separation in the active region and charge transport from the active region to the integration gate (IG). The separation-enhancing means (SL) are for instance a shield layer designed such that for a given lateral electric potential (?(x)), the incident light (In) does not impinge on the section from which the charge carriers would not be transported to the integration gate (IG).

Abstract: A method for producing a solid-state imaging device, which including: a photoelectric conversion section; a charge transfer section having a charge transfer electrode; and an antireflection film covering a light-receiving region in the photoelectric conversion section, wherein forming the antireflection film includes: forming a sidewall on a lateral wall of the charge transfer electrode after forming the charge transfer electrode; forming an antireflection film on a substrate surface where the sidewall is formed; forming a resist on the antireflection film; melting and flattening the resist to expose the antireflection film on the charge transfer electrode; removing the antireflection film by using the resist as the mask; removing the sidewall; covering the charge transfer electrode with an insulating film; and forming a light-shielding film that reaches a level lower than the top surface of the antireflection film, and that surrounds the periphery of the antireflection film.

Abstract: Provided is an electromagnetic wave reception device capable of being downsized and directly and simply (at least at a room temperature) detecting electromagnetic waves in a wider bandwidth including the terahertz range. The electromagnetic wave reception device that obtains charges according to an electric field of the electromagnetic waves incident on a semiconductor substrate includes: a high charge-density region provided on the semiconductor substrate and having a first charge density; a conductive region covering the high charge-density region via an insulation region; and a low charge-density region provided adjacent to the high charge-density region on the semiconductor substrate and having a second charge density lower than the first charge density, wherein the low charge-density region is connected to a charge detecting circuit that is not illustrated.

Abstract: A solid-state image sensor capable of improving detection sensitivity for an output signal is provided. This solid-state image sensor comprises a first gate electrode formed on a semiconductor substrate, a first impurity region formed on the semiconductor substrate at a first distance from the first gate electrode for receiving the signal charges and a second gate electrode formed at a second distance from the first impurity region for discharging unnecessary signal charges after extraction of a voltage signal from the first impurity region. The first distance between the first impurity region and the first gate electrode is larger than the second distance between the first impurity region and the second gate electrode.

Abstract: Provided is a solid-state imaging device including: a photodiode which converts an optical signal to signal charges; a transfer gate which transfers the signal charges from the photodiode; an impurity diffusion layer to which the signal charges are transferred by the transfer gate; and a MOS transistor of which a gate is connected to the impurity diffusion layer. The impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer which is formed in the first conduction type semiconductor layer and under an end portion of the transfer gate.

Abstract: A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of the semiconductor substrate, on an opposite side of the transfer gate from the photodiode, to accommodate the optical charges; and/or a channel area formed under the transfer gate and contacting a side of the photodiode to transfer the optical charges. The transfer gate may be formed, at least in part, of transparent material. A method of manufacturing a complimentary metal-oxide-semiconductor image sensor may include: forming the photodiode; forming the floating diffusion area, separate from the photodiode; and/or forming the transfer gate, near the photodiode, to transfer optical charges accumulated in the photodiode.

Abstract: A charge transfer device formed in a semiconductor substrate and including an array of electrodes distributed in rows and columns, wherein: each electrode is formed in a cavity with insulated walls formed of a groove which generally extends in the row direction, having a first end closer to an upper row and a second end closer to a lower row; and the electrodes of two adjacent rows are symmetrical with respect to a plane orthogonal to the sensor and comprising the direction of a row.

Abstract: During an exposure time period (long accumulation time period) of a low shutter speed shooting mode, a second reference voltage Vss2, which is different from a first reference voltage Vss1 (a ground voltage) corresponding to a reference voltage of a peripheral circuit, is applied to a well (5) where a photoelectric converter section (2) and a drain region (4) are formed, whereby generation of dark electrons at a portion of a surface of the well (5) below a gate electrode (6) is suppressed. A polarity of the second reference voltage Vss2 is positive in the case where a conductivity type of the well (5) is a P-type, and is negative in the case of an N-type.

Abstract: An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.

Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.

Abstract: A light detecting device includes a well region, a first holding region disposed in a surface portion of the well region, a second holding region and a third holding region disposed in a surface portion of the first holding region, an insulating layer disposed on the second holding region and the third holding region, a first electrode disposed on the second holding region through the insulating layer, and the second electrode disposed on the third holding region through the insulating layer. The first holding region is configured to hold a first carrier generated in the well region. Each of the second holding region and the third holding region is configured to hold a second carrier generated in the well region. The first carrier is one of an electron and a hole, and the second carrier is the other one of the electron and the hole.

Abstract: A solid state imaging device includes: a light receiving section performing photoelectric conversion; a transfer register formed in a semiconductor base; a transfer electrode formed of a semiconductor layer on the transfer register; a charge transfer section which formed of the transfer register and the transfer electrode and transferring a signal charge accumulated in the light receiving section; a bus line electrically connected to a portion of the transfer electrode to supply a driving pulse to the transfer electrode and formed of a metal layer; and a barrier metal layer formed near an interface between the transfer electrode and the bus line in a contact section that connects the transfer electrode and the bus line with each other and having a work function of the size between a work function of the semiconductor layer of the transfer electrode and a work function of the metal layer of the bus line.

Abstract: Disclosed is a metal optical filter capable of a photo-lithography process and an image sensor including the same, and more particularly, a metal optical filter capable of a photo-lithography process, which can quite freely adjust the transmission band and transmittance thereof, even with a small number of metal layers, and simultaneously, can be actually applied in a CMOS process because it is possible to achieve nanoscale patterning by the photo-lithography process, and an image sensor including the metal optical filter. The metal optical filter capable of a photo-lithography process includes a plurality of metal rods arranged in parallel with each other at an equal nanoscale interval; and an insulation material formed between the plurality of metal rods and on upper and lower surfaces of the plurality of metal rods, wherein the metal rod is formed to comprise an upper Ti layer, an Al layer, and a lower TiN layer.

Abstract: An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e. one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a Vt adjustment implant and/or increasing its gate length.

Abstract: A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels.

Abstract: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Abstract: An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.

Abstract: A noise generated by a constitution of widening an incident aperture of light of a photoelectric conversion element is reduced. In a manufacturing method of a photoelectric conversion device, first electroconductor arranged in a first hole arranged in the first interlayer insulation layer electrically connects a first semiconductor region to a gate electrode of an amplifying MOS transistor not through wirings included in a wiring layer. Moreover, a second electroconductor electrically connects a second semiconductor region different from the first semiconductor region to a wiring. In a constitution of that second electroconductor, a third electroconductor arranged in a second hole arranged in the first interlayer insulation layer and a fourth electroconductor arranged in a third hole arranged in the second interlayer insulation layer are stacked and electrically connected to each other.

Abstract: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode comprising a first conductive film and a second layer electrode comprising a second conductive film, and the first layer electrode and the second layer electrode are separated by insulation with an interelectrode insulating film having a two-layer structure comprising a sidewall insulating film consisting of a first insulating layer formed by a CVD method to cover the lateral wall of the first layer electrode and a second insulating film.

Abstract: An image pickup apparatus having plural light receiving areas arranged two-dimensionally, and vertical and horizontal scanning circuits composed of plural unit circuit stages arranged in the vertical and horizontal directions, respectively. The vertical and horizontal scanning circuits are arranged in spaces between the light receiving areas, wherein for unit circuit groups each constituted by two unit circuits of the horizontal or vertical scanning circuits, the unit circuit groups are arranged at a constant pitch.

Abstract: Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces are disclosed herein. In one embodiment, a method for forming microlenses includes forming a plurality of shaping members on a microfeature workpiece between adjacent pixels, reflowing the shaping members to form a shaping structure between adjacent pixels, depositing lens material onto the workpiece, removing selected portions of the lens material adjacent to the shaping structure such that discrete masses of lens material are located over corresponding pixels, and heating the workpiece to reflow the discrete masses of lens material and form a plurality of microlenses.

Abstract: A solid-state imaging device including: a semiconductor substrate on which an imaging region having a light receiving section is formed; and a predetermined layer formed on the semiconductor substrate by planarization processing using liquid containing a metal element, wherein at least a first diffusion protection film is formed between the light receiving section and the predetermined layer.

Abstract: Disclosed herein is a solid-state imaging element including: (A) a light reception/charge storage region formed in a semiconductor layer, the light reception/charge storage region including M light reception/charge storage layers stacked one on top of the other, where M?2; (B) a charge output region formed in the semiconductor layer; (C) a conduction/non-conduction control region which includes a portion of the semiconductor layer located between the light reception/charge storage region and the charge output region; and (D) a conduction/non-conduction control electrode adapted to control the conduction or non-conduction state of the conduction/non-conduction control region, wherein mth potential control electrodes are provided between the mth and (m+1)th light reception/charge storage layers, where 1?m?(M?1), to control the potentials of the light reception/charge storage layers.

Abstract: A display apparatus includes pixel electrodes disposed on a first base substrate, a second base substrate which faces the first base substrate, color pixels disposed on the second base substrate, the color pixels correspond to the pixel electrodes in a one-to-one correspondence, each color pixel partially covers the corresponding pixel electrode, a common electrode disposed on the second base substrate to cover the pixel electrodes and an electrophoretic layer including a plurality of electrophoretic particles, the electrophoretic layer being interposed between the pixel electrodes and the common electrode.

Abstract: The pixel for use in an image sensor comprises a low-doped semiconductor substrate (A). On the substrate (A), an arrangement of a plurality of floating areas, e.g., floating gates (FG2-FG6), is provided. Neighboring floating gates are electrically isolated from each other yet capacitively coupled to each other. By applying a voltage (V2?V1) to two contact areas (FG1, FG7), a lateral steplike electric field is generated. Photogenerated charge carriers move along the electric-field lines to the point of highest potential energy, where a floating diffusion (D) accumulate the photocharges. The charges accumulated in the various pixels are sequentially read out with a suitable circuit known from image-sensor literature, such as a source follower or a charge amplifier with row and column select mechanisms. The pixel of offers at the same time a large sensing area, a high photocharge-detection sensitivity and a high response speed, without any static current consumption.

Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.

Abstract: An image sensor and method for manufacturing the same are provided. The image sensor can include an isolation area and active area on a substrate; a photodiode area and a transistor area provided on the active area; a gate insulating layer on the transistor area; and a gate electrode provided on the gate insulating layer and a portion of the photodiode area by extending over a portion of the isolation area between the transistor area and the photodiode area. In one embodiment, the gate electrode can be a gate electrode of a drive transistor of a 3-T type image sensor.

Abstract: To reduce white spots by optimizing an impurity concentration of a p-type impurity doped region of a well contact, a size of a contact portion, a position of an n-type region serving as a photoelectric converter, and so on. In a solid state image pickup device in which a semiconductor substrate 11 includes a pixel region where a plurality of pixels are arranged, each pixel including a photoelectric converter 21, and a pixel well 12 shared by the respective pixels, a well contact 14 supplying a reference voltage to the pixel well 12 includes: an electrode 15 supplying a reference voltage; a p-type impurity doped region 16 placed in a surface of the pixel well 12; and a contact portion 17 placed in the p-type impurity doped region 16 so as to be connected to the electrode 15 and having a higher concentration than the p-type impurity doped region 16. The p-type impurity doped region 16 is doped with at least a p-type impurity, with an impurity concentration of 1×1019 cm?3 or less.

Abstract: A pixel structure including an active device, a common line pattern, a protective layer, a pixel electrode, and a patterned semiconductor layer is provided. The active device is disposed on a substrate. In addition, the common line pattern is disposed on the substrate and covered with an insulation layer. The protective layer covers the active device and a part of the insulation layer. The protective layer has a contact window exposing the active device. The pixel electrode is disposed on the protective layer and electrically connected to the active device through the contact window. The patterned semiconductor layer is disposed on the insulation layer above the common line pattern. The patterned semiconductor layer is located between the common line pattern and the pixel electrode.

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract: A solid-state imaging device is provided and includes: a semiconductor substrate having a two-dimensional array of photoelectric conversion elements, each storing a signal charge in accordance with a received amount of light; a charge transfer path that transfers the signal charge read out of the photoelectric conversion elements toward an output end of the solid-state imaging device; and a branching part having two branches, the branching part receiving the signal charge transferred along the charge transfer path and distributing the signal charge toward one of the two branches alternately. The charge transfer path has an end portion narrowed in channel width and connected to the branching part.

Abstract: A CCD type solid-state imaging device includes: a photoelectric conversion element (n layer 2, p layer 3) formed in a semiconductor substrate 1; a charge transfer channel 5 that transfers electric charges generated in the photoelectric conversion element; a charge read region 6 that reads out the electric charges accumulated in the photoelectric conversion element into the charge transfer channel 5; and a charge read electrode 8 formed above the charge read region 6 with a gate insulating film 10 disposed therebetween. The charge read electrode 8 controls the reading out of the electric charges into the charge transfer channel 5. A gap is formed between the photoelectric conversion element and the charge read electrode 8 in plan view.

Abstract: A MOS-type solid-state image pickup device, on a semiconductor substrate, includes a photoelectric conversion unit having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a transfer MOS transistor having a gate electrode disposed on an insulation film and transferring a charge carrier from a fourth semiconductor region. In addition, an amplifying MOS transistor having a gate electrode is connected to the fourth semiconductor region, and a fifth semiconductor region of the second conductivity type is continuously disposed to the second semiconductor region and under the gate electrode, and is disposed apart from the insulation film under the gate electrode of the transfer MOS transistor.

Abstract: An image sensor, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material.

Abstract: Provided is a solid-state CMOS image sensor, specifically a CMOS image sensor pixel that has stacked photo-sites, high sensitivity, and low dark current. In an image sensor including an array of pixels, each pixel includes: a standard photo-sensing and charge storage region formed in a first region under a surface portion of a substrate and collecting photo-generated carriers; a second charge storage region formed adjacent to the surface portion of the substrate and separated from the standard photo-sensing and charge storage region; and a potential barrier formed between the first region and a second region underneath the first region and diverting the photo-generated carriers from the second region to the second charge storage region.

Abstract: A solid-state imaging device includes a substrate having a first surface and a second surface, light being incident on the second surface side; a wiring layer disposed on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer gate disposed on the first surface of the substrate and adjacent to the photodetector, the transfer gate transferring a signal charge accumulated in the photodetector; and at least one control gate disposed on the first surface of the substrate and superposed on the photodetector, the control gate controlling the potential of the photodetector in the vicinity of the first surface.

Abstract: The invention concerns a sensor with silicon-containing components from whose sensitive detection element electrical signals relevant to a present analyte can be read out by means of a silicon semiconductor system. The invention is characterized in that the silicon-containing components are covered with a layer made of hydrophobic material in order to prevent unwanted signals caused by moisture.

Abstract: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens.

Abstract: A MOS-type solid-state image pickup device includes a photoelectric conversion unit having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, a third semiconductor region of the first conductivity type disposed at a light incident side of the second semiconductor region, and a transfer MOS transistor having the second semiconductor region, a fourth semiconductor region of the second conductivity type, and a gate electrode disposed on an insulating film on the first semiconductor region between the photoelectric conversion unit and the fourth semiconductor region to transfer a charge carrier from the second semiconductor region to the fourth semiconductor region. The photoelectric conversion unit and the transfer MOS transistor are disposed on a substrate.

Abstract: A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first charge storage region and between the first storage region and a floating diffusion region. A global shutter gate is formed to control the charge barrier and transfer charges from the photodiode to the first charge storage region by effectively lowering the first charge barrier. A transfer transistor acts to transfer charges from the first storage region to the floating diffusion region by reducing the second charge barrier.

Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

Abstract: A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over the pixel's photodiode. The VWG includes an upper light concentrator having a curved (e.g., parabolic) surface extending from a relatively wide upper opening to a relatively small lower opening. The VWG also includes a lower section extending between the lower opening of the light concentrator and the associated photodiode. A mirror coating is optionally formed on the surface of the VWG. An optional light-guiding material and/or color filter materials are disposed inside the VWG. An optional microlens is formed over the VWG.

Abstract: A CCD structure (20) tolerant to the adverse formation of traps resulting from exposure to irradiation by particles such as protons and neutrons is described. The CCD comprises an image plane (22) having a number of parallel transfer channels. Path defining structures (24), such as barrier implants, define a principal electron flow path through the channel, and define a number of secondary paths which converge on the principal path. The paths ensure that signal charge generated across the entire width of the channel is collected together into regions of smaller area so that the likelihood of interaction with traps is reduced, and charge containment is maintained near the optimum for all signal levels up to the full well.

Abstract: A charge accumulation region of a first conductivity type is buried in a semiconductor substrate. A charge transfer destination diffusion layer of the first conductivity type is formed on a surface of the semiconductor substrate. A transfer gate electrode is formed on the charge accumulation region, and charge is transferred from the charge accumulation region to the charge transfer destination diffusion layer.