Responsive To Non-electrical External Signal (e.g., Imager) Patents (Class 257/222)
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Patent number: 7235831Abstract: In order to reduce the capacitance of a light-receiving element, the present invention provides a light-receiving element which includes a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, provided on the first semiconductor region, a third semiconductor region of the first conductivity type, provided between the second semiconductor region and an insulating film and an electrode region of the second conductivity type, provided in the second semiconductor region where the third semiconductor region is absent on and above the second semiconductor region, and connected to an anode or cathode electrode consisting of a conductor.Type: GrantFiled: August 11, 2003Date of Patent: June 26, 2007Assignee: Canon Kabushiki KaishaInventors: Hiraku Kozuka, Toru Koizumi, Koji Sawada
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Patent number: 7235824Abstract: An active gate includes a substrate of a first conductivity type, a channel of a second conductivity type formed in the substrate, a first gate region of the first conductivity type formed in a corresponding first portion of the channel, and a first contact connected to the first gate region. The first gate region covers a first area, and the first contact covers a fraction of the first area. A pixel or register element includes an active gate, a second gate region of the first conductivity type formed in a corresponding second portion of the channel, and a second contact connected to the second gate region. The second gate region covers a second area and is spaced by a first gap from the first gate region. The second contact covers a fraction of the second area. The pixel or register element further includes a first gate electrode insulatively spaced from and disposed over the first gap.Type: GrantFiled: June 11, 2001Date of Patent: June 26, 2007Assignee: Dalsa, Inc.Inventor: Surendra Singh
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Patent number: 7233049Abstract: The prevent invention is to provide a solid-state imaging device having a electrode configuration applicable to a progressive scan, and able to reduce a obstruction of incident light at the periphery of a light receiving portion, a method of producing the same, a camera including the same. A first transfer electrode, a second transfer electrode, and a third transfer electrode which have a single layer transfer electrode configuration are repeatedly arranged in a vertical direction. The first transfer electrodes are connected in a horizontal direction by an inter-pixel interconnection formed in the same layer. Shunt interconnections are formed in the horizontal direction and in the vertical direction above the transfer layers. The shunt interconnection connected to the second transfer interconnection is formed on the inter-pixel interconnection. The shunt interconnection connected to the third transfer electrode is formed above the transfer electrodes.Type: GrantFiled: September 1, 2005Date of Patent: June 19, 2007Assignee: Sony CorporationInventor: Hideo Kanbe
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Patent number: 7230288Abstract: A solid-state image pickup device includes: a plurality of light receiving portions arranged in a matrix, and a vertical transfer register which is four-phase driven by first, second, third and fourth transfer electrodes of a three-layer structure. The vertical transfer register is provided for each of columns of the light receiving portions. The first and third transfer electrodes of the first layer are alternately arranged in a charge transfer direction, and the adjacent two of the first and third transfer electrodes extend in parallel to each other between the light receiving portions. With this solid-state image pickup device, the accumulated charge capacity of each transfer region composed of the adjacent transfer electrodes for two-phases is equalized and the area of the light receiving portion is increased irrespective of variations in processed dimension between the transfer electrodes.Type: GrantFiled: August 7, 2006Date of Patent: June 12, 2007Assignee: Sony CorporationInventors: Junji Yamane, Kunihiko Hikichi
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Patent number: 7227191Abstract: An optoelectronic component having a semiconductor chip containing a semiconductor layer sequence (6) with a radiation-emitting active zone (4), the semiconductor layer sequence (6) having sidewalls (10). A connection contact (9) is provided for impressing current into the active zone. A first current expansion layer (7) adjoins a semiconductor layer (5) of the semiconductor layer sequence (6) and a second current expansion layer (8) is provided between the semiconductor layer sequence (6) and the connection contact (9). The first current expansion layer (7) has a larger sheet resistance than the second current expansion layer (8) and forms an ohmic contact with the adjoining semiconductor layer (5). The second current expansion layer (8) is applied to a partial region of the first current expansion layer (7) which is at a distance from the sidewalls (10).Type: GrantFiled: May 2, 2005Date of Patent: June 5, 2007Assignee: Osram Opto Semiconductors GmbHInventors: Franz Eberhard, Uwe Strauss, Ulrich Zehnder, Andreas Weimar, Raimund Oberschmid
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Patent number: 7227199Abstract: Disclosed is a method of manufacturing an image sensor having light sensitivity over a photodiode equal in area to that of a unit pixel. The image sensor includes an image sensor comprising: a first semiconductor substrate doped with a first conductive dopant; a first diffusion layer formed in the semiconductor substrate and doped with a second conductive dopant; a second diffusion layer formed in the semiconductor substrate adjacent the first diffusion layer and having a width wider than a width of the first diffusion layer; a third diffusion layer doped with the first conductive dopant and formed at an exposed surface of the semiconductor substrate in the first diffusion layer; a gate electrode formed on the exposed surface and having a first edge adjacent to the third diffusion layer; and a fourth diffusion layer doped with the second conductive dopant and formed at the exposed surface adjacent a second edge of the gate electrode, the fourth diffusion layer defining a gap with the second diffusion layer.Type: GrantFiled: February 8, 2005Date of Patent: June 5, 2007Assignee: Hynix Semiconductor Inc.Inventor: Joon Hwang
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Patent number: 7224003Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.Type: GrantFiled: March 24, 2006Date of Patent: May 29, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
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Patent number: 7217961Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.Type: GrantFiled: January 26, 2006Date of Patent: May 15, 2007Assignee: Sony CorporationInventors: Keiji Tatani, Hideshi Abe, Masanori Ohashi, Atsushi Masagaki, Atsuhiko Yamamoto, Masakazu Furukawa
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Patent number: 7205525Abstract: A light conversion apparatus has a germanium-based photodiode, and a polysilicon-based receiving electrode for receiving light to be converted by the photodiode. The receiving electrode is coupled with the photodiode and permits the received light to substantially pass through it to the photodiode. The photodiode is capable of converting the received light into an electrical signal.Type: GrantFiled: September 5, 2003Date of Patent: April 17, 2007Assignee: Analog Devices, Inc.Inventor: John Yasaitis
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Patent number: 7199406Abstract: A method for manufacturing a transistor includes forming a semiconductor layer on a substrate, a first insulation film on the semiconductor layer, and a gate electrode on the first insulation film. The method also includes forming a source region, a channel region, and a drain region in the semiconductor layer and forming a second insulation film on the gate electrode. A source electrode and a drain electrode are formed on the second insulation film and are coupled to the source region and the drain region, respectively. The method further includes coupling the drain electrode to the gate electrode through a contact hole that is vertically above the channel region.Type: GrantFiled: November 5, 2004Date of Patent: April 3, 2007Assignee: Samsung SDI Co., Ltd.Inventors: Keum-Nam Kim, Ui-Ho Lee
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Patent number: 7199439Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.Type: GrantFiled: June 14, 2004Date of Patent: April 3, 2007Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Sidney B. Rigg, William M. Hiatt, Kyle K. Kirby, Peter A. Benson, James M. Wark, Alan G. Wood, David R. Hembree, Salman Akram, Charles M. Watkins
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Patent number: 7199405Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.Type: GrantFiled: October 20, 2004Date of Patent: April 3, 2007Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 7190008Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: GrantFiled: October 27, 2004Date of Patent: March 13, 2007Assignee: E Ink CorporationInventors: Karl R. Amundson, Andrew P. Ritenour, Gregg M. Duthaler, Paul S. Drzaic, Yu Chen, Peter T. Kazlas
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Patent number: 7187017Abstract: An image sensor provided with: a plurality of photodiodes arranged on a surface of a semiconductor substrate, the photodiodes each including a first region of a first conductivity type provided on the semiconductor substrate, a second region of a second conductivity type provided on the first region, the second conductivity type being different from the first conductivity type, and a signal extraction region of the second conductivity type provided on the second region; and an isolation region which electrically isolates the second regions of each adjacent pair of photodiodes from each other, the isolation region including a first trench provided between the second regions of the adjacent photodiodes and an oxide film provided on the first trench in the vicinity of surfaces of the second regions and having a greater width than the first trench.Type: GrantFiled: June 30, 2004Date of Patent: March 6, 2007Assignee: Rohm Co., Ltd.Inventors: Kensuke Sawase, Yuji Matsumoto, Kiyotaka Sawa
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Patent number: 7187018Abstract: A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed at least partially below the surface of the substrate and a photodiode is adjacent to the gate. The photodiode comprises a doped surface layer of a first conductivity type, and a doped region of a second conductivity type underlying the doped surface layer. The doped surface layer is at least partially above a level of the bottom of the gate.Type: GrantFiled: June 25, 2003Date of Patent: March 6, 2007Assignee: Micron Technology, Inc.Inventors: Chandra Mouli, Howard E. Rhodes
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Patent number: 7154136Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.Type: GrantFiled: February 20, 2004Date of Patent: December 26, 2006Assignee: Micron Technology, Inc.Inventors: Bryan G. Cole, Troy Sorensen
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Patent number: 7141833Abstract: Apart from a semiconductor substrate and a photosensitive region in the semiconductor substrate, which comprises a space charge zone region for generating a diffusion current portion and a diffusion region for generating a diffusion current portion, a photodiode includes an insulation means in the semiconductor substrate for at least partially confining the diffusion region against an adjacent surrounding region of the semiconductor substrate.Type: GrantFiled: November 19, 2004Date of Patent: November 28, 2006Assignee: Thomson Licensing SASInventors: Ingo Hehemann, Armin Kemna
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Patent number: 7138696Abstract: An image pickup apparatus includes plural light receiving areas arranged two-dimensionally and a vertical scanning circuit composed of plural unit circuit stages arranged in the vertical direction and a horizontal scanning circuit composed of plural unit circuit stages arranged in the horizontal direction for selecting and reading the plural light receiving areas in succession and in which the vertical scanning circuit and the horizontal scanning circuit are arranged in spaces between the light receiving areas. A crossing area of the vertical scanning circuit and the horizontal scanning circuit, in a space between the light receiving areas, is divided into two areas, and at least a unit circuit of the horizontal scanning circuit is provided in one of the two areas while at least a unit circuit of the vertical scanning circuit is provided in the other of the two areas.Type: GrantFiled: October 16, 2002Date of Patent: November 21, 2006Assignee: Canon Kabushiki KaishaInventor: Tomoyuki Noda
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Patent number: 7138671Abstract: A first p+-type region on a surface of a photodiode unit is formed over a region from a surface of the photodiode unit through a surface of a signal charge read-out unit until reaching the charge transfer unit. Also, the following structure is adapted: the structure in which a boundary between the first p+-type region and a p++-type region is not on a same plane with a boundary of an n-type impurity region which forms the photodiode unit on a side of the signal charge read-out unit. Further, a second p+-type region is formed between the first p+-type region and the p++-type region on the surface of the photodiode unit. The second p+-type region has an impurity concentration between the impurity concentrations of the first p+-type region and the p++-type region.Type: GrantFiled: May 26, 2005Date of Patent: November 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Jun Hirai, Tooru Yamada
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Patent number: 7122831Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.Type: GrantFiled: August 27, 2004Date of Patent: October 17, 2006Assignee: TPO Displays Corp.Inventor: Naoki Sumi
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Patent number: 7112778Abstract: Pixel electrodes on an active-matrix substrate do not overlap signal lines and scanning lines, and satisfy a relation X1>Y1, where X1 is the gap between the pixel electrodes and the signal lines, and Y1 is the gap between the pixel electrodes and the scanning lines. As a result, a large-area and high-resolution electromagnetic wave detector is realized with an improved S/N ratio, even with an active-matrix array providing a large area for the charge collecting electrodes.Type: GrantFiled: January 26, 2004Date of Patent: September 26, 2006Assignees: Sharp Kabushiki Kaisha, Shimadzu CorporationInventors: Yoshihiro Izumi, Kenji Sato
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Patent number: 7105867Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) comprises a light-receiving sensor section disposed on the surface layer portion of a substrate (21) for performing a photoelectric conversion, a charge transfer section for transferring a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at its position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.Type: GrantFiled: March 8, 2005Date of Patent: September 12, 2006Assignee: Sony CorporationInventors: Yasushi Maruyama, Hideshi Abe
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Patent number: 7102185Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.Type: GrantFiled: June 21, 2004Date of Patent: September 5, 2006Assignee: Eastman Kodak CompanyInventors: David N. Nichols, David L. Losee, Christopher Parks
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Patent number: 7102180Abstract: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.Type: GrantFiled: June 24, 2005Date of Patent: September 5, 2006Assignee: Micron Technology, Inc.Inventors: Howard Rhodes, Jeff McKee
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Patent number: 7091463Abstract: Each transfer electrode of a charge transfer unit is made of a main electrode layer and subsidiary electrode layers formed on the side walls of the main electrode layer. The upper surfaces of the transfer electrodes are flush with each other. A charge coupled device having a practically sufficient charge transfer efficiency can be provided. If this charge coupled device is used for an image pickup apparatus, the distance between photoelectric conversion elements and micro lenses can be shortened.Type: GrantFiled: December 30, 2002Date of Patent: August 15, 2006Assignee: Fuji Photo Film Co., LTDInventors: Noriaki Suzuki, Kazuaki Ogawa, Tohru Hachiya, Teiji Azumi
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Patent number: 7091530Abstract: A charge-coupled device imager including an array of super pixels disposed in a semiconductor substrate having a surface that is accessible to incident illumination. For each super pixel there is provided a plurality of subpixels which each correspond to one in the sequence of image frames. Each subpixel includes a doped photogenerated charge collection channel region opposite the illumination-accessible substrate surface, a charge collection channel region control electrode, doped charge drain regions adjacent to the channel region, a charge drain region control electrode, and a doped charge collection control region. To each subpixel are provided channel region and drain region control voltage connections, for independent collection and storage of photogenerated charge from the substrate at the charge collection channel region of a selected subpixel during one in the sequence of image frames and for drainage of photogenerated charge from the substrate to a drain region.Type: GrantFiled: July 2, 2003Date of Patent: August 15, 2006Assignee: Massachusetts Institute of TechnologyInventors: Robert K. Reich, Bernard B. Kosicki, Jonathan C. Twichell, Barry E. Burke, Dennis D. Rathman
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Patent number: 7091531Abstract: A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate having source and drain regions commonly connected to the floating diffusion region. The gate has an intrinsic capacitance which, when the gate is activated, is added to the capacitance of the floating diffusion region, providing a low conversion gain readout. When the gate is off, the floating diffusion region capacitance is minimized, providing a high conversion gain readout. The gate may also be selectively switched to mid-level. At mid-level, a mid-level conversion gain, which is between the high and low conversion gains, readout is provided, but the gate still provides some capacitance to prevent the floating diffusion region from saturating.Type: GrantFiled: April 7, 2004Date of Patent: August 15, 2006Assignee: Micron Technology, Inc.Inventor: Christian Boemler
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Patent number: 7091532Abstract: An image sensor includes a substrate containing photosensitive areas; an insulator spanning the substrate; and a first and second layer of a multi-layer metalization structure wherein the first layer forms the light shield regions over portions of the photosensitive area as well as forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area, and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging area.Type: GrantFiled: January 25, 2005Date of Patent: August 15, 2006Assignee: Eastman Kodak CompanyInventor: Eric G. Stevens
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Patent number: 7087939Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) includes a light-receiving sensor section disposed on the surface layer portion of a substrate (21) that performs a photoelectric conversion, a charge transfer section that transfers a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at a position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.Type: GrantFiled: March 8, 2005Date of Patent: August 8, 2006Assignee: Sony CorporationInventors: Yasushi Maruyama, Hideshi Abe
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Patent number: 7081647Abstract: A microelectromechanical system includes a substrate, a transducer supported on the substrate and a conductor layer, which is also supported on the substrate and electrically connected to the transducer. The transducer includes a portion made of silicon or a silicon compound. The conductor layer is made of a refractory conductor, which includes, as its main ingredient, at least one element selected from the group consisting of copper, gold and silver. At least a portion of the conductor layer is located at an intermediate level between the silicon or silicon compound portion of the transducer and the substrate.Type: GrantFiled: September 16, 2004Date of Patent: July 25, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yoshihiro Mushika
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Patent number: 7078670Abstract: A charge coupled device (CCD) includes a low noise charge gain circuit that amplifies charge of a cell dependent upon the charge accumulated by the cell. The low noise charge gain circuit receives clocking signals, such as from an input diode, which allow charge to accumulate in a reservoir well and then flow into a receiving well. The low noise charge gain circuit also receives a voltage signal corresponding to charge accumulated on an associated cell. The amount of charge flowing into the receiving well depends on this voltage signal.Type: GrantFiled: September 9, 2004Date of Patent: July 18, 2006Assignee: Imagerlabs, Inc.Inventors: Gene Atlas, Mark Wadsworth, Richard H. Kullman, Sarit Neter
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Patent number: 7078746Abstract: Pixel cells are provided which employ a gate capacitor associated with the floating diffusion node to selectively increase the storage capacity of the floating diffusion node. The gate capacitor can be formed at the same time as the same process steps used to form other gates of the pixel cells. The inherent capacity of the storage node alone may be sufficient under low light conditions. Higher light conditions may result in selective activation of the gate capacitor, thus increasing the capacity of the storage node with the additional capacity provided by the gate capacitor. The invention produces high dynamic range and high output signal without charge sharing or lag output signal. Methods of forming such pixel cells can be applied in CMOS and CCD imaging devices, image pixel arrays in CMOS and CCD imaging devices, and CMOS and CCD imager systems.Type: GrantFiled: July 15, 2003Date of Patent: July 18, 2006Assignee: Micron Technology, Inc.Inventor: Sungkwon C. Hong
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Patent number: 7075128Abstract: A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting the channel region, a floating diffusion region formed continuous from the channel region, and an output transistor having a gate connected to the floating diffusion region. In a region where the output transistor is formed, the dopant density profile in the depth direction of the semiconductor substrate exhibits the maximum value relative to a middle region.Type: GrantFiled: February 5, 2004Date of Patent: July 11, 2006Assignee: Sanyo Electric Co., Ltd.Inventor: Yoshihiro Okada
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Patent number: 7071505Abstract: An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided between a floating diffusion region and a gate of a source follower output transistor, with the contact also electrically connected to a storage capacitor. The storage capacitor provides additional charge storage capacity to the floating diffusion region. In addition, an associated reset transistor has different dopant characteristics in the source and drain regions. The floating diffusion region may be used in the pixels of a CMOS imager or in the output stage of a CCD imager.Type: GrantFiled: January 8, 2004Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 7071501Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.Type: GrantFiled: December 30, 2003Date of Patent: July 4, 2006Assignee: DongbuAnam Semiconductor Inc.Inventor: James Jang
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Patent number: 7061030Abstract: A semiconductor device includes a transfer channel for transferring charge generated by photoelectric conversion, an insulating film formed on the transfer channel, and a transfer electrode for applying a transfer voltage to the transfer channel via the insulating film. The insulating film has the first thickness and a second thickness that is thinner than the first thickness. The insulating film has the first thickness below both ends of the transfer electrode in a width direction of the transfer channel that is orthogonal to a charge transfer direction through the transfer channel, and the insulating film has the second thickness on a part including a center of the transfer channel in the width direction.Type: GrantFiled: September 1, 2004Date of Patent: June 13, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hiroshi Tanaka
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Patent number: 7061031Abstract: A method of fabricating a high-sensitivity image sensor is disclosed. The disclosed method comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon substrate to form a P-type region; forming crossed active silicon by patterning the rest of the active silicon not etched while the active silicon is etched to expose the N-type silicon substrate; implanting P-type ions into first two predetermined regions facing each other of the crossed active silicon to form P-type regions; implanting N-type ions into second two predetermined regions facing each other except for the P-type regions of the crossed active silicon to form N-type regions; forming a gate oxide layer and a gate electrode on the crossed active silicon; and forming a connection part to connect the P-type region of the crossed active silicon to the P-type region of the silicon substrate.Type: GrantFiled: December 30, 2004Date of Patent: June 13, 2006Assignee: Korea Electronics Technology InstituteInventor: Hoon Kim
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Patent number: 7057302Abstract: A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode.Type: GrantFiled: August 3, 2004Date of Patent: June 6, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Matsuzawa, Ken Uchida, Takahiro Nakauchi
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Patent number: 7045838Abstract: Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step.Type: GrantFiled: October 31, 2003Date of Patent: May 16, 2006Assignee: International Business Machines CorporationInventor: Daniel C. Worledge
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Patent number: 7038259Abstract: CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in periphery circuits have different requirements from the capacitors used in the pixel itself. Dual stack capacitors comprising two dielectric layers may be provided to achieve low leakage and high capacitance. A single masking step may be provided such that one region has a dual dielectric capacitor and a second region has a single dielectric capacitor. A different dielectric may also be provided in one region compared to another region wherein the inter-electrode insulator comprises a single dielectric in both regions.Type: GrantFiled: October 22, 2003Date of Patent: May 2, 2006Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 7034274Abstract: A light receiving device using a new method of controlling sensitivity and a spatial information detecting apparatus using the same technical concept are provided. This light receiving device comprises a photoelectric converter for receiving a light at a light receiving surface and generating amounts of electric charges corresponding to an intensity of received light; electrodes formed on the photoelectric converter; a charge collection area induced in the photoelectric converter by applying a control voltage to the electrodes to collect at least part of the electric charges generated in the photoelectric converter; a charge ejector for outputting the electric charges from the charge collection area; and a sensitivity controller for controlling the number of the electrodes, to which the control voltage is applied, to change size of the charge collection area in the light receiving surface of the photoelectric converter.Type: GrantFiled: June 6, 2003Date of Patent: April 25, 2006Assignee: Matsushita Electric Works, Ltd.Inventors: Yusuke Hashimoto, Yuji Takada, Fumikazu Kurihara
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Patent number: 6998657Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.Type: GrantFiled: October 21, 2003Date of Patent: February 14, 2006Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 6979841Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).Type: GrantFiled: September 9, 2003Date of Patent: December 27, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hisashi Ohtani
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Patent number: 6974975Abstract: A solid-state imaging device comprising: a semiconductor substrate having a first surface; and a plurality of light-receiving sections arranged in an array pattern on the first surface of the semiconductor substrate, the solid-state imaging device reading a stored electric charge in each of the light-receiving sections, wherein each of the light-receiving sections comprises: a first signal electric charge storage section that stores a first signal electric charge corresponding to an incident light energy; and a second signal electric charge storage section that stores at least part of an excessive electric charge, the at least part of the excessive electric charge being captured from the first signal electric charge storage section, when the electric charge stored in the first signal electric charge storage section exceeds a saturated electric charge amount of the first signal electric charge section to form the excessive electric charge.Type: GrantFiled: April 29, 2004Date of Patent: December 13, 2005Assignee: Fuji Photo Film Co., Ltd.Inventor: Makoto Shizukuishi
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Patent number: 6974973Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.Type: GrantFiled: November 8, 2002Date of Patent: December 13, 2005Assignee: Micron Technology, Inc.Inventors: Giuseppe Rossi, Gennadiy A. Agranov
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Patent number: 6974980Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.Type: GrantFiled: April 29, 2005Date of Patent: December 13, 2005Assignee: Sony CorporationInventor: Toshinobu Sugiyama
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Patent number: 6969877Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.Type: GrantFiled: April 29, 2005Date of Patent: November 29, 2005Assignee: Sony CorporationInventor: Toshinobu Sugiyama
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Patent number: 6965135Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.Type: GrantFiled: April 29, 2005Date of Patent: November 15, 2005Assignee: Sony CorporationInventor: Toshinobu Sugiyama
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Patent number: 6960796Abstract: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.Type: GrantFiled: November 26, 2002Date of Patent: November 1, 2005Assignee: Micron Technology, Inc.Inventors: Howard Rhodes, Jeff McKee
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Patent number: 6956240Abstract: In an active matrix type light emitting device, a top surface exit type light emitting device in which an anode formed at an upper portion of an organic compound layer becomes a light exit electrode is provided. In a light emitting element made of a cathode, an organic compound layer and an anode, a protection film is formed in an interface between the anode that is a light exit electrode and the organic compound layer. The protection film formed on the organic compound layer has transmittance in the range of 70 to 100%, and when the anode is deposited by use of the sputtering method, a sputtering damage to the organic compound layer can be inhibited from being inflicted.Type: GrantFiled: October 29, 2002Date of Patent: October 18, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toshimitsu Konuma, Hiroko Yamazaki