Responsive To Non-electrical External Signal (e.g., Imager) Patents (Class 257/222)
  • Patent number: 7091530
    Abstract: A charge-coupled device imager including an array of super pixels disposed in a semiconductor substrate having a surface that is accessible to incident illumination. For each super pixel there is provided a plurality of subpixels which each correspond to one in the sequence of image frames. Each subpixel includes a doped photogenerated charge collection channel region opposite the illumination-accessible substrate surface, a charge collection channel region control electrode, doped charge drain regions adjacent to the channel region, a charge drain region control electrode, and a doped charge collection control region. To each subpixel are provided channel region and drain region control voltage connections, for independent collection and storage of photogenerated charge from the substrate at the charge collection channel region of a selected subpixel during one in the sequence of image frames and for drainage of photogenerated charge from the substrate to a drain region.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: August 15, 2006
    Assignee: Massachusetts Institute of Technology
    Inventors: Robert K. Reich, Bernard B. Kosicki, Jonathan C. Twichell, Barry E. Burke, Dennis D. Rathman
  • Patent number: 7087939
    Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) includes a light-receiving sensor section disposed on the surface layer portion of a substrate (21) that performs a photoelectric conversion, a charge transfer section that transfers a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at a position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: August 8, 2006
    Assignee: Sony Corporation
    Inventors: Yasushi Maruyama, Hideshi Abe
  • Patent number: 7081647
    Abstract: A microelectromechanical system includes a substrate, a transducer supported on the substrate and a conductor layer, which is also supported on the substrate and electrically connected to the transducer. The transducer includes a portion made of silicon or a silicon compound. The conductor layer is made of a refractory conductor, which includes, as its main ingredient, at least one element selected from the group consisting of copper, gold and silver. At least a portion of the conductor layer is located at an intermediate level between the silicon or silicon compound portion of the transducer and the substrate.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: July 25, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshihiro Mushika
  • Patent number: 7078670
    Abstract: A charge coupled device (CCD) includes a low noise charge gain circuit that amplifies charge of a cell dependent upon the charge accumulated by the cell. The low noise charge gain circuit receives clocking signals, such as from an input diode, which allow charge to accumulate in a reservoir well and then flow into a receiving well. The low noise charge gain circuit also receives a voltage signal corresponding to charge accumulated on an associated cell. The amount of charge flowing into the receiving well depends on this voltage signal.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: July 18, 2006
    Assignee: Imagerlabs, Inc.
    Inventors: Gene Atlas, Mark Wadsworth, Richard H. Kullman, Sarit Neter
  • Patent number: 7078746
    Abstract: Pixel cells are provided which employ a gate capacitor associated with the floating diffusion node to selectively increase the storage capacity of the floating diffusion node. The gate capacitor can be formed at the same time as the same process steps used to form other gates of the pixel cells. The inherent capacity of the storage node alone may be sufficient under low light conditions. Higher light conditions may result in selective activation of the gate capacitor, thus increasing the capacity of the storage node with the additional capacity provided by the gate capacitor. The invention produces high dynamic range and high output signal without charge sharing or lag output signal. Methods of forming such pixel cells can be applied in CMOS and CCD imaging devices, image pixel arrays in CMOS and CCD imaging devices, and CMOS and CCD imager systems.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: July 18, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Sungkwon C. Hong
  • Patent number: 7075128
    Abstract: A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting the channel region, a floating diffusion region formed continuous from the channel region, and an output transistor having a gate connected to the floating diffusion region. In a region where the output transistor is formed, the dopant density profile in the depth direction of the semiconductor substrate exhibits the maximum value relative to a middle region.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: July 11, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Yoshihiro Okada
  • Patent number: 7071505
    Abstract: An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided between a floating diffusion region and a gate of a source follower output transistor, with the contact also electrically connected to a storage capacitor. The storage capacitor provides additional charge storage capacity to the floating diffusion region. In addition, an associated reset transistor has different dopant characteristics in the source and drain regions. The floating diffusion region may be used in the pixels of a CMOS imager or in the output stage of a CCD imager.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 7071501
    Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: July 4, 2006
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: James Jang
  • Patent number: 7061031
    Abstract: A method of fabricating a high-sensitivity image sensor is disclosed. The disclosed method comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon substrate to form a P-type region; forming crossed active silicon by patterning the rest of the active silicon not etched while the active silicon is etched to expose the N-type silicon substrate; implanting P-type ions into first two predetermined regions facing each other of the crossed active silicon to form P-type regions; implanting N-type ions into second two predetermined regions facing each other except for the P-type regions of the crossed active silicon to form N-type regions; forming a gate oxide layer and a gate electrode on the crossed active silicon; and forming a connection part to connect the P-type region of the crossed active silicon to the P-type region of the silicon substrate.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: June 13, 2006
    Assignee: Korea Electronics Technology Institute
    Inventor: Hoon Kim
  • Patent number: 7061030
    Abstract: A semiconductor device includes a transfer channel for transferring charge generated by photoelectric conversion, an insulating film formed on the transfer channel, and a transfer electrode for applying a transfer voltage to the transfer channel via the insulating film. The insulating film has the first thickness and a second thickness that is thinner than the first thickness. The insulating film has the first thickness below both ends of the transfer electrode in a width direction of the transfer channel that is orthogonal to a charge transfer direction through the transfer channel, and the insulating film has the second thickness on a part including a center of the transfer channel in the width direction.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroshi Tanaka
  • Patent number: 7057302
    Abstract: A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Matsuzawa, Ken Uchida, Takahiro Nakauchi
  • Patent number: 7045838
    Abstract: Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: May 16, 2006
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7038259
    Abstract: CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in periphery circuits have different requirements from the capacitors used in the pixel itself. Dual stack capacitors comprising two dielectric layers may be provided to achieve low leakage and high capacitance. A single masking step may be provided such that one region has a dual dielectric capacitor and a second region has a single dielectric capacitor. A different dielectric may also be provided in one region compared to another region wherein the inter-electrode insulator comprises a single dielectric in both regions.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 7034274
    Abstract: A light receiving device using a new method of controlling sensitivity and a spatial information detecting apparatus using the same technical concept are provided. This light receiving device comprises a photoelectric converter for receiving a light at a light receiving surface and generating amounts of electric charges corresponding to an intensity of received light; electrodes formed on the photoelectric converter; a charge collection area induced in the photoelectric converter by applying a control voltage to the electrodes to collect at least part of the electric charges generated in the photoelectric converter; a charge ejector for outputting the electric charges from the charge collection area; and a sensitivity controller for controlling the number of the electrodes, to which the control voltage is applied, to change size of the charge collection area in the light receiving surface of the photoelectric converter.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: April 25, 2006
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Yusuke Hashimoto, Yuji Takada, Fumikazu Kurihara
  • Patent number: 6998657
    Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: February 14, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 6979841
    Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: December 27, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 6974980
    Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: December 13, 2005
    Assignee: Sony Corporation
    Inventor: Toshinobu Sugiyama
  • Patent number: 6974973
    Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: December 13, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Rossi, Gennadiy A. Agranov
  • Patent number: 6974975
    Abstract: A solid-state imaging device comprising: a semiconductor substrate having a first surface; and a plurality of light-receiving sections arranged in an array pattern on the first surface of the semiconductor substrate, the solid-state imaging device reading a stored electric charge in each of the light-receiving sections, wherein each of the light-receiving sections comprises: a first signal electric charge storage section that stores a first signal electric charge corresponding to an incident light energy; and a second signal electric charge storage section that stores at least part of an excessive electric charge, the at least part of the excessive electric charge being captured from the first signal electric charge storage section, when the electric charge stored in the first signal electric charge storage section exceeds a saturated electric charge amount of the first signal electric charge section to form the excessive electric charge.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: December 13, 2005
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Makoto Shizukuishi
  • Patent number: 6969877
    Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: November 29, 2005
    Assignee: Sony Corporation
    Inventor: Toshinobu Sugiyama
  • Patent number: 6965135
    Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: November 15, 2005
    Assignee: Sony Corporation
    Inventor: Toshinobu Sugiyama
  • Patent number: 6960796
    Abstract: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: November 1, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Howard Rhodes, Jeff McKee
  • Patent number: 6956240
    Abstract: In an active matrix type light emitting device, a top surface exit type light emitting device in which an anode formed at an upper portion of an organic compound layer becomes a light exit electrode is provided. In a light emitting element made of a cathode, an organic compound layer and an anode, a protection film is formed in an interface between the anode that is a light exit electrode and the organic compound layer. The protection film formed on the organic compound layer has transmittance in the range of 70 to 100%, and when the anode is deposited by use of the sputtering method, a sputtering damage to the organic compound layer can be inhibited from being inflicted.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: October 18, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshimitsu Konuma, Hiroko Yamazaki
  • Patent number: 6946694
    Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: September 20, 2005
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Eiichi Okamoto, Shunsuke Tanaka, Shinji Uya
  • Patent number: 6943391
    Abstract: Tensile or compressive stress may be added in one or more selected locations to the biaxial residual stress existing in the channel of a semiconductor device, such as a MOSFET. The periphery of the active area containing the channel is modified by following layout procedures that result in forming outward protrusions of or inward depressions in the periphery of the active area and its surrounding shallow trench isolation during generally otherwise conventional fabrication of the device.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: September 13, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Hwa Chi, Wai-Yi Lien
  • Patent number: 6943070
    Abstract: A complementary metal oxide semiconductor (CMOS) image sensor includes at least a non-single-crystal-silicone-base substrate, an opaque layer, a polysilicon layer, a source, a drain, a gate dielectric layer, a first transparent gate electrode, and a second gate transparent gate electrode. The opaque layer is formed on the non-single-crystal-silicone-base substrate, and the polysilicon layer, formed on the opaque layer, has a charge-generating region. The source and the drain are formed in the polysilicon layer, and a pre-channel region is formed between the source and the drain. The source is located between the pre-channel region and the charge-generating region. The gate dielectric layer is formed on the polysilicon layer, and the first and the second transparent gate electrodes, formed on the gate dielectric layer, are respectively located above the charge-generating region and the pre-channel region.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: September 13, 2005
    Assignee: AU Optronics Corp.
    Inventor: Chien-Sheng Yang
  • Patent number: 6943719
    Abstract: A signal processing circuit outputs a digital word responsive to incident light, and includes an analog integrated circuit having a first input terminal receiving a first analog signal during a first active period of a first switching signal and a second input terminal receiving a time varying reference signal; an inverter circuit inverting and amplifying an output of the analog integrated circuit responsive to an activated enable signal; and an output circuit generating the digital word. During a second active period of the first switching signal, the first input terminal is coupled to a data line for receiving a second analog signal corresponding to image charges of an image input element. The enable signal is deactivated between end points of the first and second active periods of the first switching signal.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: September 13, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Yun, Dong-Hun Lee
  • Patent number: 6936873
    Abstract: A solid state imaging device includes a transparent insulation film. The insulation film is laminated on transfer electrodes over the power supply lines. A transparent protection film, which has a refractive index that is greater than that of the insulation film, is laminated on the insulation film. The transparent insulation film has portions above the channels in which the thickness continuously increases from the center of adjacent channels to the associated channel separating region.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: August 30, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Minoru Konishi
  • Patent number: 6933528
    Abstract: An in-plane switching mode active matrix type liquid crystal display device includes a first substrate, a second substrate located opposing the first substrate, and a liquid crystal layer sandwiched between the first and second substrates. The first substrate includes a thin film transistor, a pixel electrode, a common electrode, a data line, a scanning line, and a common electrode line. The scanning line and the common electrode line are formed in a common layer in parallel with each other. The common electrode overlaps the data line and the scanning line with an interlayer insulating film existing therebetween. The common electrode line is singly formed at either side about the scanning line. The common electrode is electrically connected to the common electrode line through a contact hole formed throughout the interlayer insulating film, and shields a gap formed between the scanning line and the common electrode line.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: August 23, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Kunimasa Itakura, Shinichi Nishida, Kimikazu Matsumoto
  • Patent number: 6909126
    Abstract: An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is tied to the same potential of a substrate of the imager cell and is disposed between the photoreceptor and the sense node in order to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, and an output amplifier coupled to the sense node. Control circuitry supplies a photoreceptor readout clock to the photoreceptor. The readout clock includes an integration period and a transfer period. According to various embodiments of the invention, the imager cell provides improved noise performance, selective charge capacities, and improved blue light response beyond that of conventional imager cells.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: June 21, 2005
    Assignee: ESS Technology, Inc.
    Inventor: Jim Janesick
  • Patent number: 6903391
    Abstract: A solid state image pickup device includes: a semiconductor substrate defining light receiving areas; pixels formed in the light receiving areas, each pixel including a high and a low sensitivity photoelectric conversion element; a light shielding film formed above the light receiving areas and having an opening above each pixel, the opening exposing at least a partial area of the high and the low sensitivity photoelectric conversion element; an on-chip micro lens formed above each opening, the on-chip micro lens converging incidence light; and an inner lens formed between the light shielding film and the on-chip micro lens and above the opening, the inner lens being disposed so that the inner lens receives light converged by the on-chip micro lens, excluding a portion of the light, and further converges the received light to make the portion of the light propagate toward the opening without passing through the inner lens.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: June 7, 2005
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Yutaka Takeuchi, Masako Sato, Mariko Nakamura
  • Patent number: 6900480
    Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: May 31, 2005
    Assignee: Sony Corporation
    Inventor: Toshinobu Sugiyama
  • Patent number: 6891242
    Abstract: An array of photodetectors intended to be hybridized on a readout circuit and fabricated from a wafer in semiconductor material. The wafer is divided into pixels, the pixels being separated from one another by walls formed crosswise over the entire thickness of the wafer, the hybridization surface having connection pads enabling hybridization of the photodetector array to the readout circuit.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: May 10, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Pierre Gidon, Philippe Pantigny
  • Patent number: 6891209
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: May 10, 2005
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 6888214
    Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: May 3, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Mouli, Howard Rhodes
  • Patent number: 6881992
    Abstract: A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: April 19, 2005
    Assignee: SMAL Camera Technologies
    Inventors: Hae-Seung Lee, Keith Glen Fife
  • Patent number: 6878918
    Abstract: A circuit and method are described which suppresses reset noise in active pixel sensor arrays. A circuit having a number of N? wells formed in a P? silicon epitaxial layer or a number of P? wells formed in an N? silicon epitaxial layer is provided. A pixel is formed in each of the wells so that each of the wells is surrounded by silicon of the opposite polarity and an array of pixels is formed. Means are provided for selectively combining or binning adjacent N? or P? wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated. The reset is accomplished using a PMOS transistor formed in each N? well or an NMOS transistor formed in each P? well. The selective binning is accomplished using NMOS or PMOS transistors formed in the region between adjacent wells.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: April 12, 2005
    Assignee: Dialdg Semiconductor GmbH
    Inventor: Taner Dosluoglu
  • Patent number: 6853045
    Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: February 8, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 6853005
    Abstract: A camera module for a mobile device is reduced in size and manufacturing cost. A filter material made of a multi-layer thin film is bonded to a surface of a lens which is bonded to a surface of an image sensor chip. The filter material is a filter to block radiation within a predetermined range of wave length in an incident radiation to the lens, for example, an IR filter to block infrared radiation. An iris material made of a film such as an acrylic film or a polyolefin film is bonded to the lens covered with the filter material.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: February 8, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Osamu Ikeda
  • Patent number: 6838301
    Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: January 4, 2005
    Assignee: California Institute of Technology
    Inventors: Xinyu Zheng, Bedabrata Pain
  • Publication number: 20040259293
    Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.
    Type: Application
    Filed: February 27, 2003
    Publication date: December 23, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Tooru Yamada
  • Patent number: 6833601
    Abstract: A semiconductor device includes a plurality of photoelectric conversion photodiodes provided on a silicon substrate, and a refractive index matching film provided on each of the photodiodes. The refractive index matching film is composed of an insulating compound layer represented by SiOxNy (0≦x and y) assuming that the molar ratio of silicon, oxygen and nitrogen of the compound layer is 1:x:y. The oxygen content of the compound layer is the lowest at the silicon interface with each photodiode and the highest in an upper portion of the compound layer, and the nitrogen content is the highest at the silicon interface with each photodiode and the lowest in the upper portion of the compound layer. Therefore, multiple reflection can be decreased to improve light receiving sensitivity, as compared with a case in which a SiN single layer and a SiO2 single layer are laminated.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: December 21, 2004
    Assignee: Sony Corporation
    Inventor: Ichiro Murakami
  • Publication number: 20040251476
    Abstract: A radiation shielded and packaged integrated circuit semiconductor device includes a lid secured to a base to enclose an integrated circuit die within, wherein the lid and the base are each constructed from a high Z material to prevent radiation from penetrating therethrough. Another embodiment includes a die attach slug constructed from a high Z material disposed between the integrated circuit die and the base, in combination with a high Z material lid to substantially block incident radiation.
    Type: Application
    Filed: April 9, 2004
    Publication date: December 16, 2004
    Applicant: Maxwell Technologies, Inc.
    Inventors: David J. Strobel, David R. Czajkowski
  • Publication number: 20040245551
    Abstract: The invention provides an electro-optic device that includes a frame (i.e., frame-shaped pattern) disposed on a frame area in a TFT array substrate. The frame area is disposed between an image display area and a peripheral area. The frame is formed of the same film as capacitor electrodes, and is disposed at at least a part of the frame area. The frame is formed of the same film as wiring connected to an external circuit-connecting terminal. Accordingly, the electro-optic device can prevent the generation of an image caused by light leakage at the periphery of the image as much as possible, and thereby improve image quality.
    Type: Application
    Filed: April 19, 2004
    Publication date: December 9, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Masao Murade
  • Patent number: 6828601
    Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: December 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mahito Shinohara
  • Publication number: 20040238856
    Abstract: In the method, at least one layer-structured plane OLED component is formed on a plane substrate (10) with a method known per se, which component comprises a first electrode (20), an electrically conductive polymer (30), a light emitting material (50) and a second electrode (70), as well as intermediate and protective layers (40, 60, 80, 90) The plane OLED film comprising the substrate (10) and at least one OLED component is formed in a plastic forming process known per se by using vacuum, pressure, compression or a combination of these so that at least one OLED area ascended from the plane OLED component is formed on the plane OLED film. The OLED component comprises at least one OLED area ascended from the plane surface.
    Type: Application
    Filed: July 8, 2004
    Publication date: December 2, 2004
    Inventors: Tapio Mkel, Heikki Isotalo, Jukka Lappalainen
  • Patent number: 6825497
    Abstract: An active matrix substrate for a liquid crystal display and method of forming the same. To form the active matrix substrate five masks are needed. The first mask forms gate lines on the transparent substrate. The second mask patterns a stacked layer of a metal layer/an n-doped layer/a semiconductor layer formed on a gate insulating layer to form data lines. After forming a low k dielectric layer, the third mask forms openings therein. The forth mask patterns pixel electrodes and conducting lines with source pattern on the low k dielectric layer and further patterns the metal layer and the n-doped layer. After depositing a passivating layer the fifth mask defines the passivating layer.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: November 30, 2004
    Assignee: Au Optronics Corp.
    Inventor: Han-Chung Lai
  • Publication number: 20040232454
    Abstract: An object of the present invention is to provide a large-size light-emitting device from which uniform light emission can be obtained.
    Type: Application
    Filed: June 17, 2004
    Publication date: November 25, 2004
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Atsuo Hirano, Koichi Ota, Naohisa Nagasaka
  • Publication number: 20040232455
    Abstract: A method for increasing the bonding strength between a die and a housing for the die is described where a micro-electromechanical system (MEMS) device is formed on the die. The method includes depositing a plurality of contacts of bonding material between the substrate and die, and forming a bond between the die and the housing by applying at least 25,000 kilograms of force per gram of bonding material to the housing, the contacts, and the die.
    Type: Application
    Filed: June 28, 2004
    Publication date: November 25, 2004
    Inventors: Jon B. DCamp, Harlan L. Curtis, Lori A. Dunaway, Max C. Glenn
  • Publication number: 20040232453
    Abstract: A semiconductor device of the present invention includes a semiconductor layer 10, an insulation gate type heavy insulated transistor 200 and an insulation gate type light insulated transistor 300 having different drain-source breakdown voltages and formed on the semiconductor layer 10, and a resistive impurity layer 24 formed on the semiconductor layer 10.
    Type: Application
    Filed: January 16, 2004
    Publication date: November 25, 2004
    Inventor: Tetsumasa Sato