Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor includes at least a non-single-crystal-silicone-base substrate, an opaque layer, a polysilicon layer, a source, a drain, a gate dielectric layer, a first transparent gate electrode, and a second gate transparent gate electrode. The opaque layer is formed on the non-single-crystal-silicone-base substrate, and the polysilicon layer, formed on the opaque layer, has a charge-generating region. The source and the drain are formed in the polysilicon layer, and a pre-channel region is formed between the source and the drain. The source is located between the pre-channel region and the charge-generating region. The gate dielectric layer is formed on the polysilicon layer, and the first and the second transparent gate electrodes, formed on the gate dielectric layer, are respectively located above the charge-generating region and the pre-channel region.

Abstract: A signal processing circuit outputs a digital word responsive to incident light, and includes an analog integrated circuit having a first input terminal receiving a first analog signal during a first active period of a first switching signal and a second input terminal receiving a time varying reference signal; an inverter circuit inverting and amplifying an output of the analog integrated circuit responsive to an activated enable signal; and an output circuit generating the digital word. During a second active period of the first switching signal, the first input terminal is coupled to a data line for receiving a second analog signal corresponding to image charges of an image input element. The enable signal is deactivated between end points of the first and second active periods of the first switching signal.

Abstract: Tensile or compressive stress may be added in one or more selected locations to the biaxial residual stress existing in the channel of a semiconductor device, such as a MOSFET. The periphery of the active area containing the channel is modified by following layout procedures that result in forming outward protrusions of or inward depressions in the periphery of the active area and its surrounding shallow trench isolation during generally otherwise conventional fabrication of the device.

Abstract: A solid state imaging device includes a transparent insulation film. The insulation film is laminated on transfer electrodes over the power supply lines. A transparent protection film, which has a refractive index that is greater than that of the insulation film, is laminated on the insulation film. The transparent insulation film has portions above the channels in which the thickness continuously increases from the center of adjacent channels to the associated channel separating region.

Abstract: An in-plane switching mode active matrix type liquid crystal display device includes a first substrate, a second substrate located opposing the first substrate, and a liquid crystal layer sandwiched between the first and second substrates. The first substrate includes a thin film transistor, a pixel electrode, a common electrode, a data line, a scanning line, and a common electrode line. The scanning line and the common electrode line are formed in a common layer in parallel with each other. The common electrode overlaps the data line and the scanning line with an interlayer insulating film existing therebetween. The common electrode line is singly formed at either side about the scanning line. The common electrode is electrically connected to the common electrode line through a contact hole formed throughout the interlayer insulating film, and shields a gap formed between the scanning line and the common electrode line.

Abstract: An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is tied to the same potential of a substrate of the imager cell and is disposed between the photoreceptor and the sense node in order to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, and an output amplifier coupled to the sense node. Control circuitry supplies a photoreceptor readout clock to the photoreceptor. The readout clock includes an integration period and a transfer period. According to various embodiments of the invention, the imager cell provides improved noise performance, selective charge capacities, and improved blue light response beyond that of conventional imager cells.

Abstract: A solid state image pickup device includes: a semiconductor substrate defining light receiving areas; pixels formed in the light receiving areas, each pixel including a high and a low sensitivity photoelectric conversion element; a light shielding film formed above the light receiving areas and having an opening above each pixel, the opening exposing at least a partial area of the high and the low sensitivity photoelectric conversion element; an on-chip micro lens formed above each opening, the on-chip micro lens converging incidence light; and an inner lens formed between the light shielding film and the on-chip micro lens and above the opening, the inner lens being disposed so that the inner lens receives light converged by the on-chip micro lens, excluding a portion of the light, and further converges the received light to make the portion of the light propagate toward the opening without passing through the inner lens.

Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.

Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Abstract: An array of photodetectors intended to be hybridized on a readout circuit and fabricated from a wafer in semiconductor material. The wafer is divided into pixels, the pixels being separated from one another by walls formed crosswise over the entire thickness of the wafer, the hybridization surface having connection pads enabling hybridization of the photodetector array to the readout circuit.

Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

Abstract: A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor.

Abstract: A circuit and method are described which suppresses reset noise in active pixel sensor arrays. A circuit having a number of N? wells formed in a P? silicon epitaxial layer or a number of P? wells formed in an N? silicon epitaxial layer is provided. A pixel is formed in each of the wells so that each of the wells is surrounded by silicon of the opposite polarity and an array of pixels is formed. Means are provided for selectively combining or binning adjacent N? or P? wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated. The reset is accomplished using a PMOS transistor formed in each N? well or an NMOS transistor formed in each P? well. The selective binning is accomplished using NMOS or PMOS transistors formed in the region between adjacent wells.

Abstract: A camera module for a mobile device is reduced in size and manufacturing cost. A filter material made of a multi-layer thin film is bonded to a surface of a lens which is bonded to a surface of an image sensor chip. The filter material is a filter to block radiation within a predetermined range of wave length in an incident radiation to the lens, for example, an IR filter to block infrared radiation. An iris material made of a film such as an acrylic film or a polyolefin film is bonded to the lens covered with the filter material.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.

Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.

Abstract: A semiconductor device includes a plurality of photoelectric conversion photodiodes provided on a silicon substrate, and a refractive index matching film provided on each of the photodiodes. The refractive index matching film is composed of an insulating compound layer represented by SiOxNy (0≦x and y) assuming that the molar ratio of silicon, oxygen and nitrogen of the compound layer is 1:x:y. The oxygen content of the compound layer is the lowest at the silicon interface with each photodiode and the highest in an upper portion of the compound layer, and the nitrogen content is the highest at the silicon interface with each photodiode and the lowest in the upper portion of the compound layer. Therefore, multiple reflection can be decreased to improve light receiving sensitivity, as compared with a case in which a SiN single layer and a SiO2 single layer are laminated.

Abstract: A radiation shielded and packaged integrated circuit semiconductor device includes a lid secured to a base to enclose an integrated circuit die within, wherein the lid and the base are each constructed from a high Z material to prevent radiation from penetrating therethrough. Another embodiment includes a die attach slug constructed from a high Z material disposed between the integrated circuit die and the base, in combination with a high Z material lid to substantially block incident radiation.

Abstract: The invention provides an electro-optic device that includes a frame (i.e., frame-shaped pattern) disposed on a frame area in a TFT array substrate. The frame area is disposed between an image display area and a peripheral area. The frame is formed of the same film as capacitor electrodes, and is disposed at at least a part of the frame area. The frame is formed of the same film as wiring connected to an external circuit-connecting terminal. Accordingly, the electro-optic device can prevent the generation of an image caused by light leakage at the periphery of the image as much as possible, and thereby improve image quality.

Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.

Abstract: In the method, at least one layer-structured plane OLED component is formed on a plane substrate (10) with a method known per se, which component comprises a first electrode (20), an electrically conductive polymer (30), a light emitting material (50) and a second electrode (70), as well as intermediate and protective layers (40, 60, 80, 90) The plane OLED film comprising the substrate (10) and at least one OLED component is formed in a plastic forming process known per se by using vacuum, pressure, compression or a combination of these so that at least one OLED area ascended from the plane OLED component is formed on the plane OLED film. The OLED component comprises at least one OLED area ascended from the plane surface.

Abstract: An active matrix substrate for a liquid crystal display and method of forming the same. To form the active matrix substrate five masks are needed. The first mask forms gate lines on the transparent substrate. The second mask patterns a stacked layer of a metal layer/an n-doped layer/a semiconductor layer formed on a gate insulating layer to form data lines. After forming a low k dielectric layer, the third mask forms openings therein. The forth mask patterns pixel electrodes and conducting lines with source pattern on the low k dielectric layer and further patterns the metal layer and the n-doped layer. After depositing a passivating layer the fifth mask defines the passivating layer.

Abstract: An object of the present invention is to provide a large-size light-emitting device from which uniform light emission can be obtained.

Abstract: A module includes a component, a circuit board having the component mounted thereon, a first grounding pattern formed on an outermost periphery of a surface portion of the circuit board; a first sealer provided on the circuit board and having a dimension projected on the circuit board, and a metal film covering the sealer and connected to the grounding pattern. The dimension of the first dealer is smaller than an outside dimension of the circuit board. The first sealer is made of first resin and sealing the component. The module has a low profile and is adequately shielded.

Abstract: A method for increasing the bonding strength between a die and a housing for the die is described where a micro-electromechanical system (MEMS) device is formed on the die. The method includes depositing a plurality of contacts of bonding material between the substrate and die, and forming a bond between the die and the housing by applying at least 25,000 kilograms of force per gram of bonding material to the housing, the contacts, and the die.

Abstract: A semiconductor device of the present invention includes a semiconductor layer 10, an insulation gate type heavy insulated transistor 200 and an insulation gate type light insulated transistor 300 having different drain-source breakdown voltages and formed on the semiconductor layer 10, and a resistive impurity layer 24 formed on the semiconductor layer 10.

Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract: A Si/C superlattice useful for semiconductor devices comprises a plurality of epitaxially grown silicon layers alternating with carbon layers respectively adsorbed on surfaces of said silicon layers. Structures and devices comprising the superlattice and methods are described.

Abstract: A TFT is provided completely separated by an insulating film, in which a parasitic MOSFET is not generated at ends of a semiconductor layer, and the variation in characteristics is small. At least one portion of the ends in the gate-width direction of a gate electrode forming the TFT is disposed in a semiconductor region which forms the TFT, and the ends in the gate-length direction of the gate electrode extend toward the outside of the semiconductor region forming the TFT. With this arrangement, a uniform TFT in which a parasitic MOSFET is not generated at the ends in the gate-width direction is obtainable.

Abstract: A semiconductor detector of electromagnetic radiation which utilizes a dual-purpose electrode which extends significantly beyond the edge of a photodiode. This configuration reduces the sensitivity of device performance on small misalignments between manufacturing steps while reducing dark currents, kTC noise, and “ghost” images. The collection-mode potential of the dual-purpose electrode can be adjusted to achieve charge confinement and enhanced collection efficiency, reducing or eliminating the need for an additional pinning layer. Finally, the present invention enhances the fill factor of the photodiode by shielding the photon-created charge carriers formed in the substrate from the potential wells of the surrounding circuitry.

Abstract: A multiple layered wafer structure having, on a semiconductor substrate, a first dielectric layer, a single crystal semiconductor layer formed on the dielectric layer, a semiconductor nano-crystal layer formed on the single crystal semiconductor layer, and a second dielectric layer formed on the semiconductor nano-crystal layer. A laser is irradiated from the side of the second dielectric layer, to thereby separate the second dielectric layer from the others of the multiple layered wafer structure.

Abstract: A MEM tunneling gyroscope assembly includes (1) a beam structure, and a mating structure defined on a first substrate or wafer; and (2) at least one contact structure, and a mating structure defined on a second substrate or wafer, the mating structure on the second substrate or wafer being of a complementary shape to the mating structure on the first substrate or wafer; and (3) a bonding layer is disposed on at least one of said mating structures for bonding the mating structure defined on the first substrate or wafer to the mating structure on the second substrate or wafer.

Abstract: A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer back side laminate formed on a back side of a semiconductor die is disclosed. The coating element may be formed from a somewhat compressible and, optionally, resilient material, which seals against a surface of a mold cavity while the semiconductor die assembly is being encapsulated. In this manner, the coating element prevents encapsulant material from covering at least a portion of the back side of the semiconductor die to prevent encapsulant flashing over the back side and thus improve heat dissipation characteristics of the packaged semiconductor die during operation.

Abstract: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a region along the aperture; and an imaging element mounted on the surface of the base with wirings provided thereon so that a light-receptive region of the imaging element faces the aperture. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element.

Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a wavelength of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage Vth, and hence to enhance the reliability of the transfer or reset of electric charges.

Abstract: One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way. application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.

Abstract: A solid-state image pickup device includes: a plurality of light receiving portions arranged in a matrix, and a vertical transfer register which is four-phase driven by first, second, third and fourth transfer electrodes of a three-layer structure. The vertical transfer register is provided for each of columns of said light receiving portions. The first and third transfer electrodes of the first layer are alternately arranged in a charge transfer direction, and the adjacent two of the first and third transfer electrodes extend in parallel to each other between the light receiving portions. With this solid-state image pickup device, the accumulated charge capacity of each transfer region composed of the adjacent transfer electrodes for two-phases is equalized and the area of the light receiving portion is increased irrespective of variations in processed dimension between the transfer electrodes.

Abstract: A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that at of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors. The series-connected capacitors are coupled to the floating diffusion (FD) region for receiving “surplus” charge from the FD region during saturation conditions.

Abstract: An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is disposed to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, and an output amplifier coupled to the sense node. Control circuitry supplies a photoreceptor readout clock to the photoreceptor. The readout clock includes an integration period and a transfer period. During the integration period, the readout clock is at an integration voltage V+ which may be varied to setup a desired charge capacity in the photoreceptor. A thin gate structure or light aperture may be included to enhance blue light response of the photoreceptor. Thus, the imager cell provides improved noise performance, selective charge capacities, and improved blue light response beyond that of conventional imager cells.

Abstract: A solid state image sensor is constructed such that a plurality of linear image sensors are provided to have at least one row of photodiodes in each of the plurality of linear image sensors and a photodiode array is formed by arranging the plurality of linear image sensors side by side. A control gate electrode used to retrieve electric charges and a polysilicon electrode serving as a charge transfer electrode are provided between the pluraliielding conductive film is provided on the polysilicon electrode to partition the plurality of linear image sensors into individual linear image sensors. Accordingly, a light beam incident on a certain linear image sensor can be prevented from entering another linear image sensor adjacent to the certain linear image sensor, thereby reducing a difference between the amounts of signal charges outputted from different linear image sensors and suppressing smear.

Abstract: A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of a source follower transistor. The reset region is connected to one terminal of a capacitor which integrates collected charge of the photodiode. The charge collection region is reset by pulsing the other terminal of the capacitor from a higher to a lower voltage.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Abstract: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

Abstract: An amplifier circuit (R/A) conducts the first stage of ordering of whether to output data of four data bus pairs at the first half (first or second) or at the last half (third or fourth) based on the value of a signal EZORG1 reflecting the value of the least significant second bit of an externally applied column address. A switch circuit conducts the second stage of ordering to determine which is to be the first and the second of the two data output as the first half and to determine which is to be the third and the fourth of the two data output as the last half based on the value of a signal EZORG0 reflecting the value of the least significant bit in the externally applied column address.

Abstract: An image sensor and a fabricating method thereof are provided. The image sensor includes a floating diffusion region disposed at a predetermined region of a substrate, a photodiode region, and a source plug disposed on the floating diffusion region. Further, the sensor includes conductive patterns that may be used as gate electrodes of transistors. The conductive pattern and the source plug may have the same thickness and composition. Preferably, the source plug and the conductive pattern are made of polysilicon containing impurities. The fabricating method includes forming an insulating pattern on the semiconductor substrate having an opening exposing a predetermined region of the substrate, and forming a conductive pattern across the opening on the resultant structure. The conductive pattern may be made of polysilicon containing impurities.

Abstract: Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sensed spurious current. The spurious current could include photocurrent from a bright light, and the compensating current can prevent bright light effects.