With Specified Semiconductor Materials Patents (Class 257/22)
  • Patent number: 7122827
    Abstract: The present invention is directed toward a method for fabricating low-defect nanostructures of wide bandgap materials and to optoelectronic devices, such as light emitting sources and lasers, based on them. The invention utilizes nanolithographically-defined templates to form nanostructures of wide bandgap materials that are energetically unfavorable for dislocation formation. In particular, this invention provides a method for the fabrication of phosphor-less monolithic white light emitting diodes and laser diodes that can be used for general illumination and other applications.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: October 17, 2006
    Assignee: General Electric Company
    Inventors: Azar Alizadeh, Pradeep Sharma, Steven Francis LeBoeuf, Suryaprakash Ganti, Mark Philip D'Evelyn, Kenneth Roger Conway, Peter Micah Sandvik, Loucas Tsakalakos
  • Patent number: 7122813
    Abstract: A device for generating terahertz radiation. The device comprising a dipole generating layer, a coupling block and an extraction block. The coupling block is transparent to laser light and is in contact with the surface of the dipole generating layer to couple light from a laser to the surface of the dipole generating layer, when the device is in use. The extraction block is located in contact with the surface of the dipole generating layer to provide an emission extraction surface. The refractive indices of the dipole forming layer, the coupling block and the extraction block are substantially equal. In this way, the dipole which is generated upon illumination of the dipole generating layer by a laser, has an axis which is not perpendicular to the emission.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: October 17, 2006
    Assignee: Cambridge University Technical Services Limited
    Inventors: Edmund Harold Linfield, Michael Johnston, David Mark Whittaker
  • Patent number: 7118932
    Abstract: A method of manufacturing a waveguide type optical element wherein Zn is selectively diffused on a light absorption layer using an undoped InP layer. Since an impurity diffusion area is made on the light absorption layer under a ridge part, a depletion layer becomes thin in a thickness direction and an electric field can strongly be applied. Thereby, an extinction ratio characteristic of a device can be improved.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: October 10, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Koji Nakamura
  • Patent number: 7112830
    Abstract: The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: September 26, 2006
    Assignee: APA Enterprises, Inc.
    Inventor: Gordon Munns
  • Patent number: 7109517
    Abstract: Subwavelength random and periodic microscopic structures are used to enhance light absorption and tolerance for ionizing radiation damage of thin film and photodetectors. Diffractive front surface microscopic structures scatter light into oblique propagating higher diffraction orders that are effectively trapped within the volume of the photovoltaic material. For subwavelength periodic microscopic structures etched through the majority of the material, enhanced absorption is due to waveguide effect perpendicular to the surface thereof. Enhanced radiation tolerance of the structures of the present invention is due to closely spaced, vertical sidewall junctions that capture a majority of deeply generated electron-hole pairs before they are lost to recombination. The separation of these vertical sidewall junctions is much smaller than the minority carrier diffusion lengths even after radiation-induced degradation.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: September 19, 2006
    Inventor: Saleem H. Zaidi
  • Patent number: 7109529
    Abstract: A flip chip type of light-emitting semiconductor device using group III nitride compound includes a thick positive electrode. The positive electrode, which is made of at least one of silver (Ag), rhodium (Rh), ruthenium (Ru), platinum (Pt) and palladium (Pd), and an alloy including at least one of these metals, is adjacent to a p-type semiconductor layer, and reflect light toward a sapphire substrate. Accordingly, a positive electrode having a high reflectivity and a low contact resistance can be obtained. A first thin-film metal layer, which is made of cobalt (Co) and nickel (Ni), or any combinations of including at least one of these metals, formed between the p-type semiconductor layer and the thick electrode, can improve an adhesion between an contact layer and the thick positive electrode. A thickness of the first thin-film metal electrode should be preferably in the range of 2 ? to 200 ?, more preferably 5 ? to 50 ?. A second thin-film metal layer made of gold (Au) can further improve the adhesion.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: September 19, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Shigemi Horiuchi
  • Patent number: 7099362
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a substrate; a first mirror stack over the substrate; an active region having a plurality of quantum wells over the first mirror stack; a tunnel junction over the active region, the tunnel junction including a modulation-doped layer; and a second mirror stack over the tunnel junction. The modulation doped layer can be used for either the n-layer or the p-layer, or the both layers of the tunnel junction. Such tunnel junctions are especially useful for a long wavelength VCSEL.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: August 29, 2006
    Assignee: Finisar Corporation
    Inventor: Jin K. Kim
  • Patent number: 7098487
    Abstract: There is provided a GaN single crystal at least about 2 millimeters in diameter, with a dislocation density less than about 104 cm?1, and having no tilt boundaries. A method of forming a GaN single crystal is also disclosed. The method includes providing a nucleation center, a GaN source material, and a GaN solvent in a chamber. The chamber is pressurized. First and second temperature distributions are generated in the chamber such that the solvent is supersaturated in the nucleation region of the chamber. The first and second temperature distributions have different temperature gradients within the chamber.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: August 29, 2006
    Assignee: General Electric Company
    Inventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven LeBoeuf, Larry Rowland, Kristi Narang, Huicong Hong, Peter M. Sandvik
  • Patent number: 7098471
    Abstract: Semiconductor quantum well devices and methods of making the same are described. In one aspect, a device includes a quantum well structure that includes semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells. Each of the quantum wells includes a quantum well layer interposed between barrier layers. One of the semiconductor layers that functions as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells. Another of the semiconductor layers that functions as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 29, 2006
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: Tirumala R. Ranganath, Jintian Zhu
  • Patent number: 7087923
    Abstract: A photon source comprising a quantum dot layer having a plurality of quantum dots with an n-modal distribution in emission wavelength, said n-modal distribution in emission wavelength comprising n peaks in a plot of dot density as a function of emission wavelength where n is an integer of at least 2, the photon source further comprising isolating means for isolating the emission from a predetermined number of quantum dots.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Martin Brian Ward, Andrew James Shields
  • Patent number: 7087924
    Abstract: Disclosed is a multi-quantum-well light emitting diode, which makes enormous adjustments and improvements over the conventional light emitting diode, and further utilizes a transparent contact layer of better transmittance efficiency, so as to significantly raise the illuminance of this light emitting diode and its light emission efficiency. The multi-quantum-well light emitting diode has a structure including: substrate, buffer layer, n-type gallium-nitride layer, active light-emitting-layer, p-type cladding layer, p-type contact layer, barrier buffer layer, transparent contact layer, and the n-type electrode layer.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: August 8, 2006
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Liang-Wen Wu, Ru-Chin Tu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien
  • Patent number: 7077982
    Abstract: A molecular electric wire that is formed of an environmentally benign ecological material and enables a microscopic wiring, a molecular electric wire circuit using the molecular electric wire, and the like are provided. The molecular electric wire comprises a rod-shaped organic molecule and an electroconductive material, the electroconductive material being carried by the rod-shaped organic molecule, and the molecular electric wire circuit is formed by using the molecular electric wire.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: July 18, 2006
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Takatoshi Kinoshita, Shintaro Washizu
  • Patent number: 7071492
    Abstract: A polymer well may be formed over a thermal oxide formed over a semiconductor substrate in one embodiment. The well may include a waveguide and a pair of heaters adjacent the waveguide. Each heater may be mounted on a platform of insulating material to reduce heat loss through the substrate and the thermal oxide, in one embodiment.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Ruolin Li, Ut Tran
  • Patent number: 7061020
    Abstract: An array substrate for a liquid crystal display device includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; source and drain electrodes on the semiconductor layer, the source and drain electrodes including a copper layer as an upper layer and a barrier layer as a lower layer; a first passivation layer on the source and drain electrodes; a second passivation layer on the first passivation layer, the second passivation layer having a drain contact hole through the first passivation layer, the drain contact hole exposing the barrier layer; and a pixel electrode connected to the barrier layer through the drain contact hole.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: June 13, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Gee Sung Chae
  • Patent number: 7061014
    Abstract: Disclosed is a natural-superlattice homologous single-crystal thin film, which includes a complex oxide which is epitaxially grown on either one of a ZnO epitaxial thin film formed on a single-crystal substrate, the single-crystal substrate after disappearance of the ZnO epitaxial thin film and a ZnO single crystal. The complex oxide is expressed by the formula: M1M2O3 (ZnO)m, wherein M1 is at least one selected from the group consisting of Ga, Fe, Sc, In, Lu, Yb, Tm, Er, Ho and Y, M2 is at least one selected from the group consisting of Mn, Fe, Ga, In and Al, and m is a natural number of 1 or more. A natural-superlattice homologous single-crystal thin film formed by depositing the complex oxide and subjecting the obtained layered film to a thermal anneal treatment can be used in optimal devices, electronic devices and X-ray optical devices.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: June 13, 2006
    Assignee: Japan Science and Technology Agency
    Inventors: Hideo Hosono, Hiromichi Ota, Masahiro Orita, Kazushige Ueda, Masahiro Hirano, Toshio Kamiya
  • Patent number: 7049641
    Abstract: The invention relates to the design, fabrication, and use of semiconductor devices that employ deep-level transitions (i.e., deep-level-to-conduction-band, deep-level-to-valence-band, or deep-level-to-deep-level) to achieve useful results. A principal aspect of the invention involves devices in which electrical transport occurs through a band of deep-level states and just the conduction band (or through a deep-level band and just the valence band), but where significant current does not flow through all three bands. This means that the deep-state is not acting as a nonradiative trap, but rather as an energy band through which transport takes place. Advantageously, the deep-level energy-band may facilitate a radiative transition, acting as either the upper or lower state of an optical transition.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: May 23, 2006
    Assignee: Yale University
    Inventor: Janet L. Pan
  • Patent number: 7045871
    Abstract: Since a ZnTe-base compound semiconductor crystal was designed so as to have, on a ZnTe-base compound semiconductor layer, an n-type contact layer which includes a superlattice layer having n-type CdSe and n-type ZnTe grown with each other or a ZnCdSeTe-graded layer, it was made possible to raise carrier concentration of the n-type contact layer, and to control the conductivity type in a relatively easy manner. Moreover, formation of a CdSe/ZnTe superlattice layer or a ZnCdSeTe-graded layer between the contact layer and an electrode can prevent electric resistance from being increased due to difference in the energy gaps. Since CdSe and ZnTe, composing the CdSe/ZnTe superlattice or ZnCdSeTe composition-graded layer, have relatively close lattice constants, formation thereof is less likely to adversely affect the crystallinity of the semiconductor crystal, which is advantageous in obtaining the semiconductor crystal with an excellent quality.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 16, 2006
    Assignees: Nikko Materials Co., Ltd.
    Inventors: Katsumi Kishino, Ichiro Nomura, Song-Bek Che, Kenji Sato
  • Patent number: 7038234
    Abstract: A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon germanium. The p-legs includes alternating layers of B4C and B9C. In preferred embodiments the layers are about 100 angstroms thick. Applicants have fabricated and tested a first Si/SiGe (n-leg) and B4C/B9C (p-leg) quantum well thermocouple. Each leg was only 11 microns thick on a 5 micron Si substrate. Nevertheless, in actual tests the thermocouple operated with an amazing efficiency of 14 percent with a Th of 250 degrees C. Thermoelectric modules made according to the present invention are useful for both cooling applications as well as electric power generation. This preferred embodiment is a thermoelectric 10×10 egg crate type module about 6 cm×6 cm×0.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: May 2, 2006
    Assignee: Hi-Z Technology, Inc.
    Inventors: Saeid Ghamaty, Norbert B. Elsner, John C. Bass
  • Patent number: 7038233
    Abstract: An InGaAlAs-based buried type laser is expected to improve properties of the device, but generates defects at a re-growth interface and is difficult to realize a long-term reliability necessary for optical communication, due to inclusion of Al in an active layer. A semiconductor optical device and an optical module including a package substrate and a semiconductor optical device mounted on the package substrate are provided, whereby there are realized the improvement of device properties and the long-term reliability through the use of an Al composition ratio-reduced tensile strained quantum well layer.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: May 2, 2006
    Assignees: Hitachi, Ltd., Opnext Japan, Inc.
    Inventors: Tomonobu Tsuchiya, Tsukuru Ohtoshi
  • Patent number: 7034330
    Abstract: A Group-III nitride semiconductor device including a crystal substrate, an electrically conducting Group-III nitride semiconductor (AlXGaYIn1?(X+Y)N: 0?X<1, 0<Y?1 and 0<X+Y?1) crystal layer vapor-phase grown on the crystal substrate, an ohmic electrode and an electrically conducting boron phosphide crystal layer provided between the ohmic electrode and the Group-III nitride semiconductor crystal layer, the ohmic electrode being disposed in contact with the boron phosphide crystal layer. Also disclosed is a method for producing the Group-III nitride semiconductor device, and a light-emitting diode including the Group-III nitride semiconductor device.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: April 25, 2006
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Patent number: 7034328
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: April 25, 2006
    Assignee: Cree, Inc.
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.
  • Patent number: 7026642
    Abstract: The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis through the channel, the quantum dot and the gate is substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 7023010
    Abstract: A Si/C superlattice useful for semiconductor devices comprises a plurality of epitaxially grown silicon layers alternating with carbon layers respectively adsorbed on surfaces of said silicon layers. Structures and devices comprising the superlattice and methods are described.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: April 4, 2006
    Assignee: Nanodynamics, Inc.
    Inventors: Chia Gee Wang, Raphael Tsu
  • Patent number: 7023011
    Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: April 4, 2006
    Assignee: Translucent, Inc.
    Inventors: Petar B. Atanackovic, Larry R. Marshall
  • Patent number: 7019325
    Abstract: The invention concerns a superluminescent light emitting diode (SLED) comprising a semiconductor heterostructure forming a PN junction and a waveguide. The semiconductor heterostructure includes a gain region with a contact means for biasing the PN junction so as to produce light emission including stimulated emission from an active zone of the gain region, and in the active zone a plurality of quantum dot layers, each quantum dot layer made up of a plurality of quantum dots and a plurality of adjoining layers, each adjoining layer adjacent to one of said quantum dot layers. The material composition or a deposition parameter of at least two adjoining layers is different. This ensures an enhanced emission spectral width.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: March 28, 2006
    Assignee: Exalos AG
    Inventors: Lianhe Li, Andrea Fiore, Lorenzo Occhi, Christian Velez
  • Patent number: 7005667
    Abstract: A broad-spectrum Al(1-x-y)InyGaxN light emitting diode (LED), including: a substrate, a buffer layer, an N-type cladding layer, at least one quantum dot emitting layer, and a P-type cladding layer. The buffer layer is disposed over the substrate. The N-type cladding layer is disposed over the buffer layer to supply electrons. The quantum dot emitting layer is disposed over the N-type cladding layer and includes plural quantum dots. The dimensions and indium content of the quantum dots are manipulated to result in uneven distribution of character distribution of the quantum dots so as to increase the FWHM of the emission wavelength of the quantum dot emitting layer. The P-type cladding layer is disposed over the quantum dot emitting layer to supply holes. A broad-spectrum Al(1-x-y)InyGaxN yellow LED may thus be made from the LED structure of this invention, with an emission wavelength at maximum luminous intensity falling within a range of 530˜600 nm, and FWHM within a range of 20˜150 nm.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: February 28, 2006
    Assignee: Genesis Photonics, Inc.
    Inventors: Cheng Chuan Chen, Ming Chang Chen
  • Patent number: 6998690
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: February 14, 2006
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 6992325
    Abstract: An active matrix organic electroluminescence display device capable of maintaining the brightness of the organic light emitting diode. The active matrix organic electroluminescence display device comprises a thin film transistor and an organic light emitting diode. By improving the structure of the passivation layer of the thin film transistor to reduce the leakage current occurring in the TFT, the brightness of the organic light emitting diode can be stably maintained.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: January 31, 2006
    Assignee: Au Optronics Corp.
    Inventor: Wei-Pang Huang
  • Patent number: 6979835
    Abstract: An epitaxial structure for the GaN-based LED is provided. The GaN-based LED uses a substrate usually made of sapphire or silicon-carbide (SiC). On top of the substrate, the GaN-based LED contains an n-type contact layer made of an n-type GaN-based material. On top of the n-type contact layer, the GaN-based LED further contains a lower barrier layer covering part of the surface of the n-type contact layer. A negative electrode is also on top of and has an ohmic contact with the n-type contact layer in an area not covered by the lower barrier layer. On top of the lower barrier layer, the GaN-based LED then further contains an active layer made of aluminum-gallium-indium-nitride, an upper barrier layer, a p-type contact layer made of a magnesium (Mg)-doped GaN material, and a positive electrode having an ohmic contact with the p-type contact layer, sequentially stacked in this order from bottom to top.
    Type: Grant
    Filed: September 11, 2004
    Date of Patent: December 27, 2005
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Cheng-Tsang Yu, Ru-Chin Tu, Liang-Wen Wu, Tzu-Chi Wen, Fen-Ren Chien
  • Patent number: 6980748
    Abstract: A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventor: James M. Leas
  • Patent number: 6967346
    Abstract: A light emitting diode (LED) structure and manufacture method thereof are disclosed, wherein a buffer layer is grown on a substrate and then an LED structural layer is grown on the buffer layer. The LED structural layer comprises a p-type quantum-dot epitaxial layer on a p-type GaN layer. As the p-type quantum-dot epitaxial layer has a coarsening and scattering effect the path of light emitted from an INGaN multiple-quantum-well structural layer is changed. Therefore, it is possible to decrease the probability of total reflection and thereby increase the light-emitting efficiency of LED.
    Type: Grant
    Filed: August 2, 2003
    Date of Patent: November 22, 2005
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Fen-Ren Chien, Lung-Chien Chen
  • Patent number: 6952018
    Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: October 4, 2005
    Assignee: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Patent number: 6946372
    Abstract: A method of manufacturing a gallium nitride (GaN)-based semiconductor light emitting device includes forming a contact resistance improved layer on a p-type GaN-based semiconductor layer with at least one metal selected from the group of Au, Mg, Mn, Mo, Pd, Pt, Sn, Ti and Zn, heat-treating the p-type GaN-based semiconductor layer so that elements in the contact resistance improved layer diffuse into the p-type GaN-based semiconductor layer and that Ga elements in the p-type GaN-based semiconductor layer dissolve into the contact resistance improved layer, and removing the contact resistance improved layer remaining on the p-type GaN-based semiconductor layer.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: September 20, 2005
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Hyun Kyung Kim
  • Patent number: 6946318
    Abstract: A photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate efficiently in the C-band and L-band.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: September 20, 2005
    Assignee: Massachusetts Institute of Technology
    Inventors: Kazumi Wada, Lionel C. Kimerling, Yasuhiko Ishikawa, Douglas D. Cannon, Jifeng Liu
  • Patent number: 6936869
    Abstract: Semiconductor devices, e.g., heterojunction field effect transistors, fabricated with silicon-germnanium buffer layer and silicon-carbon channel layer structures. The invention provides a method of reducing threading defect density via reducing germanium content in a SiGe relaxed buffer layer on which a strained silicon channel layer is formed, by forming the strained silicon channel layer of a silicon-carbon alloy, e.g., containing less than about 1.5 atomic % C substitutionally incorporated in the Si lattice of the alloy.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: August 30, 2005
    Assignee: International Rectifier Corporation
    Inventors: Douglas A. Webb, Michael G. Ward
  • Patent number: 6933519
    Abstract: The present invention relates to a II-VI compound semiconductor crystal comprising an n-type contact layer which includes a superlattice layer comprising n-type CdSe and n-type ZnTe stacked with each other, on a ZnTe-base compound semiconductor layer; a A II-VI compound semiconductor crystal comprising an n-type contact layer which includes an n-type ZnCdSeTe composition-graded layer in which composition of Zn, Cd, Se and Te is gradually varies, on a ZnTe-base compound semiconductor layer; a II-VI compound semiconductor crystal comprising a p-type contact layer which includes a superlattice layer comprising p-type CdSe and p-type ZnTe stacked with each other, on a CdSe-base compound semiconductor layer; and a II-VI compound semiconductor crystal comprising a p-type contact layer which includes a p-type ZnCdSeTe composition-graded layer in which composition of Zn, Cd, Se and Te is gradually varied, on a CdSe-base compound semiconductor layer.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: August 23, 2005
    Assignees: Nikko Materials Co., Ltd.
    Inventors: Katsumi Kishino, Ichiro Nomura, Song-Bek Che, Kenji Sato
  • Patent number: 6924528
    Abstract: In a bottom gate type semiconductor device made of a semiconductor layer with crystal structure, source/drain regions are constructed by a lamination layer structure including a first conductive layer (n+ layer), a second conductive layer (n? layer) having resistance higher than the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i layer). At this time, the n? layer acts as LDD region, and the i layer acts as an offset region is a film thickness direction.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: August 2, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Takeshi Fukunaga
  • Patent number: 6906358
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. At least one extraction region is disposed on a first side of the active region and has a majority carrier of the second conductivity type. Carriers of the second conductivity type are extracted from the active region and into the extraction region under a condition of reverse bias. At least one exclusion region is disposed on a second side of the active region and has a majority carrier of the first conductivity type. The exclusion region prevents entry of its minority carriers, which are of the second conductivity type, into the active region while in a condition of reverse bias. The exclusion region includes a superlattice with a plurality of layers.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 14, 2005
    Assignee: EPIR Technologies, Inc.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Patent number: 6903364
    Abstract: Group III-nitride quaternary and pentenary material systems and methods are disclosed for use in semiconductor structures, including laser diodes, transistors, and photodetectors, which reduce or eliminate phase separation and provide increased emission efficiency. In an exemplary embodiment the semiconductor structure includes a first ternary, quaternary or pentenary material layer using BlnGaAlN material system of a first conduction type formed substantially without phase separation, and a quaternary or pentenary material active layer using BlnGaAlN material system substantially without phase separation, and a third ternary, quaternary or pentenary material layer using BlnGaAlN material system of an opposite conduction type formed substantially without phase separation.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toru Takayama, Takaaki Baba, James S. Harris, Jr.
  • Patent number: 6897470
    Abstract: Supermolecular structures and devices made from same. Semiconductor materials and devices are manufactured and provided which use controlled, discrete distribution of and positioning of single impurity atoms or molecules within a host matrix to take advantage of single charge effects. Single-dopant pn junctions and single-dopant bipolar cells are created. Each bipolar cell can function as a bistable device or an oscillator, depending on operating temperature. The cells can be used alone or in an array to make useful devices by adding an insulating substrate and contact electrodes.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 24, 2005
    Assignees: Semiconductor Research Corporation, North Carolina State University
    Inventors: Daniel Joseph Christian Herr, Victor Vladimirovich Zhirnov
  • Patent number: 6898340
    Abstract: A semiconductor light-emitting element 10 includes a silicon single crystal substrate 20 having a first and a second surfaces 20a, 20b in head-tail relationship with each other, a GaN-based semiconductor laminate 40 formed on a selected region of the first surface with a predetermined conductive intermediate layer 25 interposed therebetween, a first electrode layer 51 having a portion in contact with an uppermost layer of the GaN-based semiconductor laminate 40 and insulated from the monocrystal silicon substrate, and a second electrode layer 52 formed on a suitable portion of the monocrystal silicon substrate. The monocrystal silicon substrate 20 is formed with a light guide 30 for directing light emitted from the GaN-based semiconductor laminate 40 toward the second surface 20b.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: May 24, 2005
    Assignee: Rohm Co., Ltd.
    Inventor: Haruo Tanaka
  • Patent number: 6897471
    Abstract: This invention teaches two new families of Si-based Ge/SnxGe1-x heterodiode and multiple quantum well (MQW) photonic devices: (1) band-to-band photodetectors, lasers, emitters, amplifiers and modulators for the 1.5 to 12 ?m wavelength range; (2) intersubband photodetectors, lasers, emitters and modulators for 12 to 100 ?m operation. The bipolar band-to-band devices have applications within the 1.5-2.2, 3-5 and 8-to-12 ?m bands. The unipolar intersubband group has longwave infrared and terahertz applications. All strained-layer devices are grown a relaxed SnySizGe1-y-z buffer layer—a virtual substrate (VS) grown directly upon a silicon wafer by unique LT UHV-CVD. The VS provides a low-defect atomic template for subsequent heteroepitaxy and is an essential enabling technique for engineering tensile and compressive strain within the Ge/SnxGe1-x MQW by selecting the VS lattice parameter to be approx midway between the layer lattices.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: May 24, 2005
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Richard A. Soref, Jose Menendez, John Kouvetakis
  • Patent number: 6891189
    Abstract: A nitride semiconductor laser device includes a nitride semiconductor substrate, and a layered portion corresponding to a nitride semiconductor film grown on the nitride semiconductor substrate, the layered portion including an n-type layer and a p-type layer and a light emitting layer posed between the n- and p-type layers, of the n- and p-type layers a layer opposite to the nitride semiconductor substrate with the light emitting layer opposed therebetween serving as an upper layer having a stripe of 1.9 ?m to 3.0 ?n in width, the light emitting layer and the upper layer having an interface distant from a bottom of the stripe by 0 ?m to 0.2 ?m.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: May 10, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigetoshi Ito, Yuhzoh Tsuda
  • Patent number: 6891187
    Abstract: A quantum well structure is provided that includes two or more quantum well layers coupled by at least one barrier layer such that at least one of a piezo-electric field and a pyro-electric field is produced. The quantum well structure is sufficiently doped to cause a Fermi energy to be located between ground states and excited states of the coupled quantum well layers. The quantum well structure can be incorporated into a layered semiconductor to form optical devices such as a laser or optical amplifier.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: May 10, 2005
    Assignee: Lucent Technologies Inc.
    Inventors: Alfred Yi Cho, Claire F. Gmachl, Hock Min Ng
  • Patent number: 6890809
    Abstract: A method for fabricating a p-n heterojunction device is provided, the device being preferably comprised of an n-type GaN layer co-doped with silicon and zinc and a p-type AlGaN layer. The device may also include a p-type GaN capping layer. The device can be grown on any of a variety of different base substrates, the base substrate comprised of either a single substrate or a single substrate and an intermediary layer. The device can be grown directly onto the surface of the substrate without the inclusion of a low temperature buffer layer.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: May 10, 2005
    Assignee: Technologies and Deviles International, Inc.
    Inventors: Sergey Karpov, Alexander Usikov, Heikki I. Helava, Denis Tsvetkov, Vladimir A. Dmitriev
  • Patent number: 6888179
    Abstract: GaAs substrates with compositionally graded buffer layers for matching lattice constants with high-Indium semiconductor materials such as quantum well infrared photoconductor devices and thermo photo voltaic devices are disclosed.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: May 3, 2005
    Assignee: Bae Systems Information and Electronic Systems Integration INC
    Inventor: Parvez N. Uppal
  • Patent number: 6872965
    Abstract: An undercoat layer inclusive of a metal nitride layer is formed on a substrate. Group III nitride compound semiconductor layers are formed on the undercoat layer continuously.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: March 29, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Jun Ito, Toshiaki Chiyo, Naoki Shibata, Hiroshi Watanabe, Shizuyo Asami, Shinya Asami
  • Patent number: 6870235
    Abstract: A Semiconductor sensor device for the detection of target molecules and molecular interactions, based on Silicon-on-Insulator (SOI) technology.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: March 22, 2005
    Assignee: Fujitsu Limited
    Inventors: Gerhard Abstreiter, Marc Uwe Tornow, Karin Buchholz, Sebastian Markus Luber, Erich Sackmann, Andreas Richard Bausch, Michael Gerold Hellmut Nikolaides, Stefan Rauschenbach
  • Patent number: 6864512
    Abstract: A semiconductor waveguide is disclosed which includes a substrate coated with a cladding. A core is embedded in the cladding. The core includes a plurality of discreet stacked layers of core material surrounded by cladding material. The cladding and core layers each include silica and silicon nitride with the core layers having a higher nitrogen content than the cladding material. The core is fabricated by carefully manipulating the process parameters of a PECVD process.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: March 8, 2005
    Assignee: Intel Corporation
    Inventor: Kjetil Johannessen
  • Patent number: 6864511
    Abstract: An optical transmission module with an optical device mounted in a substrate provided with an optical waveguide is provided wherein respective metallic electrodes in pair are symmetrically disposed in each side of an optical device divided by a centerline parallel to an optical axis such that those electrodes have an error of 60 ?m or less and said metallic electrodes are soldered to a metallic electrode as disposed on a substrate, which electrode has a size enough to cover those electrodes as disposed in the optical device.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: March 8, 2005
    Assignee: OpNext Japan, Inc.
    Inventors: Yoshio Oozeki, Kazumi Kawamoto, Seiichi Tsuchida