Abstract: A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.

Abstract: A high frequency semiconductor device including a high frequency semiconductor chip, comprising an active region provided on a front face side of the high frequency semiconductor chip; a covering electrode provided on the active region and connected to a ground potential; and a back face wiring provided on a back face side of the high frequency semiconductor chip. The back face wiring forms a high frequency transmission line together with the covering electrode functioning as a high frequency ground plate. A front face wiring may be provided on the front face side of the high frequency semiconductor chip to form a high frequency transmission line together with the covering electrode.

Abstract: Since a 5 GHz-band broadband has a frequency twice that of 2.4 GHz, the parasitic capacitance greatly influences deterioration in isolation of a switching device used in this frequency region. Therefore, to improve isolation, a shunt FET is added to the device. The switching device also includes a protecting element that has a first n+-type region, an insulating region and a second n+-type region. This protecting element is connected in parallel between two electrodes of the shunt FET. Since electrostatic charges are discharged between the first and second n+-type regions, the electrostatic energy reaching an operation region of the shunt FET can be reduced without an increase in parasitic capacitance.

Abstract: A high-frequency semiconductor device for power amplification has a comb-teeth electrode on each of active regions formed on the front surface of the semiconductor substrate. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a plurality of rectangular-shaped active regions arranged side by side on the front surface of the semiconductor substrate, each of the active regions having interdigited gate, drain and source electrodes thereon which are connected to the respective pads by multilayer interconnection technique. Additionally, the source potential is fed from the back surface of the substrate through a metal plugged via-hole.

Abstract: A multilayer semiconductor device includes at least one structure for transmitting electrical signals, and in particular, microwave signals. The device includes at least one electrically conductive enclosure that includes a bottom plate and a top plate in two different layers. Lateral walls connect the bottom and top plates. Electrically conductive connecting strips extend into the enclosure and are in an intermediate layer, and are electrically insulated from the enclosure. The enclosure has at least one passage through which extends electrical connections of the connecting strips, which are also electrically insulated from the enclosure.

Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Abstract: A high frequency switch, has a transmitting terminal; a receiving terminal; an antenna terminal; a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal; a second diode having an anode connected through a transmission line of ¼ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded; and a control terminal provided to a node between the transmitting terminal and the first anode, wherein the first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.

Abstract: A FET or BJT structure or distributed transistor amplifier having a tapered gate feed line and a tapered channel width (tapered source fingers, tapered drain fingers) provides increased bandwidth and gain in the microwave/mm-wave frequency spectrum.

Abstract: A phased-array antenna system and other types of radio frequency (RF) devices and systems using microelectromechanical switches (“MEMS”) and low-temperature co-fired ceramic (“LTCC”) technology and a method of fabricating such phased-array antenna system and other types of radio frequency (RF) devices are disclosed. Each antenna or other type of device includes at least two multilayer ceramic modules and a MEMS device fabricated on one of the modules. Once fabrication of the MEMS device is completed, the two ceramic modules are bonded together, hermetically sealing the MEMS device, as well as allowing electrical connections between all device layers. The bottom ceramic module has also cavities at the backside for mounting integrated circuits. The internal layers are formed using conducting, resistive and high-k dielectric pastes available in standard LTCC fabrication and low-loss dielectric LTCC tape materials.

Abstract: A method is presented in which an active element, e.g. a semiconductor device, is embedded in a passive circuitry formed on a low-cost substrate, having good dielectric properties. After forming the active element on a first substrate, the active elements are singulated and transferred to a second substrate. The active element is bonded to this second substrate and the portion of the first substrate, on which this active element is created, is removed selectively to the active element and the low-cost substrate. On this second substrate passive circuitry may be present or it can be formed after the attachment of the active element. The passive circuitry is interconnected to the active element or other components or dies present on the low-cost substrate.

Abstract: An asymmetric double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a first fin formed on a substrate; a second fin formed on the substrate; a first gate formed adjacent first sides of the first and second fins, the first gate being doped with a first type of impurity; and a second gate formed between second sides of the first and second fins, the second gate being doped with a second type of impurity. An asymmetric all-around gate MOSFET includes multiple fins; a first gate structure doped with a first type of impurity and formed adjacent a first side of one of the fins; a second gate structure doped with the first type of impurity and formed adjacent a first side of another one of the fins; a third gate structure doped with a second type of impurity and formed between two of the fins; and a fourth gate structure formed at least partially beneath one or more of the fins.

Abstract: A small area cascode FET structure capable of operating at mm-wave frequenices cascades a common-source (CS) FET with a common gate (CG) FET, in a smaller physical area than conventional cascode FET structures. The small area of the cascode FET structure is partially achieved by using small source via grounds, requiring a thin gallium arsenide substrate (typically between 50 and 70 microns thick). The overall cascode area is reduced further, by having the two FETs share a common node. This common node is the output drain manifold of the CS FET, which is also an input source finger of the CG FET. In addition, small via grounds within the MIM capacitors and CS FET, which provide the ground connection to the gate manifolds of the CG FET, further reduce circuit area. Advantageously, the small area cascode FET can be applied to many different MMICs to reduce MMIC area requirements and cost.

Abstract: An electronic package component includes a flip-chip device mounted to a BGA substrate. The BGA substrate includes conductive traces formed on its upper surface and configured in a coplanar waveguide structure. The package includes a dielectric coating applied over the conductive traces and over the upper surface of the substrate. The coating is formed from a material having a dielectric constant that is equal to or approximately equal to the dielectric constant of the BGA substrate material. The dielectric coating reduces the adverse effects caused by phase velocity dispersion of the signal propagated by the coplanar waveguide.

Abstract: A filter has suspended metal structures which are surrounded by a metal shield on all sides, except at the input and output ports. The shape of the metal determines the type of filter. The signal can be coupled into and out of the filter either by coplanar waveguide ports, stripline ports, or through a waveguide connection. The metals making up the filters are suspended, and only come into contact with air or with an extremely thin dielectric. This minimizes both dielectric losses and ohmic losses in the metal, and allows filters to be made without separately mounted dielectric resonators. The low losses allows, in the cause of a bandpass filter, high Q resonators to be achieved, thus providing a high quality filter with low insertion loss in the passband.

Abstract: The electronic circuit unit of the present invention includes first and second insulating substrates on respective surfaces of which wiring patterns are formed, and thick-film passive elements formed on the surfaces of the first and second insulating substrates in a state in which they are connected to the wiring patterns, wherein the first and second insulating substrates are disposed vertically opposite to each other, and the wiring patterns provided on the first and second insulating substrates are connected through metallic bumps provided between the first and second insulating substrates.

Abstract: A contact-less high-speed signaling interface and method provide for the communication of high-speed signals across an interface, such as a die-substrate interface or die-die interface. The interface includes a transmission-line structure disposed on a dielectric medium to carry a high-speed forward incident signal, and another transmission-line structure disposed on another dielectric medium and substantially aligned with the other transmission-line structure to generate a coupled high-speed signal in a direction opposite to the incident signal.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.

Abstract: A field-effect transistor device includes an active area on a semiconductor substrate and a gate electrode, a source electrode, and a drain electrode are disposed on the surface of the active area, so as to define an FET portion. An electrode defining a line for connection to the gate, an electrode defining a line for connection to the source, and an electrode defining a line for connection to the drain are disposed on the semiconductor substrate. The electrodes define a slot line on the input side for supplying a signal to the FET portion, and a slot line on the output side from which a signal of the FET portion is output. The gate electrode has a shape which extends along the direction that approximately perpendicular to the conduction direction of the signal through the slot line on the input side.

Abstract: An integrated semiconductor circuit including a substrate and at least one microwave circuit area supported by a substrate is provided, at least one cooling area supported by the substrate being provided for cooling the microwave circuit area, the at least one cooling area having electric contacts and regions having different types of doping so that cooling may be accomplished by the Peltier effect.

Abstract: An inexpensive and small-sized semiconductor device with high power output performance includes a semiconductor substrate; an active region on the semiconductor substrate; first and second channel regions on the active region so that width directions of the first and second channel regions are substantially perpendicular to each other, bent gate electrodes on the first and second channel regions; and source electrodes and drain electrodes on opposite sides of the bent gate electrodes.

Abstract: The invention relates to an LDMOS transistor including a gate, source and drain, and an earth plane located under the gate, source and drain. According to the invention, the earth plane is given such an extent in the lateral direction of the transistor that an additional component of chip type can be mounted on it, whereby the LDMOS transistor and the additional component of chip type have a shared earth plane. The earth plane suitably comprises a silicon layer which is doped so that it has become conductive and can thereby constitute the earth plane for the transistor and the additional component of chip type.

Abstract: The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends.

Abstract: An isolation structure for high frequency integrated circuits is a conductive material disposed over a region of active gallium arsenide substrate. The conductive material over the active region creates a lossy RF path to reduce undesired coupling between adjacent conductors. In one case, two RF signal lines (1,2) terminated at the same via pad (3) have weaker coupling than in prior art via structures due to the lossy RF structure disposed on isolating fractional portions (10,11) of the via pad (3). The isolating fractional portion (10,11) are intermediate terminating fractional portions (8,9) of the via pad (3) to which the signal lines (1,2) are connected. In another case, two parallel bias lines (12,13) are disposed over an active layer region (6) increasing the RF loss between them and advantageously reducing the RF coupling. The reduced RF coupling improves RF isolation and permits increased miniaturization.

Abstract: A ferrite magnetic film structure exhibiting a magnetic anisotropy, the ferrite magnetic film structure comprising, a substrate provided on one main surface thereof with a groove-like recessed portion and with a ridge-like projected portion located neighboring to the groove-like recessed portion, and a ferrite magnetic film constituted by a continuous film having a substantially flat upper surface and formed on one main surface of the substrate, wherein the ferrite magnetic film structure meets the following conditions: (a/(a+b))(h/(t−h))≧0.047 1≧(a+b) where “a” is a width of the ridge-like projected portion, b is a width of the groove-like recessed portion, h is a height of step between the groove-like recessed portion and the ridge-like projected portion, t is a thickness of the ferrite magnetic film at the recessed portion, and 1 is a length of the recessed portion and of the projected portion.

Abstract: To eliminate variations in measurement of the chip characteristics an MMIC chip has a pad main portion having the same width as a main line at an end of the main line The main line is located on a GaAs substrate. Pad auxiliary islands are adjacent to the pad main portion on one or both sides. A grounding wiring layer is on at least one side of the pad main portion with the pad auxiliary island interposed in between. The pad main portion and the pad auxiliary portions secure a sufficient bonding area. The electrical characteristics are measured by bringing probes into contact with the pad main portion and the grounding wiring layer(s). The electrical characteristics of the MMIC chip can be evaluated without an increase in bonding pad capacitance.

Abstract: An integrated circuit arrangement having a number of structural elements, at least one of which is surrounded by a metallic shielding structure. This structural element is thus protected against interference due to disturbing impulses from its environment. In particular, the structural elements of the circuit arrangement can be arranged next to or on top of one another. To produce the metallic shielding structure of a structural element of the circuit arrangement, at least one depression which surrounds the structural element is created and then lined with metal. The contacts and electrical connections of the structural element are electrically insulated from the metal of the shielding structure.

Abstract: Packaged power devices include an electrically conductive flange having a slot therein and an electrically conductive substrate mounted within the slot. A dielectric layer is provided on the electrically conductive substrate and a gate electrode strip line is patterned on the dielectric layer. The gate electrode strip line extends opposite the electrically conductive substrate. A vertical MOSFET is also provided. The vertical MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line.

Abstract: A high frequency switch, has a transmitting terminal; a receiving terminal; an antenna terminal; a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal; a second diode having an anode connected through a transmission line of ¼ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded; and a control terminal provided to a node between the transmitting terminal and the first anode, wherein the first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.

Abstract: A composite module and its production process which allow multiple functions, miniaturization, low power consumption and low costs without requiring any external chip parts at all. A high-frequency integrated circuit is embedded in a silicon substrate, a high-frequency high-capacity bypass capacitor and a matching coil using thin films of different types of materials are also formed on the silicon substrate, a high-frequency high-capacity bypass capacitor is further formed with an interlayer insulation film between them, and these elements and the high-frequency integrated circuit are connected via a wiring layer.

Abstract: A semiconductor device is provided which is capable of reducing direct current resistance in a signal line, of reducing a high-frequency resistance even in the case of transmitting high-frequency signals and, therefore, of increasing power gain when employed in, for example, an MMIC for high power. The semiconductor device has a microstrip line containing an interlayer dielectric and signal line formed on a semiconductor substrate on which predetermined circuit devices are mounted, wherein the signal line is made multi-layered with the interlayer dielectric interposed among the multiple layers and wherein the interlayer dielectric is made so thin that pin holes are produced and each layer constituting the signal line is electrically connected to each other through the pin holes.

Abstract: A high-frequency circuit, wherein there is provided a switching transistor connected between an input terminal and an output terminal, with a gate electrode connected to a control terminal via a resistance element, and with an effective gate portion of the gate electrode divided into a plurality of sections, and arrangement is made of additional capacitance elements added in parallel to a capacitance between a gate and a source or drain of the switching transistor at positions in proximity to one ends of at least two effective gate sections of the plurality of effective gate sections. Preferably, there is provided a short-circuiting transistor similarly having an additional capacitance element between the output terminal Tout and a reference voltage supply line.

Abstract: A traveling wave FET in which increasing distances between electrodes and the design of semiconductor regions associated with the various electrodes act to increase maximum gain parameters of the device. The relationship of the electrode series resistance is also considered in the design as it affects these gain parameters.

Abstract: A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p-well (22) includes a plurality of n-well plugs (27) extending from the surface of the semiconductor device (20) into the isolated p-well (22) and contacting the buried n-well (25). The plurality of n-well plugs (27) reduces an n-well resistance to provide better noise isolation for high frequency signals.

Abstract: A Microwave/Millimeter-wave Monolithic Integrated Circuit (MMIC) device including PIN diode and Schottky diode circuits that provides improved performance with a reduced cost of manufacture. The planar, glass-passivated, MMIC device is fabricated in silicon technology and includes mesa isolation between the PIN diode and the Schottky diode. The PIN and Schottky diodes include respective anode regions having different thicknesses and resistivity for implementing the PIN and Schottky diode functions. Further, the Schottky anode region is formed relatively late in a process for fabricating the Si MMIC device to allow the Schottky anode region to be formed in approximately the same plane as the PIN anode region and to allow precise control of the relative thicknesses of the PIN and Schottky anode regions.

Abstract: A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.

Abstract: A semiconductor apparatus comprises a resistor formed in a driver to connect a driving device to a transmission line connecting the driver to a receiver. The resistor has resistance considerably larger than on-state resistance of the driving device on condition that the resistor matches output impedance of the driver with impedance of the transmission line. The transmission line has length decided so that a reflected wave from a receiver-side end of the transmission line reaches the driver while a driving signal supplied to the driver has a logical high or low level.

Abstract: A microwave transistor structure comprising: (a) a SiC substrate having a top surface; (b) a silicon semiconductor material of a first conductivity type overlaying the top surface of the semiconductor substrate and having a top surface; (c) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (d) a channel region of the first conductivity type formed completely within the silicon semiconductor material including a channel dopant concentration; (e) a drain region of the second conductivity type formed in the silicon semiconductor material and contacting the channel region; (f) a body region of the first conductivity type and having a body region dopant concentration formed in the silicon semiconductor material under the conductive gate region; (g) a source region of the second conductivity type and having a source region dopant concentration formed in the silicon semiconductor material within the body region; (h) a shield plate region being adjacent and being pa

Abstract: A small area cascode FET structure capable of operating at mm-wave frequenices cascades a common-source (CS) FET with a common gate (CG) FET, in a smaller physical area than conventional cascode FET structures. The small area of the cascode FET structure is partially achieved by using small source via grounds, requiring a thin gallium arsenide substrate (typically between 50 and 70 microns thick). The overall cascode area is reduced further, by having the two FETs share a common node. This common node is the output drain manifold of the CS FET, which is also an input source finger of the CG FET. In addition, small via grounds within the MIM capacitors and CS FET, which provide the ground connection to the gate manifolds of the CG FET, further reduce circuit area. Advantageously, the small area cascode FET can be applied to many different MMICs to reduce MMIC area requirements and cost.

Abstract: A microwave device, including a substrate having a first surface and a second surface, a plurality of electrically conductive vias extending through the substrate from the first surface to the second surface, a first interconnect trace connected to the first surface of the substrate and electrically connected to a first of the plurality of vias, a second interconnect trace connected to the first surface of the substrate and electrically connected to a second of the plurality of vias, and a microwave circuit chip connected to the second surface of the substrate and electrically connected to the first and second conductive vias.

Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output.

Abstract: A microstrip line includes a first conductor pattern formed on a substrate, a second conductor pattern formed on the first conductor pattern with a width substantially identical with a width of the first conductor pattern, and a third conductor pattern formed on the second conductor pattern with a width smaller than the width of the second conductor pattern.

Abstract: A filter that can achieve miniaturization and low power consumption at the same time without reducing operation precision, and a modulation semiconductor integrated circuit suitable for a wireless communication system using the filter are realized. In a modulation semiconductor integrated circuit including a digital filter that sample a digital transmission data signal an odd number of times for each two symbol cycles to perform product-sum operations, and a DA conversion circuit that subjects the output of the digital filter to DA conversion, a compensating circuit is provided which inserts predetermined values different from two types of symbols to the input of the digital filter.

Abstract: A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and a semiconductor circuit and a method for driving the same, having a semiconductor circuit 11, an input signal generation circuit 12 able to change the phase difference i of a reference signal out&phgr;i and an input signal out&phgr;0 in accordance with a control signal Si when generating the two signals from a clock, a monitor circuit 13 having a characteristic between a power supply voltage and delay the same as that of a critical path of the semiconductor circuit 11, propagating the input signal out&phgr;0, and outputting a delayed signal out&phgr;0′ to be delayed exactly by a time equivalent to a delay of the critical path (or smaller by a constant ratio), a delay detection circuit 14 for detecting a delay of the delayed signal out&phgr;0′ relative to the reference signal out&phgr;i, and a power supply voltage control circuit 15 for co

Abstract: A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.

Abstract: A microwave monolithic integrated circuit comprises a T-shaped gate electrode including a Schottky gate electrode formed on a first region of a compound semiconductor substrate, a pair of ohmic electrodes making an ohmic contact with a surface of the substrate in the first region at respective sides of the T-shaped gate electrode, a lower capacitor electrode pattern formed on a second region of the compound semiconductor substrate with a composition substantially identical with a low-resistance, top electrode constituting the T-shaped gate electrode on the Schottky gate electrode, a dielectric film formed on the lower electrode pattern, and an upper electrode pattern formed on the dielectric film.

Abstract: A microwave microstrip/waveguide transition structure includes a substrate, an elongated microstrip layer residing on a surface of the substrate, and an elongated integral hollow waveguide on the surface of the substrate. The microstrip layer and a side of the hollow waveguide constitute a single continuous piece of metal. The transition structure is fabricated by providing a substrate, depositing a metallic layer on the substrate, and depositing a metallic hollow housing continuous with a portion of a length of the metallic layer. The metallic hollow waveguide bounded by the metallic layer and the metallic hollow housing and having a contained volume therewithin is thereby defined.

Abstract: A monolithic integrated circuit has a plurality of capacitors forming a bypass to ground, each of the capacitors being composed of two conductive coatings layers which are arranged on a substrate and separated from one another by a dielectric layer, a lower one of the coatings located on the substrate under the dielectric layer contacting with a ground conductor on an opposite substrate side, and the lower coatings of the capacitors being connected with one another, while only one upper coating which belongs to a capacitor is contacted through a through contacting in the substrate with the ground conductor.

Abstract: The invention relates notably to an integrated microwave module comprising a conductive ground plane, a non-conductive substrate on the ground plane, at least two microwave circuits mounted on the substrate, a microstrip line between the microwave circuits mounted on the substrate, and a conductive cover closing the integrated microwave module,

Abstract: A semiconductor device provided with a field effect transistor having a electrode pads for wire-bonding comprises a first electrode pad for wire-bonding directly connected with the field effect transistor, and a second electrode pad for wire-bonding connected with the field effect transistor via a resistor. According to the semiconductor device, a chip used in the field effect transistor can be used in different frequencies by changing bonding.