Microwave Integrated Circuit (e.g., Microstrip Type) Patents (Class 257/275)
  • Publication number: 20020140088
    Abstract: A semiconductor integrated circuit has a 3-dimmensional interconnection line structure for high-speed operation. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a 3-dimmensional tournament tree shaped multilayer interconnection lines, wherein a single electric feeding point on a top surface of the MMIC is divided, layer by layer, into plural electrodes on the semiconductor substrate of the MMIC via a plurality of laminated interconnection layers and vertical interconnection layers therebetween shaped like a tournament tree.
    Type: Application
    Filed: March 1, 2002
    Publication date: October 3, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh
  • Patent number: 6455880
    Abstract: A high frequency semiconductor device has a semiconductor substrate such as the semi-insulating GaAs; a first metal layer disposed above the semiconductor substrate; a first dielectric thin film disposed on the first metal layer; and a second metal layer having a second metal strip disposed on the first dielectric thin film. Here, the first metal layer has a first metal strip, first and second ground metal plates sandwiching the first metal strip. And the first dielectric thin film is not disposed uniformly on the surface of the first ground metal plate so that the dielectric structure on the first metal strip differs from the dielectric structure under the second metal strip. The CPW is constituted by the first metal strip, the first and second ground metal plates, and the TFMSL is constituted by the second metal strip and the first ground metal plate.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: September 24, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Ono, Yuji Iseki, Keiichi Yamaguchi, Junko Onomura, Eiji Takagi
  • Patent number: 6448858
    Abstract: A side fed RF amplifier comprising a plurality of transistors connected in parallel such that the base, emitter, and collector leads of each transistor are electrically connected to the base, emitter, and collector leads, respectively, of all other transistors. A common, physical point interconnects the power amplifier current source and the base leads of every transistor. The transistors are arranged such that the impedance between the common physical point and the base lead of any one transistor is substantially equivalent to the impedance between the common point and the base lead of any other transistor within the power amplifier.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: David R. Helms, Philip Antognetti
  • Publication number: 20020110942
    Abstract: The present invention is generally drawn to a system and method for creating RF integrated microwave circuits that can support multiple applications where many RF functions can be derived from a generic integrated circuit after the RF integrated microwave circuit is manufactured. More specifically, the present invention can provide active and passive device building blocks of respective monolithic microwave integrated circuit (MMIC) arrays and substrates that can be coupled together in various ways after manufacture of the integrated circuits to achieve multiple applications. This can accomplished by manufacturing chips with multiple active device blocks that can support various and multiple applications and that can be coupled together in various ways, adjusted, or tuned after manufacture.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 15, 2002
    Applicant: RF Solutions, Inc.
    Inventors: Sanjay B. Moghe, Carl S. Chun, Pranav N. Patel, Seung-yup Yoo
  • Publication number: 20020063269
    Abstract: A method, apparatus, article of manufacture, and a memory structure for selectively phase shifting one or more frequency components of a signal is described. The apparatus comprises a conductor, a ground plane, a dielectric disposed between the ground plane and the conductor, wherein the dielectric is characterized by a non-homogeneous dielectric constant.
    Type: Application
    Filed: October 18, 2001
    Publication date: May 30, 2002
    Inventor: Joseph T. DiBene
  • Publication number: 20020063270
    Abstract: A high frequency switch circuit device includes an FET to be a switching element on a semiconductor substrate. The FET includes an n-type well, a gate electrode, a source layer and a drain layer. An n-type well line to be connected to an n-type well layer to be a back gate is connected to a voltage supply node via an inductor. The flow of a high frequency signal between the voltage supply node and the n-type well layer is blocked by the inductor, and the flow of a high frequency signal in the vertical direction is blocked by a depletion layer extending between the n-type well and a p-type substrate region. Moreover, the flow of a high frequency signal in the horizontal direction is blocked by a trench separation insulative layer.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 30, 2002
    Inventors: Toshifumi Nakatani, Junji Ito, Ikuo Imanishi
  • Patent number: 6380623
    Abstract: A microwave-frequency microcircuit assembly includes an integrated circuit structure having a circuit ground. A support structure includes a grounded metallic carrier, and a dielectric substrate having a top surface, a bottom surface contacting the carrier, and a capacitor via extending through the dielectric substrate. A metallization on the top surface of the substrate includes an input metallization trace to the integrated circuit structure, an output metallization trace from the integrated circuit structure, and a substrate ground plane upon which the integrated circuit structure is affixed. A thin-film capacitor resides in the capacitor via and is electrically connected between the substrate ground plane and the carrier. An electrical resistor is connected between the circuit ground of the integrated circuit structure and the carrier to self-bias the integrated circuit structure.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: April 30, 2002
    Assignee: Hughes Electronics Corporation
    Inventor: Walter R. Demore
  • Patent number: 6362012
    Abstract: A new method and structure is provided for the simultaneous creation of inductive and capacitive components in a monolithic substrate. The invention provides a method and structure whereby a vertical spiral inductor is created on the surface of a substrate. Multiple capacitors are created inside the coils of the vertical spiral conductor. A base layer of dielectric is deposited over the surface of a semiconductor substrate, contact plugs are provided in the base layer of dielectric. Multiple layers of dielectric are deposited over the surface of the base layer, layers of coils are created in the multiple layers of dielectric. Vias are provided in the layer of dielectric to interconnect overlying coils of the spiral inductor. An etch stop layer is deposited on the surface of the upper layer of dielectric.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: March 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Min-Hwa Chi, Chia-Shiung Tsai, Yeur-Luen Tu
  • Publication number: 20020030269
    Abstract: A microwave monolithic integrated circuit (MMIC) package includes a MMIC and a base plate that is matched as to its coefficient of thermal expansion (CTE) with the MMIC. A solder preform is contained on the base plate. The MMIC is mounted on the solder preform. A chip cover covers the MMIC and are configured with respective portions that engage each other such that any pads on the MMIC are exposed for wire and ribbon bonding. The base plate and MMIC are secured together by a solder flow process from the solder preform.
    Type: Application
    Filed: May 22, 2001
    Publication date: March 14, 2002
    Applicant: Xytrans, Inc.
    Inventor: Dan F. Ammar
  • Publication number: 20020014641
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: September 25, 2001
    Publication date: February 7, 2002
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Patent number: 6344658
    Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: February 5, 2002
    Assignee: New Japan Radio Co., Ltd.
    Inventors: Atsushi Nakagawa, Kenichi Watanabe
  • Patent number: 6340823
    Abstract: There is described a semiconductor wafer suitable for efficiently testing a plurality of logic chips formed thereon without damaging input/output sections of the chips. A plurality of chips, a test circuit, and output pads are formed on a semiconductor wafer. A plurality of input pads of the test circuit are connected to terminals corresponding to all the chips by way of a test pattern. The chips are connected to the output pads by means of test patterns. All the chips are subjected to a test (or multi-test) through use of the test circuit and the output pads. The test circuit and the output pads are provided in the peripheral area of the semiconductor wafer.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: January 22, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Osamu Kitade
  • Patent number: 6326857
    Abstract: A voltage controlled oscillator formed as a first layout with metallized areas by a planar technique is located on a high dielectric loss substrate. A second layout formed of metallized area for control circuits of the voltage controlled oscillator is formed on a high loss dielectric substrate is also formed by the same technique as the first layout. A ground plane for the controlling oscillator is formed on an opposite side of the dielectric substrate on which the voltage controlled oscillator is formed.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: December 4, 2001
    Assignee: Siemens Inofmraton and Communication Networks S.p.A.
    Inventors: Carlo Buoli, Giovanni Mora
  • Publication number: 20010045583
    Abstract: A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.
    Type: Application
    Filed: July 16, 1998
    Publication date: November 29, 2001
    Inventors: FUKASHI MORISHITA, TERUHIKO AMANO, KAZUTAMI ARIMOTO, TETSUSHI TANIZAKI, TAKESHI FUJINO, TAKAHIRO TSURUDA, MITSUYA KINOSHITA, MAKO KOBAYASHI
  • Patent number: 6323533
    Abstract: A semiconductor device (1) with an operating frequency above 50 MHz comprises a body (2) composed of a soft ferrite material, which body (2) has a surface (3) to which a semiconductor element (4), a pattern of conductors (5,6) and a passive element in the form of a planar inductor (7) are fastened by means of a layer (8) of adhesive. In order to reduce the manufacturing costs of the semiconductor device without adversely affecting the performance of the semiconductor device performance, a soft ferrite material is applied having a ferromagnetic resonance frequency smaller than the operating frequency of the semiconductor device.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: November 27, 2001
    Assignee: U.S. Philips Corporation
    Inventors: Pieter Jan Van Der Zaag, Ronald Dekker, Wilhelmus Mathias Clemens Dolmans
  • Patent number: 6316827
    Abstract: A semiconductor device of the present invention includes ohmic source plate electrodes, gate plate electrodes, and drain plate electrodes in parallel from each other in a heat generating region various designs are used to more evenly distribute heat generated in the semiconductor device. A first example has gold-plate electrodes formed on the respective source and drain plate electrodes in parallel with the ohmic plate electrodes. The gold-plate electrode arranged at the central portion of the heat generating region plate electrodes has the widest width and gold-plate electrodes arranged toward the center portion to the peripheral portion of the heat generating region narrow gradually. By the structure mentioned above, the semiconductor device of the present invention has uniform temperature distribution in a heat generating region. A second example uses a plurality of stripe plates perpendicular to the ohmic plate electrodes.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventors: Kazunori Asano, Kouji Ishikura
  • Patent number: 6313493
    Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 6, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiki Mori, Ichiro Nakao, Tsutomu Fujita, Reiji Segawa
  • Patent number: 6303950
    Abstract: A field effect transistor (FET) having a stabilization circuit with a stabilization condition not affected by another circuit element, for example, a matching circuit. The stabilization circuit is pre-formed inside of the FET, thereby pre-stabilizing the FET in a frequency range in which a power amplifier is used.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: October 16, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hitoshi Kurusu, Junichi Udomoto
  • Patent number: 6285269
    Abstract: A drain electrode and a source electrode are provided for an intrinsic device section on a GaAs substrate with a gate electrode placed therebetween. Almost all or substantial parts of the GaAs substrate is covered by an extending source electrode extending from the source electrode. A belt-shaped extending drain electrode is provided on the extending source electrode with a dielectric layer placed therebetween, and thereby an output-side microstripline is formed. A belt-shaped extending gate electrode is also provided on the extending source electrode with a dielectric layer placed therebetween, and thereby an input-side microstripline is formed.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: September 4, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yohei Ishikawa, Koichi Sakamoto, Sadao Yamashita, Takehisa Kajikawa
  • Patent number: 6274889
    Abstract: A semiconductor device having a single substrate made of silicon carbide; an epitaxial film made of AlxInyGa(1−x−y)N which is selectively formed on the single substrate; an amplifier section including a gate formed on the single substrate and a source layer and a drain layer which are formed within the single substrate; and another amplifier section formed on the epitaxial film.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: August 14, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yorito Ota, Hiroyuki Masato, Yasuhito Kumabuchi, Makoto Kitabatake
  • Patent number: 6236092
    Abstract: A mixed mode device. A polysilicon layer is over a substrate having a well therein. A first metal layer is formed over the polysilicon layer. A second metal layer is formed over the first metal layer. A conductive type of the well and a conductive type of the substrate are oppositive. A part of the polysilicon layer is positioned over the well. Heavily doped regions are further formed in the well beside the polysilicon layer. The polysilicon layer is used as gates of MOS transistors, and the heavily doped regions are used as source/drain regions of the MOS transistors. The first metal layer over the gate has a finger structure which electrically couples with the drain regions of the MOS transistors. The second metal layer electrically couples with the source regions through vias.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: May 22, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Hsiung Chen, Hsiu-Chin Chen, Shen-Yuan Chou, Shih-Yin Hsiao
  • Patent number: 6222266
    Abstract: A source electrode, gate electrode, drain electrode, and a gate bus bar connected to said gate electrode are formed on a semiconductor chip. A field effect transistor unit constructed on the semiconductor chip is made up of three adjacent fingers each extending from the source electrode, gate electrode, and drain electrode. The source electrode is formed on the outer edge of the semiconductor chip from the obverse to the reverse surfaces of the semiconductor chip.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: April 24, 2001
    Assignee: NEC Corporation
    Inventor: Junko Kohno
  • Patent number: 6211541
    Abstract: An article for de-embedding parasitics and/or acting as an on-wafer calibration standard is disclosed. In particular, some articles in accordance with the present invention provide structures on integrated circuits that mitigate the severity of parasitics Furthermore, some articles in accordance with the present invention are well-suited for use with conductive substrates that operate at high frequencies. In an illustrative embodiment, conductive elements are used to construct structures near and/or around the leads on the integrated circuit. When the structures are grounded, the structures function to (at least) partially shield the leads to and from the DUT in a manner that is analogous to stripline, microstrip and coaxial cable. Because the electric fields emanating from the leads terminate in the grounded structure and not in the conductive substrate of the integrated circuit, the severity of the parasitics in the leads in mitigated.
    Type: Grant
    Filed: February 2, 1999
    Date of Patent: April 3, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Michael Scott Carroll, Tony Georgiev Ivanov, Samuel Suresh Martin
  • Patent number: 6194750
    Abstract: An integrated circuit is disclosed that comprises structures that confine, shield and/or manipulate the electric fields generated within the integrated circuit so as to improve the performance of the integrated circuit. Such structures include, but are not limited to, transmission lines, capacitors, inductors, filters, and couplers. Although embodiments of the present invention are advantageous for use on many integrated circuits, they are particularly well suited for use with integrated circuits that are disposed on conductive substrates and that operate at high frequencies.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: February 27, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Michael Scott Carroll, Tony Georgiev Ivanov, Samuel Suresh Martin
  • Patent number: 6169301
    Abstract: A planar dielectric integrated circuit is provided such that energy conversion loss between a planar dielectric line and electronic components is small and that impedance matching between them can be easily obtained. By providing slots which oppose both main surfaces of a circuit substrate, two planar dielectric lines are constructed. A slot line, and a first line-conversion conductor pattern which is connected to the electromagnetic field of the slot line and a first planar dielectric line in order to perform line conversion, are provided at the end portion of the first planar dielectric line, including a slot. A coplanar line and a second line-conversion conductor which is made to project in a direction at right angles to a second planar dielectric line is provided at the end portion of the second planar dielectric line, including a slot. A semiconductor device is placed in such a manner as to be extended over the coplanar line and the slot line.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: January 2, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yohei Ishikawa, Koichi Sakamoto, Sadao Yamashita, Takehisa Kajikawa
  • Patent number: 6137125
    Abstract: The present invention is drawn to a 2-layer hermetic coating for on wafer encapsulation of GaAs monolithic microwave integrated circuits and the flip-chip mounting thereof. The present invention utilizes the properties of benzocyclobutene (BCB) for use in high frequency microwave applications to capacitively decoupled the MMIC from the carrier substrate during the flip-chip mounting process. The present invention has the advantage of improved performance and reliable flip-chip mounting by the reduction in stress between the carrier substrate and the MMIC that often occurs in flip-chip mounting of the MMIC.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: October 24, 2000
    Assignee: The Whitaker Corporation
    Inventors: Varmazis D. Costas, Anthony Kaleta
  • Patent number: 6114696
    Abstract: An infrared radiation detector device comprises a dipole antenna mounted on a substrate and connected through blocking contacts to a bandgap detector element. The dipole antenna has a length which is approximately one half the wavelength of the incident infrared radiation. The bandgap detector element has linear dimensions which are each substantially smaller than the wavelength of the detected radiation. A group of detector devices are combined to form an array which can produce a pixel signal for an image. Unlike conventional infrared radiation detectors, the disclosed detector device is capable of producing a usable output signal without the need for cooling below ambient temperature.
    Type: Grant
    Filed: July 14, 1986
    Date of Patent: September 5, 2000
    Assignee: Lockheed Martin Corporation
    Inventor: Dayton D. Eden
  • Patent number: 6114716
    Abstract: Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: September 5, 2000
    Assignee: The Whitaker Corporation
    Inventors: Timothy Edward Boles, Joel Lee Goodrich
  • Patent number: 6114697
    Abstract: An infrared radiation detector device has an array of detectors each of which comprises a pattern of parallel detector elements. Each detector produces a pixel signal for an image. The elements of the detector are photoconductive or photovoltaic bandgap materials and the elements are spaced apart at a dimension which is equal to or less than the wavelength of the radiation to be received. Additional layered structures above and/or below the detector elements provide impedance matching between free space radiation and the radiation impedance of the detector elements to increase the capture of radiation.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: September 5, 2000
    Assignee: Lockheed Martin Corporation
    Inventors: Dayton Dale Eden, William Edward Case, Thomas R. Schimert
  • Patent number: 6111254
    Abstract: An infrared radiation detector is disclosed which is fabricated on a dielectric substrate. The detector utilizes photosensitive segments which are included within elongate members disposed on the surface of the substrate. The elongate members comprise photosensitive detector segments which are located between and contact non-photosensitive segments and the entirety of each strip is electrically conductive. The elongate members are preferably offset from each other by less than the wavelength of the radiation and the photosensitive segments within the elongate members are also preferably spaced apart by less than the wavelength of the radiation. A reflective plane, typically an aluminum layer, is offset from the plane of the detector segments by less than the wavelength of the radiation. Incident radiation is captured by the overall detector structure which includes the reflective plane and the elongate members which include both photosensitive and non-photosensitive segments.
    Type: Grant
    Filed: November 22, 1989
    Date of Patent: August 29, 2000
    Assignee: Lockheed Martin Corporation
    Inventor: Dayton D. Eden
  • Patent number: 6101099
    Abstract: The present invention relates to a device and a method for electrical and mechanical connection of an electric high-power component (111) which transmits high-frequency electrical signals to conductors (120) on a circuit board (119). The component comprises connections (114) projecting over the circuit board and which are soldered to the conductors (120) on the circuit board (119) with a solder material (112) which essentially lacks grain growth. The component is subject to repeated temperature changes which leads to stresses on the connection between the connections (114) and the conductors (120). The length of the connections is selected depending on a predetermined threshold value for the highest acceptable attenuation which the high-frequency electrical signal is subject to when passing through the electrical high-power component via the connections. The connections can be shaped so that they comprise a bent part with a bending which is determined in dependence of said threshold value.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: August 8, 2000
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Christer Olsson
  • Patent number: 6100554
    Abstract: An intrinsic device section is provided by laminating a drain area, an intermediate area, and a source area above a GaAs substrate and by forming a channel area at one oblique surface thereof. A drain electrode ohmic connected to the drain area extends toward the output side, a source electrode ohmic connected to the source area extends above the drain electrode with a dielectric layer placed therebetween, and thereby an output micro-wave transmission line is formed. A gate electrode Schottky connected to the channel area extends toward the input side, the source electrode extends above the drain electrode with the dielectric layer placed therebetween, and thereby an input micro-wave transmission line formed.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: August 8, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yohei Ishikawa, Koichi Sakamoto
  • Patent number: 6100525
    Abstract: An infrared radiation detector device comprises a dipole antenna mounted on a substrate and connected through blocking contacts to a bandgap detector element. The dipole antenna has a length which is approximately one half the wavelength of the incident infrared radiation. The bandgap detector element has linear dimensions which are each substantially smaller than the wavelength of the detected radiation. A group of detector devices are combined to form an array which can produce a pixel signal for an image. Unlike conventional infrared radiation detectors, the disclosed detector device is capable of producing a usable output signal without the need for cooling below ambient temperature.
    Type: Grant
    Filed: October 4, 1988
    Date of Patent: August 8, 2000
    Assignee: Lockheed Martin Corporation
    Inventor: Dayton D. Eden
  • Patent number: 6057569
    Abstract: The present invention provides a diode limiter device in which a first penetration hole is formed on a wall surface of an H surface; the PIN diode is supported by the PIN diode mounting side of the post with the PIN diode being electrically connected to the waveguide at the first penetration hole; a second penetration hole is formed on the other wall surface opposite to the wall surface; a second conductive boss which grasps the PIN diode with the post is electrically insulated and supported with respect to the second penetration hole; a wiring substrate with the detection diode and the resistor mounted thereon is installed; and the wiring substrate is supported in the second penetration hole by a third boss, thereby improving productivity and reducing cost.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: May 2, 2000
    Assignee: New Japan Radio Co., Ltd.
    Inventors: Ikuo Kisanuki, Manabu Tomita
  • Patent number: 6047117
    Abstract: Disclosed is a diffusion-equation-based method of determining the time-domain response of an IC interconnect to an input voltage signal. Time-dependent voltage response determinations are accomplished analytically in the Laplace domain, with appropriate boundary conditions, treating the voltage response as a superposition of transmitted and reflected diffusions, based on parasitics as known quantities per unit length. The voltage response is thus determined by summing distinct reflected diffusions originating at both sides of the interconnect. The analysis proceeds on the assumption that only a selected small number of reflective components--normally only four--are required for sufficient accuracy. Voltage response from a sequence of interconnects is determined by treating the voltage response from the first interconnect as the input to the second, and repeating such looping with successive interconnects. A final inverse transform may be accomplished to express the response in the time domain.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: April 4, 2000
    Assignee: The Regents of the University of California
    Inventors: Andrew B. Kahng, Sudhakar Muddu
  • Patent number: 6023080
    Abstract: A semiconductor device comprises a dielectric substrate formed on a metal carrier, a semiconductor chip formed on the dielectric substrate and having a first electrode, a microstrip line formed on the dielectric substrate and having a second electrode to be connected to the first electrode, and wires, having different lengths, for connecting the first and second electrodes.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: February 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruo Kojima
  • Patent number: 6014064
    Abstract: A voltage controlled oscillator includes a varactor (201) and a transistor (202) and a ground via (203), of epitaxially grown silicon that is etched to provide respective pedestals embodying the varactor (201) and the transistor (202) and the ground via (203), an L-C resonator circuit, the varactor (201) and an inductor providing a tank circuit that changes the frequency of the L-C resonator circuit, and that shifts the average frequency of the oscillator to that of an input voltage to the collector of the transistor (202).
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: January 11, 2000
    Assignee: The Whitaker Corporation
    Inventors: Timothy E. Boles, Joel L. Goodrich, Paulette R. Noonan, Brian Rizzi
  • Patent number: 6002147
    Abstract: The microwave hybrid integrated circuit comprises a dielectric board (1) provided with a topological metallization pattern (2) on its face side, a shield grounding metallization (3) on the back side thereof, a hole (4), and a metal base (5) having a projection (6). The hole (4) in the board (1) has a constriction (9) situated at a height of 1 to 300 .mu.m from the face surface of the board (1). The projection (6) is located in a wide section (10) of the hole (4). Bonding pads (8) of a chip (7) which are to be grounded are electrically connected to the projection (6) through the constricted portion (9) of the hole (4) which is filled with an electrically and heat conducting material (11). The wide section (10) of the hole (4) is from 0.2.times.0.2 mm to the size of the chip (7), and the distance between the side walls of the projection (6) and the side walls of the wide section (10) of the hole (4) is 0.001 to 1.0 mm.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: December 14, 1999
    Assignee: Samsung Electronics Company
    Inventors: Viktor Anatolievich Iovdalsky, Eduard Volfovich Aizenberg, Vladimir Iliich Beil, Mikhail Ivanovich Lopin
  • Patent number: 5998817
    Abstract: A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: December 7, 1999
    Assignee: Raytheon Company
    Inventors: Cheng P. Wen, Peter Chu, Michael R. Cole, Wah S. Wong, Robert F. Wang, Liping D. Hou
  • Patent number: 5994727
    Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: November 30, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Boong Lee
  • Patent number: 5969405
    Abstract: Integrated circuit structure having an active microwave component and at least one passive component.A high-resistance silicon substrate (11) comprises an active microwave component (16) and at least two metallization planes (12, 14), which are insulated from one another by an insulation layer (13). A passive component surrounded by a grounded line (122) in one of the metallization planes (12) is provided, which comprises a first metal structure (121), which is realized in the first metallization plane (12), and a second metal structure (141), which is realized in the other metallization plane (14). The passive component is designed, in particular, as a capacitor, coil or resonator which comprises a capacitor and a coil.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: October 19, 1999
    Assignee: Seimens Aktiengesellschaft
    Inventor: Thomas Aeugle
  • Patent number: 5955752
    Abstract: A semiconductor module having a compact antenna element capable of providing desired directivity therein has been disclosed. When an electromagnetic-wave radiation window has the capability of a lens, directivity can be set arbitrarily. For improving directivity, a convergent lens for converging millimeter waves or quasi millimeter waves is employed. For impairing directivity, a divergent lens is employed. In the case of the convergent lens, a direction in which radio waves are radiated or received by the antenna element can be set by deviating the center axis of the lens from the center of the antenna element.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: September 21, 1999
    Assignees: Fujitsu Limited, Olympus Optical Co. Ltd.
    Inventors: Jun Fukaya, Yoshio Aoki, Yasutake Hirachi, Jun-ichi Ishibashi, Toshio Yamamoto
  • Patent number: 5952709
    Abstract: A high-frequency semiconductor device contains a semiconductor element in a cavity formed by a dielectric board and a cap. A first high-frequency transmission line connected to the semiconductor element is formed on the surface of said dielectric board in said cavity and a second high-frequency transmission line is formed on the bottom surface of said dielectric board, so that said first high-frequency transmission line and said second high-frequency transmission line are electromagnetically coupled together. In this semiconductor devise in which the first transmission line and the second transmission line are electromagnetically coupled together, the transmission lines need not be passed over the side wall of the cap, and neigther reflection loss or radiation loss takes place on the side wall. Besides, transmission loss of high-frequency signals is caused by neigther through-holes or via-holes, and is effectively suppressed.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: September 14, 1999
    Assignee: Kyocera Corporation
    Inventors: Kenji Kitazawa, Shinichi Koriyama, Mikio Fujii
  • Patent number: 5952728
    Abstract: A thermoelectric conversion module having a large capacity and a curved surface which can be secured to a corresponding curved surface of a base member is manufactured by inserting N type and P type semiconductor strips into through holes formed in a honeycomb structural body, filling spaces between walls defining the through holes and the semiconductor strips with an electrically insulating filler members made of an easily deformable material such as polyimide resin and silicone resin, cutting the honeycomb structural body into a plurality of thermoelectric conversion module main bodies each having a desired surface configuration, and providing metal electrodes on both surfaces of a thermoelectric conversion module main body such that alternate N type and P type semiconductor elements are connected in cascade.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: September 14, 1999
    Assignees: NGK Insulators, Ltd., Nissan Motor Co., Ltd.
    Inventors: Yuichiro Imanishi, Makoto Miyoshi, Tetsuo Watanabe, Keiko Kushibiki, Kazuhiko Shinohara, Masakazu Kobayashi, Kenji Furuya
  • Patent number: 5932926
    Abstract: A microwave semiconductor integrated circuit having high isolation includes a wiring-side substrate including a transmission line in slots at a surface; an element-side substrate having an active element on a surface, the transmission line being embedded in the wiring-side substrate; and metal bumps electrically connecting the transmission line embedded in the wiring-side substrate to electrodes of the active element on the element-side substrate. Therefore, a connection between a transmission line and electrodes of an element, such as an FET or the like, can be easily realized without being affected by a difference in positional level between the transmission line and the electrodes. In addition, the element on the element-side substrate is not adversely affected by the subsequent fabrication of the slots and wiring layers and, therefore, the reliability of the integrated circuit is not adversely affected.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: August 3, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takaya Maruyama, Takahide Ishikawa, Noriyuki Tanino
  • Patent number: 5925901
    Abstract: A GaAs substrate is divided at boundary regions of unit cells of FET chips. With such construction, magnitude of curling of the GaAs substrate due to a difference of thermal expansion coefficients between the GaAs substrate and the PHS upon heating during assembling, can be reduced. In a semiconductor device with a PHS, the magnitude of curling of the semiconductor substrate after assembling can be reduced by reducing stress upon assembling, without causing degradation of reliability.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 20, 1999
    Assignee: NEC Corporation
    Inventor: Hiroaki Tsutsui
  • Patent number: 5914508
    Abstract: A microwave system encapsulated by two layers. The first layer is an arylcyclobutene polymer having a thickness greater than the tallest component of the system and only located in predetermined areas. Overlaying the polymer and other preselected areas of the system is a ceramic glass material. These two layers are applied in two layers coating process steps.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: June 22, 1999
    Assignee: The Whitaker Corporation
    Inventors: Costas D. Varmazis, Anthony Kaleta
  • Patent number: 5914497
    Abstract: A tunable antenna-coupled intersubband terahertz (TACIT) detector is based on intersubband absorption in doped semiconductor quantum wells. THz-frequency radiation impinges on a coplanar antenna. The antenna couples radiation into a narrow constriction in a two dimensional electron gas (the "active region") with electric field perpendicular to the plane of the antenna. Radiation, which is at the intersubband absorption frequency, is absorbed in the active region. The resulting change in resistance through the constriction is detected. The frequency of the absorption, and hence the detection frequency, can be tuned over the 1-5 THz range by applying small voltages between a front and back gate. The efficiency with which radiation couples from the antenna into the active region can be optimized at each frequency.TACIT detectors solve a number of outstanding problems associated with Terahertz detection including:1.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: June 22, 1999
    Inventor: Mark Sherwin
  • Patent number: 5913134
    Abstract: A micromachined self-packaged circuit provides at least partial shielding of a circuit element. Preferably, all the elements comprising a circuit are completely shielded between a first wafer of semi-conductor material having a recess and receiving a metallized layer therebeneath and a second wafer of semi-conductor material having a groove in a bottom face against which is received a metallized layer. The first wafer metallized face is then adhesively bonded to the second wafer on a surface opposite the metallized layer to which a circuit is affixed. The second wafer metallized face and metallized grooves cooperate with the first wafer metallized face to provide a shielded circuit cavity therebetween. Alternatively, the first or second wafer can be used alone to partially shield a circuit element.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: June 15, 1999
    Assignee: The Regents of the University of Michigan
    Inventors: Rhonda Franklin Drayton, Linda P. B. Katehi
  • Patent number: 5912484
    Abstract: An intrinsic device section is provided by laminating a drain area, an intermediate area, and a source area above a GaAs substrate and by forming a channel area at one oblique surface thereof. A drain electrode ohmic connected to the drain area extends toward the output side, a source electrode ohmic connected to the source area extends above the drain electrode with a dielectric layer placed therebetween, and thereby an output micro-wave transmission line is formed. A gate electrode Schottky connected to the channel area extends toward the input side, the source electrode extends above the drain electrode with the dielectric layer placed therebetween, and thereby an input micro-wave transmission line formed.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: June 15, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yohei Ishikawa, Koichi Sakamoto