Abstract: A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series.

Abstract: In one embodiment of the disclosure, a method includes providing a carrier substrate, forming a first region over an upper surface of the substrate, creating an electrical component using a planar process, embedding the electrical component in the dielectric layer, and removing a substrate portion of the electrical component. The first region includes a dielectric layer and may be made of any material that electrically isolates the electrical component from the carrier substrate. The electrical component may be created using a planar process thereby having an epitaxial surface that is embedded in the dielectric layer.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: Embodiments of apparatuses, articles, methods, and systems for a monolithic microwave integrated circuit with a substrate having a diamond layer are generally described herein. Other embodiments may be described and claimed.

Abstract: A semiconductor device which has low input inductance is provided.

Abstract: A three-dimensional integrated device includes at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair with the ground plane and placed in the aperture, and a transmitter and/or a receiver that is connected to the microstrip line and transmits and/or receives signals at a frequency substantially corresponding to the perimeter ? of the aperture. Each of the apertures in each of the integrated circuit substrates is superimposed on at least one of the apertures in the other integrated circuit substrates in the direction perpendicular to the ground planes, and the signals are transported in a contactless manner between the integrated circuit substrates through the apertures at a frequency substantially corresponding to the perimeter ? of the apertures.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.

Abstract: A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.

Abstract: A thin film magnetic device is provided, in which magnetic permeability in a high frequency range can be easily improved. Scratch-like grooves extending along an extending direction of a coil (for example, a Y-axis direction being an extending direction of a second coil part) are formed at least one side of a surface and a back of each of a lower magnetic film and an upper magnetic film. A magnetization direction of anisotropic magnetization is controlled in each of formation areas of the scratch-like grooves (formation areas of lower magnetic films and upper magnetic films), and therefore displacement (rotation) of the magnetization direction of the anisotropic magnetization is pinned by the scratch-like grooves. Consequently, certain magnetic permeability is kept even in a high frequency range. Moreover, such formation of the scratch-like grooves may not cause complexity in manufacturing process.

Abstract: A bond wire circuit includes bond wires arranged relatively to provide a selected inductance. In connection with various example embodiments, respective bond wire loops including forward and return current paths are arranged orthogonally. Each loop includes a forward bond wire connecting an input terminal with an intermediate terminal, and a return bond wire connecting the intermediate terminal to an output terminal. The return bond wires generally mitigate return current flow from the intermediate terminal in an underlying substrate. In some implementations, the loops are arranged such that current flowing in each of the respective loops generates equal and self-cancelling current in the other of the respective loops.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.

Abstract: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on a substrate and a raised conductor formed to protrude from the bottom conductor, a dielectric film formed on the raised conductor, and a second conductor formed on the dielectric film to constitute a capacitor element in combination with the raised conductor and the dielectric film.

Abstract: Electrode placement which applies easy heat dispersion of a semiconductor device with high power density and high exothermic density is provided for the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate 10, and have a plurality of fingers, respectively; gate terminal electrodes G1, G2, . . . , G4, source terminal electrodes S1, S2, . . . , S5, and a drain terminal electrode D which are placed on the first surface, and governs a plurality of fingers, respectively every the gate electrode, the source electrode, and the drain electrode; active areas AA1, AA2, . . . , AA5 placed on the substrate of the lower part of the gate electrode, the source electrode, and the drain electrode; a non-active area (BA) adjoining the active areas and placed on the substrate; and VIA holes SC1, SC2, . . .

Abstract: In one embodiment of the disclosure, a method includes providing a carrier substrate, forming a first region over an upper surface of the substrate, creating an electrical component using a planar process, embedding the electrical component in the dielectric layer, and removing a substrate portion of the electrical component. The first region includes a dielectric layer and may be made of any material that electrically isolates the electrical component from the carrier substrate. The electrical component may be created using a planar process thereby having an epitaxial surface that is embedded in the dielectric layer.

Abstract: A suspended-membrane/suspended-substrate monolithic microwave integrated circuit module and method of making same. The device contains a plurality of active devices, such as transistors, a plurality of transmission mediums connected to the active devices; and a substrate having a first portion supporting the active devices and the transmission mediums thereon, and further having a plurality of discrete second portions extending from the first portion. The method teaches how to manufacture the device.

Abstract: A high-frequency switch is constructed by connecting a first diode and a second diode that function as switching elements, inductors, capacitors, and resistors. One end of the resistor is connected between the first diode and the second diode, and the other end of the resistor is connected to the ground. Thus, charges accumulated in the diodes in the ON states are immediately released to ground via the resistor. Accordingly, quick switching from the transmission mode to the reception mode by switching of a control power supply terminal from ON to OFF is achieved.

Abstract: A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region.

Abstract: An ink jet head circuit board is provided which has heaters to generate thermal energy for ink ejection as they are energized. This circuit board reduces areas of the heaters to achieve higher printing resolution and image quality. This board also prevents a degradation of thermal energy efficiency and reduces power consumption. The protective insulation layer for the electrode wire layer is formed of two layers and one of the two layers is removed from above the heater to improve the heat energy efficiency. The resistor layer is deposited over the electrode wire layer. The patterning for removing the protective insulation layer is done in a wider range than a gap of the electrode wire layer, the gap being used to form the heater. Further, by forming the electrode wires in two layers, a possible reduction in an effective bubble generation area of the heater can be prevented.

Abstract: An integrated packaging assembly for an MMIC that uses the semiconductor wafers on which circuit elements are fabricated as the package. The packaging assembly includes a plurality of semiconductor layers that have been diced from the semiconductor wafers, where the semiconductor layers can be made of different semiconductor material. The semiconductor layers define cavities therebetween in which circuit components are fabricated. A sealing ring seals the semiconductor layers together so as to hermetically seal the circuit components within the cavities.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.

Abstract: High-resistance elements are connected as parts of a control resistor between a switching element and a protecting element immediately near the switching element and between adjacent protecting elements. Paths for high-frequency signals are cut off, and high-frequency signals can be prevented from leaking although there are parasitic capacitances due to the protecting elements being connected. Accordingly, electrostatic breakdown voltage can be improved, and isolation can be prevented from deteriorating.

Abstract: A semiconductor device includes a semiconductor chip, electrodes pads, first and second insulating layers, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The first insulating layer is formed on the first and second areas of the semiconductor chip and exposes the electrode pads. The first conductive pattern transfers a signal and is formed on the first insulating layer. A second insulating layer is formed on the first conductive pattern and the first insulating layer. The second conductive pattern is formed on the second insulating layer and provides a ground potential. The external terminals are formed on the first and second patterns at the second area.

Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.

Abstract: A semiconductor integrated circuit device includes a HFET formed on part of a substrate made of sapphire and including a Group III-V nitride semiconductor layer, a dielectric film formed on the substrate to cover the top and side surfaces and upper corners of the Group III-V nitride semiconductor layer, a microstrip line formed with the dielectric film interposed between the substrate and the microstrip line, and a drain lead which is formed on part of the dielectric film and through which the HFET is electrically connected to the microstrip line.

Abstract: A BST microwave device includes a substrate and an insulating layer that is formed on the substrate. A buffer layer is formed on the insulating layer. A BST layer is formed on the buffer layer with a selected orientation for high tunability and possesses a low loss in a wavelength of interest.

Abstract: An integrated microwave transistor amplifier includes a AlGaN/GaN active transistor arrangement on a thinned Si 1-mil heat spreader. Elongated, plated-through vias extend from the source portions of the transistor arrangement through the spreader to a thick gold supporting layer. A matching circuit is defined on a four-mil GaAs substrate, also with a thick gold support layer. A stepped heat sink supports the matching circuit and the active transistor with surfaces coplanar. Bond wires interconnect the matching circuit with the gate or drain connections of the transistor.

Abstract: Disclosed are an active smart antenna system and a method thereof. The system comprises: an antenna for receiving a signal; a low noise amplifier for amplifying a signal received through the antenna so as to minimize a noise generation; and a phase shifter for controlling a phase of the amplified signal. The antenna, the low noise amplifier, and the phase shifter are formed on one high resistance substrate.

Abstract: A field effect transistor structure includes a single crystal substrate having: a source, gate and drain electrodes disposed on an upper surface of the substrate, the gate electrode having a region thereof disposed between a region of the drain electrode and a region of the source electrode; a ground conductor disposed on a lower surface of the substrate; a plurality of electrically conductive vias passing through the substrate, each one of the vias having one end electrically connected to a different region of the ground conductor and having another end electrically connected to the gate electrode. The plurality of electrically conductive vias provide parallel and symmetric connections between the gate electrode and the ground conductor.

Abstract: A system and method for an electronically scanned antenna is provided in which phase shifters are deposited en masse along with other electronically scanned antenna components on a wafer scale substrate using a thin film process. Alternative wafer scale sizes may be utilized to furnish a required antenna aperture area. Significant processing costs for radar and communication systems are saved utilizing the present invention as compared with contemporary discrete phase shifters that are individually mounted on an antenna. In an aspect, the phase shifter is made up of a base electrode, a barium strontanate titanate (BST) ferroelectric varactor and a top electrode. The BST ferroelectric material is a voltage variable dielectric, which generates a radiation phase. The radiation phase is regulated by a phase shifter control. The radiation phase generates an electromagnetic field about a radiating element and electromagnetic radio waves are radiated from the radiating element.

Abstract: A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a magnetic core. The magnetic coupling between the primary and secondary windings inhibits the coupling of electrical noise between the analog and digital circuitries.

Abstract: A three-dimensional integrated device includes at least two integrated circuit substrates laminated to each other, each of the integrated circuit substrates having at least one ground plane, at least one aperture provided at a desired location in the ground plane, the end of a microstrip line formed in a pair with the ground plane and placed in the aperture, and a transmitter and/or a receiver that is connected to the microstrip line and transmits and/or receives signals at a frequency substantially corresponding to the perimeter ? of the aperture. Each of the apertures in each of the integrated circuit substrates is superimposed on at least one of the apertures in the other integrated circuit substrates in the direction perpendicular to the ground planes, and the signals are transported in a contactless manner between the integrated circuit substrates through the apertures at a frequency substantially corresponding to the perimeter ? of the apertures.

Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.

Abstract: A calibration structure for probing devices.

Abstract: Floating conducting regions at floating potentials are placed on a substrate surface between adjacent conducting regions to which predetermined potentials are applied. This makes it possible to block the spread of a depletion layer to the substrate between the conducting impurity regions. Thus, the leakage of high-frequency signals can be suppressed. In particular, in a case where a floating conducting region is placed between a peripheral impurity region of a common input terminal pad and a resistor in a switch circuit device, it is possible to suppress the leakage of high-frequency signals from an input terminal to control terminals which become high frequency GND and to suppress an increase in insertion loss.

Abstract: Techniques that enable the transitioning of high frequency signals on a printed wiring board processed in accordance with industry standards (such as the IPC specifications) are disclosed. One embodiment provides a high frequency via structure for a printed wiring board, where the via structure includes a via pad configured in accordance with IPC standards. A printed microwave transmission line having an inductive section is connected to the via pad, wherein the inductive section has dimensions to compensate for transition discontinuity.

Abstract: A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial oxide layer is exposed; (c) etching the exposed sacrificial oxide layer within the first region, thereby forming a first etched region; (d) growing a first oxide layer (211) within the first etched region; (e) depositing and patterning a second layer of photoresist (213) on the sacrificial oxide layer and first oxide layer, thereby forming a second region in which the sacrificial oxide layer is exposed; (f) etching the exposed sacrificial oxide layer within the second region, thereby forming a second etched region; and (g) growing a second oxide layer (215) within the second etched region.

Abstract: A high frequency switch, has a transmitting terminal, a receiving terminal, an antenna terminal, a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal, a second diode having an anode connected through a transmission line of ¼ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded, and a control terminal provided to a node between the transmitting terminal and the first anode. The first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.

Abstract: Disclosed are methods and circuit configurations for reference frequency signal distribution circuitry that suppress unwanted spurious components introduced by way of RF signal leakage. The methods and circuitry may include relocating components of a buffer along a reference frequency signal path, thereby suppressing conductive and inductive components associated with RF leakage paths entering the circuitry. A filter also may be used after the buffer to suppress spurious components resulting from subsampling of unwanted tones in a phase frequency detector or intermodulation between the reference signal and interference tones in the signal-path of the buffer.

Abstract: An amplifier GaAs MMIC for microwave band applications includes a ground electrode 8 having a via hole group 12 composed of three via holes 11 filled with plated metals 10a that are formed adjacently. The interaction thereby generates high frequency electromagnetic bonding, which reduces the ground inductance. According to the MMIC, the ground inductance of the via hole may be reduced while decrease of a strength and increase of a size being restrained.

Abstract: A structure and method of manufacturing a CMOS device where the Coplanar wave guide (CPW) lines are formed above the top metal lines. Also other insulating layers are provided that reduce the e-field from the signal line to the substrate. There are four embodiments. In the first embodiment, the following layers are formed over the semiconductor structure: the passivation layer, a shielding layer, a first insulator layer, a high K dielectric layer, a CPW and a second insulator layer. In the second embodiment, no shielding layer is used and the high k dielectric layer is thicker than in the first embodiment. In the third embodiment, a thick shielding layer is used and no high k dielectric layer. In the fourth embodiment, the top metal layer is used as a shielding layer and no high k dielectric layer is used.

Abstract: The structure of the nonvolatile memory includes a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.

Abstract: The present invention provides a multi-layer substrate structure for reducing layout area, including a first core layer, a second core layer, and a set of coupled transmission line. The first core layer includes a first surface connected to a power supply layer and a second surface corresponding to the first surface. The second core layer includes a third surface connected to a first grounding layer and a fourth surface corresponding to the third surface. The set of coupled transmission lines includes a plurality of first differential signal lines formed on the second surface with a certain line width and a plurality of second differential signal lines formed on the fourth surface with a line width corresponding to the first differential signal lines. The second surface and the fourth surface are connected to a first dielectric layer making the second surface separated from the fourth surface with an appropriated distance.

Abstract: A programmable logic controller has a wireless communication interface. A radio frequency identification chip set is mounted to, and is in communication with, the active elements of an integrated circuit on one or more circuit boards in the programmable controller. The chip set provides for radio frequency communication between the controller and other components either inside the controller or external to the controller. Identification information recorded on the chip may be interfaced over a network, particularly, an on-line network such as the Internet.

Abstract: A programmable integrated circuit (IC) arrangement includes at least one input/output terminal, at least two receiver/source terminals for selectable electrical connection to the at least one input/output terminal, and a plurality of layers electrically interconnected with one another and providing electrical connection between the at least one input/output terminal and at least one of the at least two receiver/source terminals. At least a sub-plurality of the plurality of layers includes electrically conductive components selectably providable at at least two positions so as to selectably program electrical connection between the at least one input/output terminal and the at least two receiver/source terminals. The selectably providable electrically conductive components include ones of selectably providable vias, switch-contacts and well regions. The plurality of layers can include many different types and constructions.