Abstract: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.

Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.

Abstract: A method of fabricating a semiconductor device includes forming a first interlayer insulating film including a storage node contact plug over a semiconductor substrate. A second interlayer insulating film is formed over the first interlayer insulating film and the storage node contact plug. A mask pattern is formed over the second interlayer insulating film to expose a storage node region. The second interlayer insulating film and the first interlayer insulating film is selectively etched to form a recess exposing a portion of the storage node contact plug. A lower storage node is formed in the recess. The storage node includes a concave structure that surrounds the exposed storage node contact plug. A dip-out process is performed to remove the second interlayer insulating film. A dielectric film is formed over the semiconductor substrate including the lower storage node. A plate electrode is deposited over the dielectric film to form a capacitor.

Abstract: In a semiconductor device, a plurality of triple-stacked structures all having the same structure are provided. Each of the triple-stacked structures includes one lower electrode layer, at least one upper electrode layer and one dielectric layer sandwiched by the lower electrode layer and the upper electrode layer.

Abstract: There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract: An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory.

Abstract: Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.

Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

Abstract: A semiconductor device includes a memory cell array region including a plurality of memory cells, an annular groove surrounding the memory cell array region, a protective insulating film covering the inner wall of the annular groove, and a conductor filling the annular groove.

Abstract: Embodiments relate to a capacitor having a high capacitance, a semiconductor device having the same, and a method for manufacturing the semiconductor device. In embodiments, the capacitor may include a lower electrode having a predetermined pattern, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer.

Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device.

Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

Abstract: Disclosed are an asymmetric recessed gate MOSFET, and a method for manufacturing the same. The asymmetric recessed gate MOSFET comprises: recess regions formed at a predetermined depth in a semiconductor; recessed gate electrodes formed at a predetermined height on a semiconductor substrate by gap-filling the recess regions, and misaligned with the recess region corresponding to one of the source/drain regions; spacers formed on sides of the recessed gate electrodes; and source/drain regions implanted with a dopant formed in the semiconductor substrate exposed between the spacers. The overlap between the gate electrodes and the source/drain regions can be reduced by having one of the source/drain regions misaligned with the recess regions in the recessed gate structure, and abnormal leakage current caused by consistency between an electron field max point A and a stress max pint B can be sharply reduced by changing the profile of the source/drain regions.

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine the electric fields between the limits of the shields.

Abstract: Dynamic random access memory (DRAM) devices include first node pads and second node pads alternately arranged in a first direction on a substrate to form a first pad column. A width of the second node pads in a second direction, perpendicular to the first direction, is greater than a width of the first node pads in the second direction. Storage electrodes are electrically connected to the first node pads and the second node pads. Bit line pads may be arranged in the first direction on the substrate to form a second pad column. The second pad column is adjacent the first pad column and displaced therefrom in the second direction.

Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

Abstract: A high surface area capacitor structure includes a storage electrode with recesses. An upper surface of the storage electrode has a maze-like appearance. Low elevation regions of a hemispherical grain polysilicon layer may remain on the upper surface of the storage electrode. The storage electrode or portions thereof may be lined or coated with dielectric material. The dielectric material may space a cell electrode of the high surface area capacitor structure apart from the storage electrode. One or both of the storage electrode and the cell electrode may be formed from polysilicon. Intermediate structures, which include mask material over contiguous low elevation regions of a layer of hemispherical grain polysilicon, which may have a maze-like appearance, and apertures located laterally between the low elevation regions of the layer of hemispherical grain polysilicon, are also disclosed.

Abstract: A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the annular shaped conductive spacer is disposed on the etching stop layer and wherein the annular shaped conductive spacer and the conductive layer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal.

Abstract: A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO2) layers and at least one tetragonal structure material layer. The tetragonal structure material layer is disposed between two titanium oxide layers and each tetragonal structure material layer has the same or a different thickness. Leakage path can be cut off through the tetragonal material layer between the titanium oxide layers. In the meantime, the tetragonal structure material layer can induce the titanium oxide layers to transform into a high k rutile phase.

Abstract: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.

Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.

Abstract: A ferroelectric memory device includes a top electrode, a bottom electrode, a ferroelectric film which is sandwiched between the top and bottom electrodes, includes a first portion having a side surface flushed with a side surface of the top electrode and a second portion having a side surface flushed with a side surface of the bottom electrode, and has a step formed by making the side surface of the second portion project outward from the side surface of the first portion, a top mask which is provided on the top electrode, and a side mask which is provided on part of a side surface of the top mask, the side surfaces of the top electrode and the first portion of the ferroelectric film and has a top at a lower level than a top of the top mask and at a higher level than a top of the top electrode.

Abstract: A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.

Abstract: A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.

Abstract: A semiconductor device of the present invention includes a plurality of lower electrodes covering the entire surfaces of a plurality of trenches formed in a first interlayer insulating film, a capacitive insulating film covering the entire surfaces of the plurality of lower electrodes, and an upper electrode covering the surfaces of the plurality of lower electrodes from above with the capacitive insulating film interposed between the upper electrode and the plurality of lower electrodes. The upper electrode is formed with a stress-relieving part, such as a crack, a notch or a recess.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Abstract: Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer.

Abstract: A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns.

Abstract: A first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and a second capacitor is formed on the substrate and connected to a second differential node of the differential circuit. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate.

Abstract: A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12? containing Pb and having a plane (111) 11 in parallel with the surface of the substrate (or a ferroelectric polycrystalline thin film containing Pb and oriented parallel with the plane (111) in parallel with the surface of the substrate) and part 16 of a circuit of a semiconductor device, to thereby fabricate the single crystalline substrate 10 having said ferroelectric thin film containing Pb and said part of the circuit of the semiconductor device; and bonding said single crystalline substrate 10 to another substrate on which the other circuit of the semiconductor device has been formed in advance, to couple the two circuits together.

Abstract: DRAM cell arrays having a cell area of about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A semiconductor memory device includes: a MOS transistor; a bit line provided above a memory region, and electrically connected to an impurity diffusion layer; a capacitor which has a capacitive insulating film including a ferroelectric material or a high-k material, and is provided at a position higher than that of the bit line; a lower hydrogen barrier film which covers a lower side of the capacitor; an upper hydrogen barrier film which covers lateral and upper sides of the capacitor; an interconnect formed above a peripheral circuit region; and a conductive layer which is formed at a position lower than that of the bit line, and extends from the memory region to the peripheral circuit region when viewed from above, for electrically connecting the bit line and the interconnect to each other.

Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

Abstract: A capacitor can prevent a problem of step coverage in semiconductor device, caused by a thickness of an insulator film and an upper metal film included a metal-insulator-metal (MIM) capacitor, between the MIM capacitor region and its circumferential region. A capacitor in a semiconductor device includes a first metal film provided with a recess having a predetermined depth over a semiconductor substrate. An insulator film and a second metal film may be formed in the recess with a thickness corresponding to a depth of the recess. The insulator and second metal films are disconnected from an inner lateral side of the recess. A dielectric film including a plurality of plugs is in contact with the first and second metal films and the insulator film. A plurality of metal electrodes is in contact with the plugs over the dielectric film.

Abstract: A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

Abstract: A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an upper surface and a lower surface. The device has a container structure within a portion of the interlayer dielectric region. The container structure extends from the upper surface to the lower surface. The container structure has a first width at the upper surface and a second width at the lower surface. The container structure has an inner region extending from the upper surface to the lower surface. In a specific embodiment, the container structure has a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.

Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Abstract: The capacitance of a capacitor is adjusted by forming openings in one of a pair of electrodes of the capacitor, the openings having different sizes d1, d2, d3, . . . , wherein d1>d2>d3> . . . and being arranged in numbers n1, n2, n3, . . . , respectively; and sequentially filling a necessary number of the openings with an electroconductive material in descending order of the size so as to adjust the capacitance gradually with an increasing degree of precision. The resulting capacitor is mounted to a printed wiring board.

Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.

Abstract: A first DRAM section including a first memory cell having a first capacitance and a second DRAM section including a second memory cell having a second capacitance different from the first capacitance are provided on the same semiconductor substrate.

Abstract: A dynamic random access memory (DRAM) structure has a stacked capacitor disposed above an upper source/drain region of a vertical transistor having a surrounding gate. The gates of each row of a memory array are electrically connected with a buried word line. Each of bit lines is disposed between two adjacent columns of transistors and electrically connected with lower source/drain regions through bit line contacts. The DRAM structure may have a unit cell size of 4F2.

Abstract: In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section.