Abstract: The present disclosure provides methods to fabricate a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.

Abstract: A manufacturing method of capacitor lower electrode of the instant disclosure comprises the steps of: providing a semiconductor substrate; forming a sacrificial laminate on the semiconductor substrate; forming a plurality of capacitor trenches in the sacrificial laminate; forming a plurality of lower electrode structures in the capacitor trenches respectively; etching back the sacrificial laminate to a desired thickness to expose an upper portion of each of the lower electrode structures; forming a liner layer to conformally cover the sacrificial laminate and the upper portions of the lower electrode structures; patterning the liner layer to form an insulating spacer on the sidewalls of each of the upper portions, wherein two adjacent insulating spacers are configured to have a self-aligned opening positioned therebetween; and performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings.

Abstract: A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.

Abstract: Embodiments described herein provide a structure for finger capacitors, and more specifically metal-oxide-metal (“MOM”) finger capacitors and arrays of finger capacitors. A plurality of Shallow Trench Isolation (STI) formations is associated with every other column of capacitor fingers, with poly fill formations covering the STI formations to provide a more robust and efficient structure.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug.

Abstract: A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive effect element provided in a memory cell, the magnetoresistive effect element including a multilayer structure including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a first electrode provided on an upper portion of the multilayer structure and including a first material, and a first film provided on a side surface of the first electrode and including a second material which is different from the first material of the first electrode.

Abstract: A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.

Abstract: A planar interdigitated capacitor structure, methods of forming, and devices including, the same. The device includes first and second planar electrode structures including respective first and second pluralities of planar continuous rectangular plate electrode elements formed above a semiconductor substrate and extending continuously in first and second orthogonal directions substantially parallel to a plane of the substrate, and first and second conductors interconnecting the respective first and second pluralities of planar electrode elements parallel to a third axis substantially normal to the plane of the substrate. The first and second planar electrode structures are arranged with respective continuous rectangular plate electrode elements of each planar electrode structure interleaved and substantially parallel with each other between the first and second conductors. The device also includes a dielectric material between the first planar electrode structure and the second planar electrode structure.

Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.

Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.

Abstract: A capacitor includes: dielectric layers including a first dielectric layer, a second dielectric layer, and at least one intermediate dielectric layer laminated between the first dielectric layer and the second dielectric layer; first interlayer electrode and second interlayer electrode arranged alternately with each other between at least two layers among the dielectric layers; a first external electrode disposed on lateral surfaces of the dielectric layers and coupled to the first interlayer electrode; and a second external electrode disposed on lateral surfaces of the dielectric layers and coupled to the second interlayer electrode, wherein the intermediate dielectric layer includes first internal electrodes coupled to the first interlayer electrode, arranged in a plane direction of the intermediate dielectric layer and spaced apart from each other, and second internal electrodes coupled to the second interlayer electrode, arranged alternately with the first internal electrodes and spaced apart from the fir

Abstract: A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less than lower end portion thereof, the lower end portion contacting the upper end portion of the first plug; a second insulating film above the first insulating film and the first plug and covering the second plug; a wiring layer including a lower end portion contacting the upper end portion of the second plug; and a third insulating film above the second insulating film and the second plug and covering the wiring layer; wherein the upper end portion of the first plug displaced from the lower end portion of the second plug has a step.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.

Abstract: A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Abstract: A semiconductor device includes an active region on a semiconductor substrate. The active region is defined by a device isolation layer and includes gate-recesses. The semiconductor device further includes gate electrodes in the gate-recesses, a contact recess in the active region between the gate-recesses, a cell pad that covers at least a portion of the active region between the gate-recesses and that fills at least a portion of the contact recess, and a bit line electrically connected to the cell pad.

Abstract: Disclosed are semiconductor devices and methods of forming the same. According to the semiconductor device, gate structures are provided to be buried in a substrate and first dopant regions and second dopant regions are provided at both ends of the gate structures. Conductive lines cross the gate structures and are connected to the first dopant regions. Contact structures are respectively provided in contact holes which are provided between the conductive lines and expose the second dopant regions. The contact structures are in contact with the second dopant regions, respectively. Each of the contact structures includes a pad pattern extending along a sidewall of the contact hole.

Abstract: A method of forming semiconductor device includes forming a landing pad, forming a stopping insulating layer on the landing pad, forming a lower molding layer including a first material on the stopping insulating layer, forming an upper molding layer including a second material different from the first material on the lower molding layer, forming a hole vertically passing through the upper molding layer and the lower molding layer and exposing the landing pad, forming a first electrode in the hole, removing the upper molding layer to expose a part of a surface of the first electrode, removing the lower molding layer to expose another part of the surface of the first electrode, forming a capacitor dielectric layer on the exposed parts of the surface of the first electrode, and forming a second electrode on the dielectric layer.

Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

Abstract: A method of fabricating a semiconductor device includes forming an etch-target layer on a substrate having an alignment key, forming a transparent first pattern on the etch-target layer to face the alignment key, forming an opaque second pattern on the etch-target layer to be adjacent to the first pattern, and etching the etch-target layer using the first pattern and the second pattern as an etch mask.

Abstract: A method for fabricating a semiconductor device includes forming a metal layer over a substrate, forming a capping layer over the metal layer, and densifying the metal layer through a heat treatment.

Abstract: A capacitor structure comprising semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other, an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure, and insulative material separating the interior and exterior structures. The structure also comprises a switching mechanism included in the capacitor structure to switch between ones of the plural capacitor units.

Abstract: A resistive random access memory includes a first electrode, a second electrode and a first metal oxide composite layer. The second electrode is opposite to the first electrode. The first metal oxide composite layer is disposed between the first electrode and the second electrode. The first metal oxide composite layer has a film layer and a nanorod structure.

Abstract: A capacitor suitable for inclusion in a semiconductor device includes a substrate, a first metallization level, a capacitor dielectric, a capacitor plate, an interlevel dielectric layer, and a second metallization level. The first metallization level overlies the substrate and includes a first metallization plate overlying a capacitor region of the substrate. The capacitor dielectric overlies the first metallization plate and includes a dielectric material such as a silicon oxide or silicon nitride compound. The capacitor plate is an electrically conductive structure that overlies the capacitor dielectric. The interlevel dielectric overlies the capacitor plate. The second metallization layer overlies the interlevel dielectric layer and may include a second metallization plate and a routing element. The routing element may be electrically connected to the capacitor plate. The metallization plates may include a fingered structure that includes a plurality of elongated elements extending from a cross bar.

Abstract: A semiconductor device and a method of fabricating the same, the device including a substrate having a transistor formed thereon; a plurality of lower electrodes formed on the substrate; a first supporter and a second supporter on the plurality of lower electrodes; a dielectric film formed on the lower electrode, the first supporter, and the second supporter; and an upper electrode formed on the dielectric film, wherein the first and second supporters are positioned between the lower electrodes, and the first and second supporters include a first material and a second material.

Abstract: A semiconductor structure may implement a metal-oxide-metal capacitor. When layer design rules change from one layer to the next, the structure may change the direction of the interleaved plates of the capacitor. For example, when the metallization width or spacing design rules change from layer M3 to layer M4, the structure may run the capacitor traces in different directions (e.g., orthogonal to one another) on M3 as compared to M4. Among the layers that adhere to the same design rules, for example layers M1, M2, and M3, the structure may run the capacitor traces in the same direction in each of the layers M1, M2, and M3. In this way, the capacitor traces overlap to large extent without misalignment on layers that have the same design rules, and the structure avoids misalignment of the capacitor traces when the design rules change.

Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract: An integrated Microelectromechanical Systems (“MEMS”) device (100). The MEMS device comprises a substrate (200, 300), a transition portion (118), and a differential inductor (1000, 1100, 1300). The transition portion is connected to and at least partially extends transversely away from a major surface of the substrate. The differential inductor is mechanically suspended above a major surface of the substrate at least partially by the transition portion. The differential inductor is also electrically connected to an electronic circuit external thereto by the transition portion. A first dielectric gap exists between the major surface of the substrate and the differential inductor.

Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.

Abstract: Embodiments of the present invention relate to systems and methods for designing and manufacturing hard masks used in the creation of patterned magnetic media and, more particularly, patterned magnetic recording media used in hard disk drives (e.g., bit patterned media (BPM)). In some embodiments, the hard mask incorporates at least one layer of Ta (tantalum) and at least one layer of C (carbon) and is used during ion implantation of a pattern onto magnetic media. The hard mask can be fabricated with a high aspect ratio to achieve small feature sizes while maintaining its effectiveness as a mask, is robust enough to withstand the ion implantation process, and can be removed after the ion implantation process with minimal damage to the magnetic media.

Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A via-hole region is employed to enclose the metal-oxide-metal capacitor so as to remove the moisture stored in the low k dielectric material.

Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate; a memory capacitor; and a first compensation capacitor. The semiconductor substrate has at least first and second regions. The memory capacitor is positioned over the first region. The memory capacitor may include, but is not limited to: a first lower electrode; and a first dielectric film covering inner and outer surfaces of the first lower electrode. The first compensation capacitor is positioned over the second region. The first compensation capacitor includes, but is not limited to: a second lower electrode; a second dielectric film covering an inner surface of the second lower electrode; and a first insulating film covering an outer surface of the second lower electrode.

Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.

Abstract: According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.

Abstract: Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The semiconductor substrate also includes a conductive contact formed in the first dielectric material, the conductive contact being electrically connected to the doped region, and a dielectric cap overlying the conductive contact.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Abstract: A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.

Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.

Abstract: A thin film transistor (TFT) array substrate is provided that includes a TFT on a substrate. The TFT can include an active layer, gate electrode, source electrode, drain electrode, first insulating layer between the active layer and the gate electrode, and second insulating layer between the gate electrode and the source and drain electrodes. A pixel electrode is disposed on the first and second insulating layers. A capacitor including a lower electrode is disposed on a same layer as the gate electrode and an upper electrode. A third insulating layer directly between the second insulating layer and the pixel electrode and between the lower electrode and the upper electrode. A fourth insulating layer covers the source electrode, the drain electrode, and the upper electrode, and exposes the pixel electrode and can further expose a pad electrode.

Abstract: A nonvolatile memory element which inhibits deterioration of an oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element are provided. The nonvolatile memory element includes a first electrode layer formed above a substrate, a variable resistance layer disposed on the first electrode layer, and a second electrode layer disposed on the variable resistance layer, and the variable resistance layer has a two-layer structure in which an oxygen- and/or nitrogen-deficient tantalum oxynitride layer and a tantalum oxide layer are stacked.

Abstract: The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound.

Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.

Abstract: A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.