Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

Abstract: A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

Abstract: The present invention relates to a method for manufacturing a semiconductor device, and provides to reduce a contact resistance of a landing plug by forming the landing plug in such a manner that a polysilicon layer is deposited only on the surface of a landing plug contact hole, and a metal layer is buried in the rest of the landing plug contact hole in the process of forming a storage node contact or a bit line contact.

Abstract: Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to substantially eliminate the micro-trench.

Abstract: A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.

Abstract: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.

Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.

Abstract: A vertical transistor structure includes a substrate, a plurality of pillars located on the substrate and spaced from each other at a selected distance, a gate line and a plurality of conductors. The pillars are aligned in a straight line in a first direction and have respectively a primary control wall along the first direction and two ancillary control walls perpendicular to the primary control wall. The gate line is connected to the primary control wall in the first direction through a first isolated layer. The conductors are interposed between the ancillary control walls through second isolated layers. By providing the gate line merely on the primary control wall and the conductors to aid the gate line to control ON/OFF of the pillars, problems of etching and separating gate material during gradually shrunken feature size process that are difficult to control etching positions and etching duration can be prevented.

Abstract: A pixel structure including a first scan line, a second scan line, a data line and a power line substantially perpendicular to the first scan line and the second scan line, a reference signal line and an emission signal line substantially parallel with the first scan line and the second scan line, a common thin film transistor (C-TFT), a first pixel unit, and a second pixel unit is provided. The common thin film transistor has a common gate electrode, a common source electrode and a common drain electrode. The common gate electrode is electrically connected to the first scan line, the common drain electrode is electrically connected to the reference signal line. The first and the second pixel units respectively have a first TFT, a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a capacitor, and an emission device.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

Abstract: Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and forming fins form the elliptical bases. The transistors are formed within the fin such that they may be used as access devices in a memory array.

Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.

Abstract: Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

Abstract: Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors.

Abstract: A semiconductor device and a method for fabricating the same are provided to enable a bit line to be formed easily, increase a bit line process margin and reduce capacitance between the adjacent bit lines. The semiconductor device comprises: a first pillar and a second pillar each extended vertically from a semiconductor substrate and including a vertical channel region; a first bit line located in the lower portion of the vertical channel region inside the first pillar and the second pillar; and an interlayer insulating film located between the first pillar and the second pillar that include the first bit line.

Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Abstract: A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (12) and a plurality of data signal lines (11) intersecting perpendicularly to each other on a glass substrate (1), and each of the thin film capacitor parts has a lower electrode (3), a gate insulating film, and an upper electrode (5), which are provided in this order. Adjacent upper electrodes (5) are electrically connected to each other via a corresponding first wire (8), which is positioned above the adjacent upper electrodes (5) and intersects with one of the data signal lines (11). This makes it possible to provide a thin film capacitor, which includes the lower electrodes (3) each having the same thickness in a center portion and an edge portion, and the upper electrodes (5) that are connected to each other by using a corresponding connecting wire with low possibility of disconnection.

Abstract: According to example embodiments, a semiconductor device includes a lower active portion protruding from a substrate, an active pillar protruding from the lower active portion, a surround gate electrode surrounding the active pillar, a buried bit line extending along a first direction and being on the lower active portion and electrically connected to the lower active portion, and a contact gate electrode contacting both the surround gate electrode and a word line extending a second direction crossing the first direction.

Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.

Abstract: A thin film transistor device, disposed on a substrate, includes a gate electrode, a semiconductor channel layer, a gate insulating layer disposed between the gate electrode and the semiconductor channel layer, a source electrode and a drain electrode disposed at two opposite sides of the semiconductor channel layer and partially overlapping the semiconductor channel layer, respectively, a capacitor electrode at least partially overlapping the gate electrode, and a capacitor dielectric layer disposed between the capacitor electrode and the gate electrode. The capacitor electrode, the gate electrode and the capacitor dielectric layer form a capacitor device.

Abstract: A fabricating method of a semiconductor device is provided. Pillars are formed on a substrate. A first oxide layer is continuously formed on upper surfaces and side walls of the pillars by non-conformal liner atomic layer deposition. The first oxide layer continuously covers the pillars and has at least one first opening. The first oxide layer is partially removed to expose the upper surfaces of the pillars, and a first supporting element is formed on the side wall of each of the pillars. The first supporting element is located at a first height on the side wall of the corresponding pillar and surrounds the periphery of the corresponding pillar. The first supporting elements around two adjacent pillars are connected and the first supporting elements around two opposite pillars do not mutually come into contact and have a second opening therebetween.

Abstract: A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the active regions of the semiconductor device, a plurality of bit lines extending on the semiconductor substrate along a first direction, a plurality of insulating patterns extending on the semiconductor substrate along a second direction that crosses the first direction, and a plurality of capping patterns extending over the bit lines, wherein the insulating patterns and the capping pattern both include insulating material and at least a portion of corresponding ones of the insulating patterns and the capping patterns are in direct contact with each other.

Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

Abstract: A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.

Abstract: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.

Abstract: A method for manufacturing a capacitor on an integrated circuit includes providing an inter-metal dielectric layer on a substrate, a bottom layer having a first and second portions, a first insulating layer having via plug openings on the bottom layer, and via plugs disposed in the via plug openings. The via plugs include a first and second via plugs and are electrically coupled to the first portion of the bottom layer. The method further includes providing a capacitor layer having a first barrier metal layer coupled to the first via plug. The capacitor layer also has a capacitor dielectric layer overlying the first barrier metal layer and a second barrier metal overlying the capacitor dielectric layer. The method further includes defining a first and second capacitor layer portions. The first capacitor layer portion has two opposite sides and spacers disposed on their surface.

Abstract: A semiconductor device may include, but is not limited to a first electrode upwardly extending, and a second electrode upwardly extending along the first electrode. The first electrode includes a lower portion and an upper portion. The second electrode covers a bottom surface and an outer side surface of the lower portion of the first electrode. The upper portion of the first electrode is positioned higher than the second electrode.

Abstract: The present invention is a method for producing a capacitor. The method includes applying a dielectric substance (ex.—silicon nitride) to a first gold seed layer, the first gold seed layer being formed on a wafer. A second gold seed layer is formed upon the dielectric substance and first gold seed layer. Gold is electroplated into a photoresist to form a first set of 3-D capacitor elements on the second gold seed layer. A first copper layer is electroplated onto the second gold seed layer. Gold is electroplated into a photoresist to form a second set of 3-D capacitor elements, the second set of 3-D elements being formed at least partially within the first copper layer and being connected to the first set of 3-D elements. A second copper layer is electroplated onto the first copper layer. Then, both copper layers are removed to provide (ex.—form) the capacitor.

Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Abstract: A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.

Abstract: A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.

Abstract: Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode.

Abstract: A method for manufacturing semiconductor device includes forming an interlayer dielectric layer including a contact plug defined therein to electrically couple a semiconductor substrate on which a cell region and a dummy region are defined. A sacrificial layer is formed over the interlayer dielectric layer. An etch stop pattern is formed over the sacrificial layer, the etch stop pattern being vertically aligned to the dummy region. A storage electrode region through the sacrificial layer is defined to expose a first storage electrode contact of the cell region, the second storage electrode contact of the dummy region remaining covered by the sacrificial layer. A conductive layer is deposited within the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.

Abstract: Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1?x): x (0.01?x?0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a base material, a first metal layer, a first dielectric layer, a first upper electrode and a first protective layer. The first metal layer is disposed on a first surface of the base material, and includes a first inductor and a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first inductor and the first capacitor. Whereby, the first inductor and the first lower electrode of the first capacitor are disposed on the same layer, so that the thickness of the product is reduced.

Abstract: A three-dimensional dynamic random access memory with an ancillary electrode structure includes a substrate, at least one bit line formed on the substrate, at least one pillar element formed on a growth zone of the bit line, an ancillary electrode, a character line parallel with the substrate and perpendicular to the bit line, and at least one capacitor connecting to the pillar element. The bit line is formed on the substrate by doping and diffusing a doping element. The ancillary electrode is located on a separation zone of the bit line and adjacent to the pillar element. The character line is insulated from the ancillary electrode and incorporates with the bit line to output or input electronic data to the capacitor. Through the ancillary electrode, impedance of the bit line can be controlled to enhance conductivity of the bit line.

Abstract: A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

Abstract: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first ferroelectric film by a sputtering method; forming a second conductive film on the second ferroelectric film; and forming a capacitor provided with a lower electrode, a capacitor dielectric film and an upper electrode by patterning the first conductive film, the first and second ferroelectric films and the second conductive film.

Abstract: The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.

Abstract: A layout of a semiconductor device is disclosed, which forms one transistor in one active region to reduce the number of occurrences of a bridge encountered between neighboring layers, thereby improving characteristics of the semiconductor device. Specifically, the landing plug connected to the bit line contact is reduced in size, so that a process margin of word lines is increased to increase a channel length, thereby reducing the number of occurrences of a bridge encountered between the landing plug and the word line.

Abstract: A semiconductor device includes a semiconductor substrate having an active region and an isolation region. A gate structure is provided on the semiconductor device. First and second impurity regions are provided in the substrate on both sides of the gate structure. A pad electrode is provided to contact the first impurity region. Because the pad electrode is provided on the first impurity region of the semiconductor device, the contact plug does not directly contact the active region. Accordingly, failures caused by damage to the active region may be prevented.

Abstract: Provided are a semiconductor device capable of increasing an ON current with a reduced channel resistance, and also capable of stably and independently operating respective transistors, and a method of manufacturing the semiconductor device. A semiconductor device includes a fin portion located in a manner that a part of an active region protrudes from a bottom portion of a gate groove, a gate insulating film for covering the gate groove and a surface of the fin portion, a gate electrode which is embedded within a lower portion of the gate groove and formed so as to straddle the fin portion via the gate insulating film, a first diffusion region, a second diffusion region, and a carrier capture region provided in the surface of the fin portion.

Abstract: According to one embodiment, a capacitor includes a substrate, a first electrode, a second electrode, and a first dielectric portion. The substrate includes an insulating layer and a semiconductor layer provided on the insulating layer. The semiconductor layer includes a dummy active region electrically isolated from an active region including an active element. The first electrode and the second electrode are located to oppose each other above the dummy active region. The first dielectric portion is provided between the first electrode and the second electrode.

Abstract: The method includes the steps of forming an upper electrode of a capacitor by patterning a second conductive film; forming a capacitor dielectric film by patterning a ferroelectric film; and forming a lower electrode by patterning a first conductive film. A step of forming the first conductive film includes the steps of forming a lower conductive layer made of a noble metal other than iridium over a first interlayer insulating film; and forming an upper conductive layer made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.

Abstract: A semiconductor device includes: an isolation layer for defining a plurality of active areas of a substrate, where the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces that are lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces that are lower than the upper surfaces of the plurality of buried word lines and extending parallel to the main surface of the substrate in a second direction that differs from the first direction.