Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract: A semiconductor device capable of preventing an electrostatic surge without increasing a leak current. In the semiconductor device, a protection circuit for protecting an internal circuit is provided between a source line and a ground line. The protection circuit has a protection transistor of which the drain is connected to the source line and the source and gate are connected to the ground line. The protection transistor is configured by integrally forming two types of transistor structural portions. The latter of the transistor structural portions is longer than the former thereof in gate length. In addition, the sum of gate widths of the latter transistor structural portions is larger than the sum of gate widths of the former transistor structural portions.

Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

Abstract: A semiconductor apparatus having an outer ESD protective circuit corresponding to each external connection terminal, the outer ESD protective circuit being formed in a peripheral region around the external connection terminals. The outer ESD protective circuit discharges electrostatic voltage from the external connection terminal and avoids the damaging of an internal circuit of the semiconductor apparatus. Accordingly, the ESD withstanding voltage of the semiconductor apparatus is improved.

Abstract: An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.

Abstract: A diode disposed on a substrate is provided. The diode includes a semiconductor pattern, a first conductor pattern, a second conductor pattern, an insulating layer, and a top conductor pattern. The first conductor pattern and the second conductor pattern are respectively disposed on a portion of the semiconductor pattern. The insulating layer is disposed on the first conductor layer, the second conductor layer, and the semiconductor pattern. Moreover, the top conductor pattern is disposed on the insulating layer above the semiconductor pattern and electrically connected to the first conductor pattern. In the diode mentioned above, no circuit belonging to the diode is disposed under the semiconductor pattern. Therefore, when the aforementioned diode and other devices are integrated, layout of the devices can adopt the space under the diode.

Abstract: A semiconductor device comprises: a MOS transistor including: a semiconductor substrate; a source region, formed in the semiconductor substrate, that comprises an impurity of a first conductive type; a drain region, formed in the semiconductor substrate, that comprises an impurity of the first conductive type; and a gate electrode, formed through a gate insulating film on the semiconductor substrate, between the source region and the drain region; an impurity region of the first conductive type formed in the semiconductor substrate; an impurity region of a second conductive type to be opposite to the first conductive type formed in the semiconductor substrate; and a wiring provided to connect each of the impurity region of the first conductive type and the impurity region of the second conductive type to the gate electrode.

Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.

Abstract: An ESP protecting circuit and a manufacturing method thereof are provided. The ESP protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.

Abstract: A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust a breakdown voltage of an ESD protection device which is fabricated in the same process as that for an internal device without varying basic performance of the internal device even at a final stage of an LSI manufacturing process.

Abstract: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer.

Abstract: In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is produced in the transistor-formation region, and features a multi-finger structure including a plurality of fingers. A guard-ring is formed in the well region so as to surround the transistor-formation region, and a well blocking region is formed in the well region between the transistor-formation area and the guard-ring. A substrate resistance determination system is associated with the electrostatic discharge protection device to determine a substrate resistance distribution at the transistor-formation area such that snapbacks occur in all the fingers in a chain-reaction manner, and such that occurrence of a latch-up state is suppressed.

Abstract: The present invention provides a method and apparatus for providing electrostatic discharge (ESD) protection between a first and a second circuit node. One embodiment of the ESD protection circuit includes one or more steering diodes that generate electromagnetic radiation and couple the first circuit node to ground in response to a voltage applied to the first circuit node. The ESD protection circuit also includes a latch circuit that couples the first circuit node to ground in response to the electromagnetic radiation generated by the steering diode(s).

Abstract: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.

Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting a element across the respective source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. The method includes connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: An electrostatic discharge (“ESD”) protection circuit having dynamically configurable series-connected diodes and a method for manufacturing the ESD protection circuit. A doped region of P-type conductivity and a doped region of N-type conductivity are formed in an SOI layer of P-type conductivity, wherein the doped regions are laterally spaced apart by a portion of the SOI layer. At least one gate structure is formed on the SOI region that is between the N-type and P-type doped regions. During normal operation, a portion of the SOI region that is adjacent to and between the P-type and N-type doped regions is biased so that it becomes a region of N-type conductivity, thereby forming two series-connected diodes. During an ESD event, the bias is changed so that the region between the P-type and N-type doped regions becomes a region of P-type conductivity, thereby forming a single P-N junction diode.

Abstract: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

Abstract: An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

Abstract: A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.

Abstract: In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view.

Abstract: High-resistance elements are connected as parts of a control resistor between a switching element and a protecting element immediately near the switching element and between adjacent protecting elements. Paths for high-frequency signals are cut off, and high-frequency signals can be prevented from leaking although there are parasitic capacitances due to the protecting elements being connected. Accordingly, electrostatic breakdown voltage can be improved, and isolation can be prevented from deteriorating.

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capa citive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract: A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area, a second area adjacent to the first area, and a third area adjacent to the second area in each of the layers. The semiconductor layer, the insulating layer, and an upper portion of the bulk layer in the first area are removed to form the removal portion. A part of the bulk layer in the second area is removed to form the cavity adjacent to the removal portion. The first semiconductor element is formed in the bulk layer in the removal portion as an ESD protection element. The second semiconductor element is formed partially in the semiconductor layer in the second area.

Abstract: A layout structure for a CMOS circuit comprises a transistor layer forming P-type transistors 11 and 21 and N-type transistors 12 and 22, and a resistor layer which includes a resistor 13 formed to have a predetermined length and to make plural appropriate portions or the entire of the resistor along a direction of the length satisfy a mask rule necessary for providing VIAs, the resistor being connected to appropriate connecting portions of the P-type transistors and the N-type transistors through the VIAs by metal wires 31 formed of a metal layer, and the resistor having a predetermined circuit resistance which can be set based on the positions of the appropriate connecting portions.

Abstract: An electrostatic protection circuit includes a first impurity region, a second impurity region, a first electrode, a third impurity region, a fourth impurity region, a second electrode, a fifth impurity region, a sixth impurity region, a third electrode, a gate insulating film, and a fourth electrode.

Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

Abstract: In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as to be aligned in a second direction perpendicular to a first direction going from a collector region of the first conductivity type, which is formed so as to be spaced away from the base region, toward the base region. The width of the sense region, the width of the emitter region, the width of a part of the base region that is adjacent to the sense region, and the width of a part of the base region that is adjacent to the emitter region in the second direction are set in such a manner that a sense ratio varies in a desired manner in accordance with variation in collector current.

Abstract: A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning.

Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract: Disclosed is an ESD protection circuit, which includes: an ESD protection element, coupled to a pad; a transmitting gate circuit; an N MOSFET, for providing a first biasing voltage to the transmitting gate circuit according to the second voltage level; a first P MOSFET, for providing a second biasing voltage to the transmitting gate circuit according to the first voltage level; a delay circuit for determining the turning on and turning off time of the transmitting gate circuit; a first inversing logic circuit, for generating a first control signal according to the output of the delay circuit; and a second inversing logic circuit, for generating a second control signal according to the output of the first inversing logic circuit, wherein the transmitting gate circuit turns on or turns off according to the first control signal and the second control signal.

Abstract: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.

Abstract: To present a semiconductor device mounting ESD protective device appropriately applicable to transistors mutually different in dielectric strength, and its manufacturing method. The semiconductor device comprises a first ESD protective circuit 1A including a first transistor 3 and a first ballast resistance 4, and a second ESD protective circuit 1B including a second transistor 5 and a second ballast resistance 6. The impurity concentration of the second diffusion region forming the first ballast resistance 4 is set lower than the impurity concentration of the fourth diffusion region for forming the second ballast resistance 6.

Abstract: Provided is a semiconductor device, including: an N-type MOS transistor for an internal element and a P-type MOS transistor for an internal element both provided in an internal circuit region; and an N-type MOS transistor for ESD protection provided between an external connection terminal and the internal circuit region, in which a gate electrode of the N-type MOS transistor for ESD protection is formed of P-type polysilicon.

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: A protection element comprises a ring-shape gate electrode, an N+ drain region inside the ring-shape gate electrode, an N+ source region outside, and a shield plate electrode. The ring gate and source regions are connected to ground via a through-hole, and the drain region is connected to an external pad. The shield plate electrode is connected to ground or to a power supply. Element isolation is achieved by the shield plate electrode, without forming a LOCOS or other element isolation oxide layer. By this means, blocking of thermal conduction by an oxide layer can be avoided to improve the heat dissipation and ESD resistance of the protection element.

Abstract: A thin film transistor array, an electrostatic discharge protective device thereof, and methods for fabricating the same are provided. The thin film transistor array comprises a plurality of scan lines, a plurality of data lines, a first shorting bar, and a second shorting bar. The electrostatic discharge protective device comprises a switching device and a resistance line in parallel. If static electricity accumulated on the TFT array is over a predetermined range, the accumulated static electricity will be conducted to the first or second shorting bar via the switching device. The resistance line can prevent signals applied to one of the scan lines or data lines from being conducted to other scan lines or data lines, to detect a defective pixel.

Abstract: Disclosed is a circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting an element across the source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.

Abstract: A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

Abstract: An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to Vcc if it is turned on.

Abstract: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

Abstract: A Field-Effect Transistor (FET) is provided that includes a first portion and a second portion separated from the first portion by a gap. The FET further includes at least one diode embedded within the gap between the first and second portions.

Abstract: A circuit board includes a transparent circuit substrate, at least one die and at least one electrostatic discharge (ESD) protection circuit. The transparent circuit substrate has a patterned conducting layer. The die is disposed on the transparent circuit substrate and has at least one input/output (I/O) electrical connecting pad. The ESD protection circuit is disposed on the transparent circuit substrate, and the ESD protection circuit is electrically connected with the I/O electrical connecting pad of the die through the patterned conducting layer. A display apparatus including the circuit board is also disclosed.

Abstract: A reduction of a current capability of a MOS transistor (P1) is compensated by dynamically changing a substrate bias of the MOS transistor (P1) in response to a fluctuation of the power supply, and thus an operating speed is stabilized automatically. An NMOS transistor (N2) generates a current (I2) that changes in response to an extent of fluctuation of the power supply voltage, and then the current (I2) is converted into a voltage via a resistor (R3) to apply a forward bias to a substrate (back gate) of the MOS transistor (P1). When the current capability of the MOS transistor (P1) is reduced owing to a reduction of the power supply voltage, an adjustment is carried out automatically to lower a threshold voltage of the MOS transistor and thus the operating speed can be compensated.

Abstract: A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

Abstract: A high voltage operating electrostatic discharge protection device is provided. The high voltage operating electrostatic discharge protection device includes: a first gate structure and a second gate structure disposed on a substrate of a first conductive type with a predetermined distance; a well of the first conductive type formed in a first region of the substrate such that the well contacts one bottom portion of the first gate structure; a source region of a second conductive type formed within in the well; a counter pocket source region of the first conductive type formed within the well encompassing the source region; and a drift region of the second conductive type contacting a bottom surface of the second gate structure and formed in a second region of the substrate such that the drift region contacts the other bottom portion of the first gate structure.