Abstract: A semiconductor protection device for efficiently protecting internal circuits in semiconductor integrated circuits wherein an N-type diffusion layer is formed to enclose a P+ doped diffusion layer. The breakdown voltage of the parasitic diode connected to the collector electrode is consequently set lower than the breakdown voltage of the diode connected to the emitter voltage due to the increase in the concentration of N-type impurities around the parasitic diode from the forming of the N-type diffusion layer. In other words, the diode breakdown voltage is determined by the high or low concentration of impurities around the applicable diode so that the higher concentration of impurities, the lower the breakdown voltage.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to VCC if it is turned on.

Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.

Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Abstract: An external current injection source is provided to individual fingers of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.

Abstract: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell tha

Abstract: An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Abstract: An exemplary ESD protection circuit includes first and second sets of transistors and an ESD discharge transistor. Each of the transistors includes a source electrode, a drain electrode, and a gate electrode. The drain electrodes and gate electrodes of each of the transistors are connected to each other, and the source electrodes of the transistors are respectively connected to the drain electrodes of the next adjacent transistors in both sets of the transistors. The gate electrode of the ESD transistor, the source electrodes of last transistors of the first and second sets of the transistors are connected to each other, the source electrode of the ESD transistor is connected to the drain electrode of a first transistor of the first set of the transistors, and the drain electrode of the ESD transistor is connected to the drain electrode of a first transistor of the second set of the transistors.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: An electrostatic discharge protection element is disclosed for protecting an internal circuit from electrostatic current. The electrostatic discharge protection element forms an embedded LVTSCR by adding a prescribed impurity region within an N-well region having a P-type diode formed therein. A P-well region having a GGNMOS transistor is also formed in the electrostatic discharge protection element. The embedded LVTSCR improves area efficiency, reduces a resistance, and lowers an operational voltage by reducing the distance between the P-type diode and the LVTSCR to allow high-speed operatation.

Abstract: In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an additional n-region next to the drain or an additional floating p-region next to the drain.

Abstract: An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-gate field effect transistor. The protection circuit is configured to protect the insulated-gate field effect transistor from destruction against a pulse having a pulse width of 1 ns or less applied to the card terminal.

Abstract: Systems and methods are disclosed herein to provide improved electrostatic protection for electrical circuits. For example, in accordance with an embodiment of the present invention, an electrostatic protection device includes: a drain region formed in a substrate; a gate separated from the substrate by a gate oxide; and an isolation region formed in the substrate, the isolation region being adapted to isolate the gate oxide from a DC voltage coupled to the drain region.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Abstract: A breakdown protection circuit for a source follower comprising a field effect transistor (FET). The protection circuit comprises a plurality of PFET's and NFET's that are controlled to exhibit on and off states for advantageously configuring a gate, source, drain and body of the source follower FET, to avoid breakdown of and forward biasing of certain FET junctions.

Abstract: A semiconductor device includes a first well of a first conductive type formed in a surface portion of a semiconductor substrate; a first contact group connected with the first well; a second well of a second conductive type formed to surround the first well in the surface portion of the semiconductor substrate; a first guard ring provided on the second well; a second contact group connected with the first guard ring; a third well of the first conductive type formed to surround the second well in the surface portion of the semiconductor substrate; a second guard ring provided on the third well; and a third contact group connected with the second guard ring. The first to third wells form a transistor, and a current flowing through the transistor is suppressed.

Abstract: According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situated between the first and second active regions. The ESD protection structure further includes at least one contact-via chain connected to the first active region, where the at least one contact-via chain includes a contact connected to a via. The at least one contact-via chain forms a ballast resistor for increased ESD current distribution uniformity. The contact is connected to the via by a first metal segment situated in a first interconnect metal layer of a die. The at least one contact-via chain is connected between the first active region and a second metal segment situated in a second interconnect metal layer of the die.

Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.

Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

Abstract: The present invention provides an integrated circuit for providing ESD protection. The integrated circuit comprises a transistor device having at least one interleaved finger having a substrate region, a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one highly doped junction formed adjacent to the source region to measure voltage potential of the substrate region. The integrated circuit further comprises a switching circuit coupled to the at least one highly doped junction such that the voltage potential is transferred to the switching circuit to either draw the full ESD current or trigger to draw the full ESD current.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

Abstract: An integrated circuit used in smart power technology, in particular, for use in automobile applications, which includes: high-voltage terminals for connection to a high voltage, a smart circuit device having low-voltage components, and an ESD protective circuit, connected between the high-voltage terminals, which has a MOSFET whose source and drain are connected to the high-voltage terminals, and whose gate is connected to its source via a resistor, the gate resistor being made of polycrystalline silicon. High ESD resistance with relatively low surface area usage and accordingly low costs may be achieved by using the polyresistor as the gate resistor. One protective diode, which blocks above the supply voltage, may be connected in the blocking direction between source and gate and between gate and drain of the MOSFET.

Abstract: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

Abstract: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.

Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).

Abstract: Realizing that rather than protect electronic circuitry, electrostatic discharge networks when hit by cosmic rays and charged particles, can actually cause the electronic circuitry in satellites and other space applications to fail, the inventor created an ESD network having a redundant voltage clamping element in series with a first voltage clamping element between two voltage pads. The ESD network may be connected to a power voltage pad or a signal voltage pad either directly or through a dummy voltage pad. The voltage clamping elements may further comprise an array of unit cells wherein the array is electrically equivalent to single large transistors currently used in ESD networks. By creating an ESD network as an array of unit cells, benefits greater than those obtained by using a single transistor as a clamping or a trigger element are realized—such as increased ballast resistance and less overall damage to the circuitry resulting from cosmic rays and particles.

Abstract: An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract: Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.

Abstract: A compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations includes first and second protective transistors. The distance from a contact hole for connecting an impurity diffusion layer serving as a source and a drain of each of the first and second protective transistors with a metallic wiring, to gates of the protective transistors, is made shorter than a corresponding distance in an output transistor or a protective transistor provided for an input terminal.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. Numerous other aspects are provided.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

Abstract: A semiconductor integrated circuit electrostatic discharge analysis apparatus includes a resistance network generation unit generating a resistance network served as a power supply interconnect equivalent circuit in a logic cell region of a semiconductor LSI circuit based on pitch, width and a sheet resistance of a power supply interconnect; a protection network generation unit generating an electrostatic discharge protection network with pads and protection elements placed in an I/O cell region of the changing semiconductor LSI circuit, connected to the resistance network; and an analysis unit calculating an inter-pad voltage between the pads when electrostatic discharge equivalent current flows between the pads.

Abstract: The invention provides a circuit substrate including an electrostatic-breakdown-protection circuit efficient for an EL display panel or the like. A substrate includes a common electrode formed on the perimeter of the substrate, multiple terminals formed on the substrate, one or more first resistances formed between adjacent terminals, and one or more second resistances formed between the terminals and the common electrode. The terminal is connected to both the first resistance and the second resistance. The first resistance has a resistance value greater than the second resistance.

Abstract: An electrostatic discharging (ESD) protected metal oxide semiconductor field effect transistor (MOSFET), an epitaxial layer on substrate; a trench gate structure formed in the epitaxial layer; a source region formed in the substrate near the gate structure; a trench capacitor formed underneath gate metal pad in the epitaxial layer connected between the source region and the gate structure, wherein the trench capacitor acts as an ESD improved element for the MOSFET.

Abstract: This invention discloses an electrostatic discharge (ESD) protection circuit that comprises a substrate of a predetermined type, at least one MOS transistor being coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event, a substrate contact region, and at least one floating diffusion region formed in a substrate area between the MOS transistor and the substrate contact region for reducing a trigger-on voltage of the MOS transistor during the ESD event.

Abstract: To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is connected to the output of the NMOS, to shift the output of the NMOS for boosting. Then, a back gate of the NMOS is connected, via a PMOS in an on state, to the power source. With this structure, the PMOS provides a resistor component when the output terminal short-circuits.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: Design and optimization of NMOS drivers using a self-ballasting ESD protection technique in a fully silicided CMOS process. Silicided NMOS fingers which include segmented drain diffusion. Specifically, the segmented drain diffusion provides self-ballasting resistors which improves the ESD performance. Preferably, the width of the each diffusion resistor is relatively small, as this can improve a non-uniform silicidation process. The resistance of the segmented diffusion resistors is determined by their width and length, and effectively increases the ballasting effect of parasitic n-p-n bipolar transistors.

Abstract: A semiconductor device is disclosed. The semiconductor device includes an internal circuit having a high breakdown voltage transistor, and a first electrostatic protection circuit in which electrostatic protection elements are connected in series. The sum of the breakdown voltage values of the electrostatic protection elements in the first electrostatic protection circuit is almost equal to the breakdown voltage value of the high breakdown voltage transistor. The first electrostatic protection circuit is connected between an input/output terminal and a ground terminal of the semiconductor device to which terminals the internal circuit is connected.

Abstract: A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.

Abstract: An active matrix substrate is provided, including a substrate, a plurality of pixel units, a static releasing conductive line and an ESD protection circuit, wherein the substrate has an active area and a peripheral area adjacent to each other. The pixel units are arranged in the active area in an array, and the static releasing conductive line is disposed in the peripheral area of the substrate. The ESD protection circuit is also disposed in the peripheral area of the substrate, being electrically connected between the pixel units and the static releasing conductive line. The ESD protection circuit includes a protection ring and a static consumption device, wherein the protection ring is disposed in a peripheral area of the substrate and the static consumption device has a floating gate, the static consumption device being electrically connected between the ESD protection circuit and the static releasing conductive line.

Abstract: A multi-transistor layout capable of saving area includes a substrate; a common drain comprising four sides formed over the substrate; four gates formed over the four sides of the common drain; and four sources formed over outer sides of the four gates corresponding to the common drain.

Abstract: A protection circuit protects an integrated circuit (“IC”) from peak voltages and includes a voltage divider coupled to a silicon controlled rectifier. The voltage divider allows for adjustment of the trigger voltage, trigger current, and holding voltage of the protection circuit so that the protection circuit can conduct current after a particular voltage level has been applied to the protection circuit without accidental triggering on by, for example, noise.

Abstract: In order to mitigate erosion of exposed processing elements in a processing system by the process and any subsequent contamination of the substrate in the processing system, processing elements exposed to the process are coated with a protective barrier. The protective barrier comprises a protective layer that is resistant to erosion by the plasma, and a bonding layer that improves the adhesion of the protective layer to the processing element to mitigate possible process contamination by failure of the protective layer.

Abstract: A layout structure of electrostatic discharge (ESD) protection circuit cooperated with an ESD protection device includes a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is disposed on the ESD protection device and electrically connected to the ESD protection device. The second electrically conductive layer is disposed on the first electrically conductive layer and electrically connected to the first electrically conductive layer. A width or a projection area of the second electrically conductive layer is less than that of the first electrically conductive layer.

Abstract: In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.