Magnetic Field Patents (Class 257/421)
  • Patent number: 10128432
    Abstract: A nonvolatile magnetic memory device having a magnetoresistance-effect element includes: (A) a laminated structure having a recording layer in which an axis of easy magnetization is oriented in a perpendicular direction; (B) a first wiring line electrically connected to a lower part of the laminated structure; and (C) a second wiring line electrically connected to an upper part of the laminated structure, wherein a high Young's modulus region having a Young's modulus of a higher value than that of a Young's modulus of a material forming the recording layer is provided close to a side surface of the laminated structure.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 13, 2018
    Assignee: SONY CORPORATION
    Inventor: Mitsuharu Shoji
  • Patent number: 10121963
    Abstract: A storage element includes a storage layer, a fixed magnetization layer, a spin barrier layer, and a spin absorption layer. The storage layer stores information based on a magnetization state of a magnetic material. The fixed magnetization layer is provided for the storage layer through a tunnel insulating layer. The spin barrier layer suppresses diffusion of spin-polarized electrons and is provided on the side of the storage layer opposite the fixed magnetization layer. The spin absorption layer is formed of a nonmagnetic metal layer causing spin pumping and provided on the side of the spin barrier layer opposite the storage layer. A direction of magnetization in the storage layer is changed by passing current in a layering direction to inject spin-polarized electrons so that information is recorded in the storage layer and the spin barrier layer includes at least a material selected from oxides, nitrides, and fluorides.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 6, 2018
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Tetsuya Yamamoto, Kazutaka Yamane, Yuki Oishi, Hiroshi Kano
  • Patent number: 10121500
    Abstract: In one embodiment, a system includes a sensor, the sensor having a free layer, a ferromagnetic spin sink layer spaced from the free layer, the spin sink layer being operative to reduce a spin-induced damping in the free layer during operation of the sensor, and a nonmagnetic spacer layer positioned between the free layer and the spin sink layer, the spacer layer having a long spin-diffusion length.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 6, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zheng Gao, James Mac Freitag
  • Patent number: 10115890
    Abstract: The problem of the invention is to provide a magnetic thin film having a high magnetic anisotropy constant Ku and a high coercive force Hc, and to provide an application device comprising the above magnetic thin film. The magnetic thin film of the present invention includes an ordered alloy including: at least one first element selected from the group consisting of Fe and Ni; at least one second element selected from the group consisting of Pt, Pd, Au and Ir; and Sc.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 30, 2018
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hitoshi Nakata, Takehito Shimatsu
  • Patent number: 10109786
    Abstract: A spin-transfer torque magnetic tunnel junction includes a layer stack with a pinned magnetic layer and a free magnetic layer, and an insulating barrier layer there-between. Each of the magnetic layers has an out-of-plane magnetization orientation. The junction is configured so as to allow a spin-polarized current flow generated from one of the two magnetic layers to the other to initiate an asymmetrical switching of the magnetization orientation of the free layer. The switching is off-centered toward an edge of the stack. The junction may allow a spin-polarized current flow that is off-centered toward an edge of the stack, from one of the two magnetic layers to the other, to initiate the asymmetrical switching. Related devices and methods of operation are also provided.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Rolf Allenspach, Anthony J. Annunziata, Daniel C. Worledge, See-Hun Yang
  • Patent number: 10102960
    Abstract: An electronic component includes a multilayer body including insulating layers stacked in a stacking direction, first and second linear conductors having different line widths and provided on a respective one of the insulating layers, and third and fourth linear conductors having different line widths and provided on a respective one of the insulating layers. The insulating layer(s) supporting the third and fourth linear conductors is/are at one side in the stacking direction of the insulating layer(s) supporting the first and the second linear conductors. In a planar view from the stacking direction, the first and the fourth linear conductors overlap each other, and the second and the third linear conductors overlap each other. The first, the second, the third and the fourth linear conductors are electrically connected to define a coil.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 16, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kuniaki Yosui
  • Patent number: 10103319
    Abstract: A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Jimmy Kan, Xiaochun Zhu, Matthias Georg Gottwald, Chando Park, Seung Hyuk Kang
  • Patent number: 10103197
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: October 16, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Patent number: 10096768
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding at the device-level is disclosed. The MRAM chip includes a magnetic shield structure that is substantially surrounding a magnetic tunnel junction (MTJ) bit or device of a MTJ array. The magnetic shield may be configured in the form of a cylindrical shield structure or magnetic shield spacer that substantially surrounds the MTJ bit or device. The magnetic shield structure in the form of cylindrical shield structure or magnetic shield spacer may include top and/or bottom plate shield. The magnetic shield structure in various forms and configurations protect the MTJ stack from external or local magnetic fields. This magnetic shielding structure is applicable for both in-plane and perpendicular MRAM chips.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yi Jiang, Bharat Bhushan, Wanbing Yi, Juan Boon Tan, Pak-Chum Danny Shum
  • Patent number: 10074690
    Abstract: A semiconductor device including: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 11, 2018
    Assignee: SONY CORPORATION
    Inventors: Mitsuharu Shoji, Ichiro Fujiwara
  • Patent number: 10069064
    Abstract: A process flow for forming a magnetic tunnel junction (MTJ) cell that is self-aligned to an underlying bottom electrode (BE) is disclosed. The BE is comprised of a lower BE layer having a first width (w1), and an upper (second) BE layer with a second width (w2) where w2>w1. Preferably, the BE has a T shape. A stack of MTJ layers including an uppermost hard mask is deposited on the BE and has width w2 because of a self-aligned deposition process. A dummy MTJ stack is also formed around the first BE layer. An ion beam etch where ions are at an incident angle <90° with respect to the substrate is used to remove extraneous material on the sidewall. Thereafter, an encapsulation layer is deposited to insulate the MTJ cell, and to fill a gap between the first BE layer and dummy MTJ stack.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: September 4, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng
  • Patent number: 10068931
    Abstract: Presented here are manufacturing techniques to create an irregularly shaped electronic display, including a hollow within which a sensor, such as a camera, can be placed. The manufacturing techniques enable the creation of the hollow anytime during the manufacturing process. The resulting electronic display occupies the full side of the mobile device, with the sensors placed within and surrounded by the display.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 4, 2018
    Assignee: ESSENTIAL PRODUCTS, INC.
    Inventors: David John Evans, V, Xinrui Jiang, Andrew E. Rubin, Matthew Hershenson, Xiaoyu Miao, Joseph Anthony Tate, Jason Sean Gagne-Keats, Rebecca Schultz Zavin
  • Patent number: 10041810
    Abstract: Magnetic field sensors can sense speed of movement and direction of movement of a ferromagnetic object. The magnetic field sensors employ both planar Hall effect elements and vertical Hall effect elements to generate two-state signals in two different signal paths with relative phases that are ninety degrees apart, the ninety degrees having sufficient margin to aid in detection of the direction of motion. Other magnetic field sensors use at least four vertical Hall effect elements to identify a speed of rotation and a direction of rotation of a moving ferromagnetic object.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 7, 2018
    Assignee: Allegro MicroSystems, LLC
    Inventors: Ravi Vig, Paul A. David, Eric G. Shoemaker
  • Patent number: 10043968
    Abstract: There is disclosed an electronic device comprising a semiconductor memory unit capable of reducing the switching current of a variable resistance element that switches between different resistance states. In an implementation, an electronic device includes a semiconductor memory unit that includes a variable resistance element comprising a first magnetic layer configured to have a magnetization direction pinned, a second magnetic layer configured to have a magnetization direction not pinned, and a non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, wherein the variable resistance element comprises plane shapes having a plurality of edges, and the number of angled edges is larger than the number of rounded edges as a damping constant of the second magnetic layer increase.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 7, 2018
    Assignees: SK Hynix Inc., Toshiba Memory Corporation
    Inventors: Sung-Joon Yoon, Tadashi Kai
  • Patent number: 10038136
    Abstract: A method of manufacturing a semiconductor device may include forming a material layer on a substrate, performing a selective oxidation process to form a capping oxide layer on a first surface of the material layer, wherein a second surface of the material layer is not oxidized, and etching the material layer through the second surface to form a material pattern. An etch rate of the capping oxide layer is less than an etch rate of the material layer. A semiconductor device may include a lower electrode on a substrate, a data storage part on a top surface of the lower electrode, an upper electrode on the data storage part, and a capping oxide layer arranged on at least a portion of a top surface of the upper electrode. The capping oxide layer may include an oxide formed by oxidation of an upper surface of the upper electrode.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: July 31, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungyoon Chung, Jinhye Bae, Hyungjoon Kwon, Jongchul Park, Wonjun Lee
  • Patent number: 10038138
    Abstract: A process flow for forming and encapsulating magnetic tunnel junction (MTJ) nanopillars is disclosed wherein MTJ layers including a reference layer (RL), free layer (FL), and tunnel barrier layer (TB) are first patterned by reactive ion etching or ion beam etching to form MTJ sidewalls. A plurality of MTJs on a substrate is heated (annealed) at a station in a process chamber to substantially crystallize the RL, FL, and TB to a body centered cubic (bcc) structure without recrystallization from the edge of the device before an encapsulation layer is deposited thereby ensuring lattice matching between the RL and TB, and between the FL and TB. The encapsulation layer is deposited at the same station as the anneal step without breaking vacuum, and preferably using a physical vapor deposition to prevent reactive species from attacking MTJ sidewalls. Magnetoresistive ratio is improved especially for MTJs with critical dimensions below 70 nm.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 31, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Sahil Patel, Yu-Jen Wang, Dongna Shen
  • Patent number: 10032981
    Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shinhee Han, Kiseok Suh, KyungTae Nam, Woojin Kim, Kwangil Shin, Minkyoung Joo, Gwanhyeob Koh
  • Patent number: 10032979
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer comprising cobalt, iron, and boron formed adjacent to the insulating tunnel junction layer; a second magnetic reference layer comprising cobalt separated from the first magnetic reference layer by a molybdenum layer; an iridium layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the iridium layer. The magnetic free layer structure includes a first and a second magnetic free layers with a perpendicular enhancement layer interposed therebetween. The first and second magnetic reference layers have a first invariable magnetization direction perpendicular to layer planes thereof.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 24, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Huadong Gan, Yiming Huai, Yuchen Zhou, Zihui Wang, Bing K. Yen, Xiaojie Hao, Pengfa Xu
  • Patent number: 10033076
    Abstract: A filter assembly in a multi-layer printed wiring board. One or more conductors is formed on an internal layer of a printed wiring board. Surrounding dielectric layers and ground layers form, together with the conductors of the internal layer, microstrip or stripline transmission lines and distributed element filters. The filter assembly may include a plurality of internal conductive layers, each sandwiched between dielectric layers and ground layers, and each internal layer may include a plurality of distributed element filters. Connections from each filter to the surface of the filter assembly are formed by vias, and connections from the surface of the filter assembly to a host board are formed by solder joints.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: July 24, 2018
    Assignee: RAYTHEON COMPANY
    Inventors: Bradley O. Hansen, Michael R. Beylor, Kevin W. Patrick, Jeremy Bart Baldwin, Michael D. Gordon
  • Patent number: 10032978
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device reduces stray magnetic fields generated by magnetic layers of the stack, including a reference layer and magnetic layers of the synthetic antiferromagnetic layer, in a way that reduces their impact on the other layers of the stack, including a free layer and an optional filter layer, which may include a polarizer layer or a precessional spin current magnetic layer. The reduction in stray magnetic fields in the stack increases the electrical and retention performance of the stack by reducing switching asymmetry in the free layer. The reduction in stray magnetic fields also may improve performance of a filter layer, such as a precessional spin current magnetic layer by reducing asymmetry in the dynamic magnetic rotation of that layer.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 24, 2018
    Assignee: SPIN TRANSFER TECHNOLOGIES, INC.
    Inventors: Manfred Ernst Schabes, Bartlomiej Adam Kardasz, Mustafa Pinarbasi
  • Patent number: 10020039
    Abstract: A magnetoresistive device includes a magnetic free layer having first and second surfaces, the magnetic free layer being comprised of a ferromagnetic material having a perpendicular magnetic anisotropy, a spin current generation layer contacting the first surface of the magnetic free layer, a tunnel barrier layer having one surface contacting the second surface of the magnetic free layer, a reference layer contacting another surface of the tunnel barrier layer, and a leakage field generation layer including first and second leakage field generation layers each of which is comprised of a ferromagnetic material and generates a leakage field, an in-plane component of the leakage field at an part of the magnetic free layer is formed generating a domain wall having an in-plane magnetization component in the magnetic free layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 10, 2018
    Assignee: TOHOKU UNIVERSITY
    Inventors: Shunsuke Fukami, Michihiko Yamanouchi, Hideo Ohno
  • Patent number: 10020446
    Abstract: A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy (“MA”) with the free region, enhancing the MA strength of the free region. A getter material proximate to the secondary oxide region is formulated and configured to remove oxygen from the secondary oxide region, reducing an oxygen concentration and an electrical resistance of the secondary oxide region. Thus, the secondary oxide region contributes only minimally to the electrical resistance of the cell core. Embodiments of the present disclosure therefore enable a high effective magnetoresistance, low resistance area product, and low programming voltage along with the enhanced MA strength. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Witold Kula
  • Patent number: 10014013
    Abstract: A stacked-thin-film structure that includes an Llo-ordered MnAl layer having high perpendicular magnetic anisotropy (PMA). In some embodiments, the Ll0-ordered MnAl layer has an Mn content in a range of about 35% to about 65%, a thickness less than about 50 nm, a saturation magnetization of about 100 emu/cm3 to about 600 emu/cm3 and a magnetocrystalline anisotropy of at least 1×106 erg/cm. In some embodiments, the high-PMA Llo-ordered MnAl material is incorporated in magnetic tunneling junction stacked-film structures that are part of magnetoelectronic circuitry, such as spin-transfer-torque magnetoresistive random access memory circuitry and magnetic logic circuitry. In some embodiments, the high-PMA Llo-ordered MnAl material is incorporated into other devices, such as into read/write heads and/or recording media of hard-disk-drive devices.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: July 3, 2018
    Assignee: Carnegie Mellon University
    Inventors: Mark H. Kryder, Efrem Y. Huang
  • Patent number: 10014465
    Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer has an interface with a tunnel barrier and a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or CoXFeYNiZLW wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing at about 400° C. thereby promoting BCC structure growth in the oxide layer. As a result, free layer PMA is enhanced and maintained to yield improved thermal stability.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Mari Iwata
  • Patent number: 10008384
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 26, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 10008350
    Abstract: According to one embodiment, a magnetic device includes a first extending magnetic portion, a first conductive portion, a first inserted magnetic portion, and a first intermediate portion. The first extending magnetic portion is conductive, and includes a first magnetic region and a second magnetic region. The first magnetic region extends in a first extending direction, includes a first part, and has a first magnetization being changeable. The second magnetic region extends in the first extending direction, having a magnetization being changeable and different form the first magnetization. The first conductive portion is provided apart from the first part in a stacking direction intersecting the first extending direction. The first inserted magnetic portion is provided between the first conductive portion and the first part, and has a second magnetization being changeable. The first intermediate portion is provided between the first part and the first inserted magnetic portion.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: June 26, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Michael Arnaud Quinsat, Shiho Nakamura
  • Patent number: 10008663
    Abstract: The present invention is directed to an MTJ memory element, which includes a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; a tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure formed adjacent to the tunnel junction layer and having a first invariable magnetization direction perpendicular to a layer plane thereof; an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure; and a magnetic fixed layer structure formed adjacent to the anti-ferromagnetic coupling layer and having a second invariable magnetization direction that is perpendicular to a layer plane thereof and is opposite to the first invariable magnetization direction. The magnetic fixed layer structure includes multiple stacks of a trilayer unit structure, which includes three layers of different materials with at least one of the three layers of different materials being magnetic.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: June 26, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Xiaojie Hao, Zihui Wang, Huadong Gan, Yuchen Zhou, Yiming Huai
  • Patent number: 10008536
    Abstract: Methods and devices are provided to construct magnetic devices, such as magnetic random access memory devices, having MTJ (magnetic tunnel junction) structures encapsulated in organic photopatternable dielectric material. For example, a method includes forming an MTJ structure on a semiconductor substrate, encapsulating the MTJ structure in a layer of organic photopatternable dielectric material, patterning the layer of organic photopatternable dielectric material to form a contact opening in the layer of organic photopatternable dielectric material to the MTJ structure, and filling the contact opening with metallic material.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Qinghuang Lin
  • Patent number: 10002904
    Abstract: Methods and devices are provided to construct magnetic devices, such as magnetic random access memory devices, having MTJ (magnetic tunnel junction) structures encapsulated in organic photopatternable dielectric material. For example, a method includes forming an MTJ structure on a semiconductor substrate, encapsulating the MTJ structure in a layer of organic photopatternable dielectric material, patterning the layer of organic photopatternable dielectric material to form a contact opening in the layer of organic photopatternable dielectric material to the MTJ structure, and filling the contact opening with metallic material.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Qinghuang Lin
  • Patent number: 10002905
    Abstract: Data storage devices are provided. A data storage device includes a dielectric layer on a substrate. The data storage device includes a plurality of data storage structures on the dielectric layer. The data storage device includes a conductive material on the dielectric layer. Moreover, the data storage device includes an insulation layer on the conductive material.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 19, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongsoon Park, Sang-Kuk Kim, Jong-Kyu Kim, Jongchul Park, Woohyun Lee, Yil-hyung Lee
  • Patent number: 9997698
    Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: June 12, 2018
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 9991314
    Abstract: A magnetoresistive element according to an embodiment includes: a first magnetic layer; a second magnetic layer; and a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, the second magnetic layer containing a material with a composition (lR1-xhRx)z(TM1-yZy)1-z (0<x<1, 0?y?0.6, 0.13?z?0.22) where lR is at least one element of Y, La, Ce, Pr, Nd, and Sm, hR is at least one element of Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu, TM is at least one element of Mn, Fe, Co, or Ni, and Z is at least one element of B, C, Mg, Al, Sc, Ti, Cu, or Zn.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 5, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoki Hase, Tadaomi Daibou, Yushi Kato, Shumpei Omine, Junichi Ito
  • Patent number: 9991436
    Abstract: An object of the present invention is to provide a low-cost thermoelectric converter element having high productivity and excellent conversion efficiency. A thermoelectric converter element according to the present invention includes a substrate 4, a magnetic film 2 provided on the substrate 4 with a certain magnetization direction A and formed of a polycrystalline magnetically insulating material, and an electrode 3 provided on the magnetic film 2 with a material exhibiting a spin-orbit interaction. When a temperature gradient is applied to the magnetic film 2, a spin current is generated so as to flow from the magnetic film 2 toward the electrode 3. A current I is generated in a direction perpendicular to the magnetization direction A of the magnetic film 2 by the inverse spin Hall effect in the electrode 3.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 5, 2018
    Assignees: NEC CORPORATION, TOHOKU UNIVERSITY
    Inventors: Akihiro Kirihara, Yasunobu Nakamura, Shinichi Yorozu, Kenichi Uchida, Eiji Saitoh
  • Patent number: 9978434
    Abstract: Method for programming a magnetic device including a plurality of magnetic logical unit MLU cells using a single programming current, each MLU cell includes a storage magnetic layer having a storage magnetization that is pinned at a low threshold temperature and freely orientable at a high threshold temperature. A programming line is physically separated from each of the plurality of MLU cells and configured for passing a programming current pulse for programming any one of the plurality of MLU cells. The method includes: passing the programming current in the field line for heating the magnetic tunnel junction of each of the plurality of MLU cells at the high threshold temperature such as to unpin the second magnetization; wherein the programming current is further adapted for generating a programming magnetic field adapted for switching the storage magnetization of each of the plurality of MLU cells in a programmed direction.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: May 22, 2018
    Assignee: CROCUS TECHNOLOGY SA
    Inventor: Yann Conraux
  • Patent number: 9978930
    Abstract: Methods for doping an active Hall effect region of a Hall effect device in a semiconductor substrate, and Hall effect devices having a doped active Hall effect region are provided. A method includes forming a first doping profile of a first doping type in a first depth region of the active Hall effect region by means of a first implantation with a first implantation energy level, forming a second doping profile of the first doping type in a second depth region of the active Hall effect region by means of a second implantation with a second implantation energy level, and forming an overall doping profile of the active Hall effect region by annealing the semiconductor substrate with the active Hall effect region having the first and the second doping profile.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Markus Eckinger, Stefan Kolb
  • Patent number: 9972708
    Abstract: A semiconductor device includes a substrate, a relaxation layer, a channel layer, a polarization compensation layer, and a barrier layer. The relaxation layer is over the substrate and configured to reduce a total strain of the semiconductor device. The channel layer is over the relaxation layer. The polarization compensation layer is between the relaxation layer and the channel layer and configured to reduce a polarization between the relaxation layer and the channel layer. The barrier layer is over the relaxation layer and configured to polarize a junction between the barrier layer and the channel layer to induce a two-dimensional electron gas in the channel layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 15, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Jinqiao Xie, Edward A. Beam, III, Xing Gu
  • Patent number: 9972773
    Abstract: A magnetic junction, a memory using the magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes a pinned layer, a perpendicular enhancement layer (PEL), an insertion layer between the pinned layer and PEL, a free layer and a nonmagnetic spacer layer between the PEL and free layer. The insertion layer includes at least one magnetic material and at least one high crystallization temperature nonmagnetic material. The PEL is between the insertion layer and the nonmagnetic spacer layer. The free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. The PEL and free and pinned layers each has a perpendicular magnetic anisotropy energy greater than its out-of-plane demagnetization energy.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Don Koun Lee, Mohamad Towfik Krounbi
  • Patent number: 9960347
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • Patent number: 9960207
    Abstract: Structures including a spin torque transfer magnetic tunnel junction (MTJ) stack and methods for fabricating same. A first contact is coupled with a first portion of a free layer of the MTJ stack, and a second contact is coupled with a second portion of the free layer of the MTJ stack. The free layer is laterally arranged between the first contact and the second contact.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Sunit S. Mahajan
  • Patent number: 9954164
    Abstract: Disclosed is a method for manufacturing a magnetic memory device. The method for manufacturing a magnetic memory device comprises sequentially forming a first magnetic layer, a tunnel barrier layer, and a second magnetic layer on a substrate, forming a boron absorption layer on the second magnetic layer, sequentially forming a metal capping layer and an oxygen donor layer on the boron absorption layer, and performing a heat treatment process to diffuse at least a portion of oxygen atoms included in the oxygen donor layer into the metal capping layer and the boron absorption layer. The metal capping layer has a greater oxygen diffusivity than the oxygen donor layer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeeun Jeong, Yoonjong Song
  • Patent number: 9947862
    Abstract: According to one embodiment, a magnetoresistive memory device includes a first magnetic layer in which a magnetization direction is variable, a first nonmagnetic layer provided on the first magnetic layer, a second magnetic layer provided on the first nonmagnetic layer, a magnetization direction of the second magnetic layer being invariable, and a second nonmagnetic layer provided on the first magnetic layer, which is opposite the first nonmagnetic layer. The first magnetic layer includes Mo.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Watanabe, Toshihiko Nagase, Youngmin Eeh, Kazuya Sawada, Makoto Nagamine, Tadaaki Oikawa, Kenichi Yoshino, Hiroyuki Ohtori
  • Patent number: 9941466
    Abstract: A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel insulator material comprises MgO and the magnetic electrode material comprises Co and Fe. B is proximate opposing facing surfaces of the tunnel insulator material and the magnetic electrode material. B-absorbing material is formed over a sidewall of at least one of the magnetic electrode material and the tunnel insulator material. B is absorbed from proximate the opposing facing surfaces laterally into the B-absorbing material. Other embodiments are disclosed, including magnetic tunnel junctions independent of method of manufacture.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 9941467
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a free layer perpendicular magnetic anisotropy energy greater than a free layer out-of-plane demagnetization energy. The free layer includes a [CoxFeyBz]uMot layer, where u+t=1, x+y+z=1 and u, t, x, y and z are each nonzero. The [CoxFeyBz]uMot layer has a perpendicular magnetic anisotropy energy greater than its out-of-plane demagnetization energy.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xueti Tang, Mohamad Towfik Krounbi, Donkoun Lee, Gen Feng
  • Patent number: 9936211
    Abstract: A compression device includes a first compressor section, a second compressor section, and a selector. The first compressor section outputs a first compression result or a second compression result as a middle compression result. The first compression result includes a first compression pixel value generated by compressing pixel values of compression target pixels without referring to pixel values of pixels belonging to a line different from a current line. The second compression result includes a second compression pixel value generated by compressing pixel values of the compression target pixels based on a correlation among pixel values of the compression target pixels and reference approximate pixel values. The second compressor section outputs a third compression result based on the correlation among the pixel values of the compression target pixels. The selector outputs one of the middle compression result or the third compression result as a final compression result.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 3, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Shintaro Nakayama
  • Patent number: 9928891
    Abstract: One end of a current path of a second field-effect transistor is connected to a gate of a first field-effect transistor. One end of a magnetic tunnel junction element is connected to one end of a current path of the first field-effect transistor. A first control terminal is connected to another end of the current path of the first field-effect transistor. A second control terminal is connected to another end of the magnetic tunnel junction element. A third control terminal is connected to another end of the current path of the second field-effect transistor.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: March 27, 2018
    Assignee: Tohoku University
    Inventors: Takashi Ohsawa, Tetsuo Endoh
  • Patent number: 9929338
    Abstract: Pure spin current devices are provided. The devices include sandwich structures of metal/magnetic insulator/metal. A first current injected in a first metal layer generates a pure spin current. The spin current can be switched between “on” and “off” states by controlling an in-plane magnetization orientation of the magnetic insulator. In the “on” state, the pure spin current is transmitted from the first metal layer to the second metal layer, through the magnetic insulator layer. The pure spin current in the second metal layer induces generation of a second charge current. In the “off” state, the pure spin current is absorbed at the interface between the first metal layer and the metal insulator. Such structures can serve as pure spin current valve devices or provide analog functionality, as rotating the in-plane magnetization provides analog sinusoidal modulation of the spin current.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: March 27, 2018
    Assignee: The Regents Of The University Of California
    Inventors: Jing Shi, Junxue Li, Yadong Xu, Mohammed Aldosary, Chi Tang, Roger Lake
  • Patent number: 9921274
    Abstract: Provided are a sensing apparatus using a plurality of Hall sensors and an apparatus using the sensing apparatus. The sensing apparatus is configured to measure an intensity of a magnetic field with respect to a magnetic element by using a plurality of Hall sensors and to identify a body that includes the magnetic element.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: March 20, 2018
    Assignee: Haechitech Corporation
    Inventors: Eun Joong Kim, Seong Min Choe
  • Patent number: 9917249
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a pinned layer perpendicular magnetic anisotropy energy greater than a pinned layer out-of-plane demagnetization energy. The pinned layer includes a high perpendicular magnetic anisotropy (PMA) layer including at least one nonmagnetic component, a magnetic layer and a magnetic barrier layer between the high PMA layer and the magnetic layer. The magnetic barrier layer includes Co and at least one of Ta, W and Mo. The magnetic barrier layer is for blocking diffusion of the nonmagnetic component of the high PMA layer.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xueti Tang, Dmytro Apalkov, Gen Feng, Mohamad Towfik Krounbi
  • Patent number: 9918244
    Abstract: Improved methods, systems, or apparatuses for UE equipment testing for D2D enabled UEs may include determining performance metrics based on one or more of received transport blocks (TBs) or received service data units (SDUs) from the received one or more data channels on a per channel basis, and reporting the determined performance metric(s) on a per channel basis. In some examples, the performance metrics may include a count of a number of TBs or SDUs successfully received at a channel.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: March 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kapil Gulati, Sudhir Kumar Baghel, Saurabha Rangrao Tavildar, Shailesh Patil
  • Patent number: 9910596
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate and having a contact hole; a contact plug formed in a lower part of the contact hole; a contact pad formed in an upper part of the contact hole; an amorphous buffer layer interposed between the contact plug and the contact pad; and a variable resistance element formed over the contact pad.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: March 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Chi-Ho Kim, Ki-Seon Park