Abstract: A spin-transfer torque magnetic tunnel junction includes a layer stack with a pinned magnetic layer and a free magnetic layer, and an insulating barrier layer there-between. Each of the magnetic layers has an out-of-plane magnetization orientation. The junction is configured so as to allow a spin-polarized current flow generated from one of the two magnetic layers to the other to initiate an asymmetrical switching of the magnetization orientation of the free layer. The switching is off-centered toward an edge of the stack. The junction may allow a spin-polarized current flow that is off-centered toward an edge of the stack, from one of the two magnetic layers to the other, to initiate the asymmetrical switching. Related devices and methods of operation are also provided.

Abstract: A magnetoresistance effect element of the present invention includes: a barrier layer; a reference layer formed on one surface of the barrier layer; a free layer formed on the other surface of the barrier layer; and a pinned layer placed on the opposite side of the reference layer from the barrier layer. The pinned layer includes a structure obtained by stacking Ni, Co, Pt, Co, Ru, Co, Pt, Co, and Ni layers in this order.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a variable resistance element including a ferromagnetic layer including a hydrogen group; an oxide spacer formed on sidewalls of the variable resistance element; and a nitride spacer formed on the oxide spacer.

Abstract: In one embodiment, a method of forming an electronic device includes providing a wafer having plurality of die separated by spaces. The method includes plasma singulating the wafer through the spaces to form singulation lines that expose side surfaces of the plurality of die. The method includes forming an insulating layer on the exposed side surfaces. In one embodiment, the steps of singulating and forming the insulating layer are carried out with the wafer mounted to a carrier substrate that supports the wafer and singulated die during both steps.

Abstract: A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface; an interlayer formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a coercive force enhancement layer adjacent to the storage layer, opposite to the interlayer, and formed of Cr, Ru, W, Si, or Mn; and a spin barrier layer formed of an oxide, adjacent to the coercive force enhancement layer, and opposite to the storage layer. The storage layer magnetization is reversed using spin torque magnetization reversal caused by a current in a lamination direction of a layer structure including the storage layer, the interlayer, and the fixed magnetization layer, thereby storing information.

Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a memory region. The memory region comprises a bottom via, a recap layer on the BV, a bottom electrode on the recap layer, a magnetic tunneling junction layer on the bottom electrode, and a top electrode on the MTJ layer. The material of the recap layer is different from that of the BV.

Abstract: The present invention is directed to an MTJ memory element including a magnetic free layer structure which includes one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure comprising a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated therefrom by a perpendicular enhancement layer with the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the perpendicular enhancement layer; and a magnetic fixed layer comprising first and second magnetic fixed sublayers with the second magnetic fixed sublayer formed adjacent to the anti-ferromagnetic

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.

Abstract: A method and apparatus for deterministically switching a free layer in a spin orbit torque magnetoresistive random access memory (SOT-MRAM) cell is disclosed herein. In one embodiment, an SOT-MRAM memory cell is provided. The SOT-MRAM memory cell includes a magnetic tunnel junction, a ferromagnetic bias layer, and an antiferromagnetic layer. The magnetic tunnel junction includes a free layer having primarily two bi-stable magnetization directions, a reference layer having a fixed magnetization direction, and an insulating tunnel barrier layer positioned between the free layer and the reference layer. The ferromagnetic bias layer is configured to provide spin orbit torque via anomalous Hall effect and simultaneously configured to provide a magnetic bias field on the free layer to achieve deterministic switching. The antiferromagnetic layer is positioned below the ferromagnetic bias layer and is configured to pin a magnetization direction of the ferromagnetic bias layer in a predetermined direction.

Abstract: A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.

Abstract: A magnetization analysis apparatus includes a processor configured to execute a process. The process includes: first calculating, using a magnetization vector of each of elements obtained by mesh division in which a magnetic substance is divided into a plurality of meshes and a magnetization vector of an element adjacent to each element, intermediate magnetization that is a magnetization vector at the halfway point between each element and an element adjacent to each element; second calculating an effective magnetic field using the intermediate magnetization calculated at the first calculating; and third calculating a magnetization vector of each element after a unit time based on the effective magnetic field calculated at the second calculating.

Abstract: A magnetic tunnel junction device and a method to make the device are disclosed. The magnetic tunnel junction device comprises a first reference magnetic material layer, a tunnel barrier material layer, a free magnetic material layer between the first reference magnetic material layer and the tunnel barrier material layer, and a second reference magnetic material layer disposed on an opposite side of the tunnel barrier material layer from the free magnetic material layer, in which the second reference magnetic material layer is anti-magnetically exchanged coupled with the first reference magnetic material layer. A shift field Hshift experienced by the free magnetic material layer is substantially canceled by the anti-magnetic exchange coupling between the first reference magnetic material layer and the second reference magnetic material layer.

Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, an insulating region provided on the semiconductor substrate, an electrode plug provided in the insulating region, an amorphous conductive portion provided on the electrode plug and including a part provided in the insulating region, and a stacked structure provided on the amorphous conductive portion and including a magnetic layer.

Abstract: A lower conductive film is formed over a substrate. A first insulating film is formed in the lower conductive film. An opening which reaches the lower conductive film is formed in the first insulating film. An MTJ multilayer film having a magnetization free layer, a tunnel barrier layer and a magnetization fixed layer is deposited over the lower conductive film in the opening and over the first insulating film. An upper electrode is formed over the MTJ multilayer film. By removing the portion of the MTJ multilayer film deposited over the first insulating film, an MTJ device composed of the portion of the MTJ multilayer film which has remained in the opening is formed. A lower electrode composed of the lower conductive film is formed under the MTJ device by removing at least a part of the first insulating film, and a part of the lower conductive film.

Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.

Abstract: Systems, methods, and apparatus are provided for tuning a functional property of a device. The device (210) includes a layer of a dielectric material (214) disposed over and forming an interface (216) with a layer of an electrically conductive target material (222). The dielectric material layer includes at least one ionic species having a high ion mobility. The target material is configured such that a potential difference applied to the device can cause the at least one ionic species to migrate reversibly across the interface into or out of the target material layer. The mobility of the at least one ionic species can be tuned by exposing the device to electromagnetic radiation and/or a temperature change.

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract: A method for providing a magnetic junction usable in a magnetic device and a magnetic junction are described. A reference layer, a crystalline MgO tunneling barrier layer and a free layer are provided. The crystalline MgO tunneling barrier layer is continuous, has a (001) orientation and has a thickness of not more than eleven Angstroms and not less than two Angstroms. The crystalline MgO tunneling barrier layer is between the free layer and the reference layer. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A magnetic reference layer is formed adjacent to a tunnel barrier layer. The magnetic reference layer includes a pinned layer, a spacer layer adjacent to the pinned layer, and a polarizing enhancement layer adjacent to the spacer layer. A magnetic free layer is formed adjacent to the tunnel barrier layer so as to be opposite the magnetic reference layer.

Abstract: A magnetoresistive element according to an embodiment includes: a first magnetic layer; a second magnetic layer; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first magnetic layer and the first nonmagnetic layer; and a layer having an amorphous structure, the layer containing two or more elements that are contained in the first magnetic layer, the layer being disposed between the first magnetic layer and the third magnetic layer.

Abstract: A data management system for a biological process, comprising: a. a single-use component, b. a tag assembly, including a non-volatile memory storage component, that is associated with the single-use component, c. the memory storage component including a unique identification and a memory, and at least one data element that describes a key performance, calibration or control parameter of the single-use component d. a memory reader useable to obtain the identification from the memory storage component.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer; and a protection layer including a pillar-shaped magnetic compensation layer and a non-magnetic layer, which are formed on the sidewall of the variable resistance element.

Abstract: A magnetic device includes a pinned polarizing magnetic layer having a magnetic vector parallel to a plane of the pinned polarizing magnetic layer. The magnetic device also includes a free layer, separated from the polarizing magnetic layer by a first non-magnetic layer, having a magnetization vector with a changeable magnetization direction. The changeable magnetization vector is configured to change to a first state upon application of a first current of a first polarity and to change to a second state upon application of a second current of a second, opposite polarity. The magnetic device also has a reference layer having a magnetic vector perpendicular to the plane of the reference layer and separated from the free layer by a second non-magnetic layer.

Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.

Abstract: An electronic device using an array of magnetic wave guides is shown. In one example a memory device is shown that utilizes spin waves and a magnet storage element that interacts with the spin waves. In one example, an electronic device is shown that utilizes both a complementary metal oxide device and a magnonic device coupled together.

Abstract: Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

Abstract: There are provided a storage device and a storage unit capable of improving retention performance of an intermediate resistance value in writing at a low current, and a storage device and a storage unit capable of reducing random telegraph noise. A storage device of one embodiment of the present technology includes a first electrode, a storage layer, and a second electrode in this order, and the storage layer includes: an ion source layer including one or more kinds of chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or more kinds of transition metal elements selected from Group 4 elements, Group 5 elements, and Group 6 elements of the periodic table; and a resistance change layer including boron (B) and oxygen (O).

Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.

Abstract: A multilayered magnetic thin-film stack including a tunneling barrier layer; a magnetic finned layer formed on a first surface of the tunneling barrier layer; and a magnetic free layer formed on a second surface of the tunneling barrier layer, which is opposite to the first surface, wherein at least one of the magnetic finned layer and the magnetic free layer includes a FeZr alloy layer and a first magnetic layer having a (001) bcc structure between the FeZr alloy layer and the tunneling barrier layer.

Abstract: The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure that comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; a first perpendicular enhancement layer (PEL) formed adjacent to the magnetic free layer structure; a magnetic dead layer formed adjacent to the first PEL; and a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a second PEL. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

Abstract: A method of fabricating a wafer according to the embodiment comprises the steps of growing an wafer on a surface of the wafer in a growth temperature; and cooling the wafer after the wafer has been grown, wherein a stepwise cooling is performed when cooling the wafer.

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.

Abstract: A nano-oscillator magnetic wave propagation system has a group of aggregated spin-torque nano-oscillators (ASTNOs), which share a magnetic propagation material. Each of the group of ASTNOs is disposed about an emanating point in the magnetic propagation material. During a non-wave propagation state of the nano-oscillator magnetic wave propagation system, the magnetic propagation material receives a polarizing magnetic field. During a wave propagation state of the nano-oscillator magnetic wave propagation system, each of the group of ASTNOs initiates spin waves through the magnetic propagation material, such that a portion of the spin waves initiated from each of the group of ASTNOs combine to produce an aggregation of spin waves emanating from the emanating point. The aggregation of spin waves may provide a sharper wave front than wave fronts of the individual spin waves initiated from each of the group of ASTNOs.

Abstract: A spin orbit torque-based spintronics device that includes a ferromagnet layer having a first surface and a second surface opposed to each other, a metal layer and a spacer layer covering the first surface and the second surface of the ferromagnet layer, respectively, and an dielectric layer covering either the metal layer or the spacer layer. Also disclosed are two related spin orbit torque-based spintronics devices and methods of using these three spintronics devices.

Abstract: Hybrid Hall Effect Devices implemented with Spin Transfer Torque write capability are configured as magnetoelectronic (ME) devices. These devices are useable as circuit building blocks in reconfigurable processing systems, including as logic circuits, non-volatile switches and memory cells.

Abstract: A method provides a magnetic junction having a top and sides. A first magnetic layer, a nonmagnetic spacer layer and a second magnetic layer are deposited. The nonmagnetic spacer layer is between the first and second magnetic layers. A free layer is one of the magnetic layers. A reference layer is the other of the magnetic layers. The second magnetic layer includes an amorphous magnetic layer having nonmagnetic constituent(s) that are glass-forming. An anneal is performed in a gas having an affinity for the nonmagnetic constituent(s). The gas includes at least one of first and second gases. The first gas forms a gaseous compound with the nonmagnetic constituent(s) The second gas forms a solid compound with the nonmagnetic constituent(s). The second gas is usable if the anneal is performed after the magnetic junction has been defined. The solid compound is at least on the sides of the magnetic junction.

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a spin current injection capping layer between the free layer of a magnetic tunnel junction and the orthogonal polarizer layer. The spin current injection capping layer maximizes the spin torque through very efficient spin current injection from the polarizer. The spin current injection capping layer can be comprised of a layer of MgO and a layer of a ferromagnetic material.

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Abstract: MRAM cell including a magnetic tunnel junction including a reference layer, a storage layer having a storage magnetization, a tunnel barrier layer between the reference and the storage layers; and an antiferromagnetic layer exchange-coupling the storage layer such as to pin the storage magnetization at a low temperature threshold and free it at a high temperature threshold. The storage layer includes a first ferromagnetic layer in contact with the tunnel barrier layer, a second ferromagnetic layer in contact with the antiferromagnetic layer, and a low saturation magnetization storage layer including a ferromagnetic material and a non-magnetic material. The MRAM cell can be written with improved reliability.

Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.

Abstract: A magnetic tunnel junction cell includes a first electrode having an axis extending in a direction substantially perpendicular to an active surface of a substrate. The magnetic tunnel junction further includes a fixed layer, a U-shaped free layer, a tunnel layer sandwiched between the fixed layer and the U-shaped free layer and a second electrode embedded in the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer are disposed between the first electrode and the second electrode and constitute a magnetic tunnel junction. The tunnel layer may also be U-shaped.

Abstract: Magneto-resistive devices with lower power consumption and higher stability are provided. The magneto-resistive devices may include a pinned layer, a free layer and an insulating layer between the pinned layer and the free layer. The pinned layer, the free layer and the insulating layer may constitute a magnetic tunnel junction. The free layer may include a first magnetic layer and a second magnetic layer that has a Curie temperature lower than a Curie temperature of the first magnetic layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: an Nth metal layer; a bottom electrode over the Nth metal layer; a seed layer over the bottom electrode; a magnetic tunneling junction (MTJ) over the seed layer; a top electrode over the MTJ; and an (N+1)th metal layer over the top electrode; wherein the seed layer has a thickness greater than about one-third of a thickness of the MTJ. Another semiconductor structure is also disclosed. The semiconductor structure includes: a bottom electrode; a seed layer over the bottom electrode; a magnetic tunneling junction (MTJ) over the seed layer; and a top electrode over the MTJ; wherein from a cross-sectional view, the seed layer and the MTJ together have a substantial trapezoidal or rectangular shape, and a slope turning point of a sidewall of the substantial trapezoidal or rectangular shape is at a sidewall of the seed layer. An associated manufacturing method is also disclosed.

Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

Abstract: According to one embodiment, there is provided a magnetoresistive element, including a lower electrode having crystallinity on a substrate, a first conductive layer including an amorphous state on the lower electrode, a buffer layer on the first conductive layer, and an MTJ element on the buffer layer.