Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

Abstract: A method and apparatus eliminate magnetic domain walls in a flux guide by applying, either simultaneously or sequentially, a current pulse along serially positioned reset lines to create a magnetic field along the flux guide, thereby removing the magnetic domain walls. By applying the current pulses in parallel and stepping through pairs of shorter reset lines segments via switches, less voltage is required.

Abstract: A magnetic random access memory (MRAM) structure includes a source line connected to a source area of a semiconductor substrate, a magnetic tunnel junction (MTJ) connected to a drain area of the semiconductor substrate, and a gate disposed over the semiconductor substrate between the source area and the drain area. The MRAM structure further includes a contact structure that is configured to apply a first voltage bias to the gate and a means for applying a second voltage bias to the semiconductor substrate outside of the source area and the drain area.

Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, an asymmetric free layer and a perpendicular magnetic anisotropy (PMA) inducing layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer is between the nonmagnetic spacer layer and the PMA inducing layer. The asymmetric free layer includes a first ferromagnetic layer having a first boron content and a second ferromagnetic layer having a second boron content. The second boron content is less than the first boron content. The first boron content and the second boron content are each greater than zero atomic percent. The first and second ferromagnetic layers each contain at least one of Co and CoFe. The magnetic junction is configured such that the asymmetric free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: In a method of manufacturing a MRAM device, a lower electrode is formed on a substrate. A first magnetic layer, a tunnel barrier layer, and a second magnetic layer are sequentially formed on the lower electrode layer. An etching mask is formed on the second magnetic layer. An ion beam etching process in which a first ion beam and a second ion beam are simultaneously emitted onto the substrate is performed to form a MTJ structure including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern from the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, respectively, the MTJ structure has no by-products remaining after the ion beam etching process is performed.

Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region (140); a drain region (190) aligned substantially vertically to the source region; a channel structure (160) bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure (170) arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels (161) extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor (240) interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.

Abstract: Methods of fabricating MRAM devices are provided along with a processing apparatus for fabricating the MRAM devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50° K to about 300° K, forming and oxidizing one or more Mg layers on the cooled ferromagnetic layer to form an MgO structure, forming a free layer on the MgO structure, and forming a capping layer on the free layer.

Abstract: An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other.

Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a magnetic element, a protective insulating film covering the stacked structure, and an interface layer provided at an interface between the stacked structure and the protective insulating film. The interface layer contains a predetermined element which is not contained in the magnetic element or the protective insulating film.

Abstract: Embodiments of the present disclosure generally relate to memory devices having enhanced perpendicular magnetic anisotropy. The memory device includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells having a plurality of magnetic layers and a tunneling barrier layer. An interfacial layer is incorporated in each memory cell between one of the magnetic layers and the tunneling barrier layer to enhance perpendicular magnetic anisotropy, while preserving high tunneling magnetoresistance.

Abstract: The invention is directed to a method of manufacturing a ferromagnetic device (10), having an elongated structure extending along a longitudinal direction (11), comprising a ferromagnetic material, wherein a transverse cross section (20) of the ferromagnetic material, perpendicular to said longitudinal direction, is designed to provide a domain wall velocity above the Walker breakdown limit of the ferromagnetic material. In particular, at least a portion (21-23) of a peripheral contour of the ferromagnetic material forms, in the transverse cross-section (20), a non-orthogonal convex set. For example, the whole peripheral contour may realize a (non-orthogonal) convex polygon.

Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: An embodiment includes a C-element logic gate implemented as a spin logic device that provides a compact and low-power implementation of asynchronous logic by implementing a C-element with spintronic technology. An embodiment includes a first nanopillar including a first contact and a first fixed magnetic layer; a second nanopillar including a second contact and a second fixed magnetic layer; and a third nanopillar including a third contact, a tunnel barrier, and a third fixed magnetic layer; wherein (a) the first, second, and third nanopillars are all formed over a free magnetic layer, and (b) the third fixed magnetic layer, the tunnel barrier, and the free magnetic layer form a magnetic tunnel junction (MTJ). Other embodiments are described herein.

Abstract: A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. The method includes providing a free layer, a pinned layer and a nonmagnetic spacer layer between the free layer and the pinned layer. The free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the step of providing the free layer includes a first plurality of steps and the step of providing the pinned layer includes a second plurality of steps. The first and second plurality of steps include depositing a portion of a layer, depositing a sacrificial layer, annealing the portion of the magnetic junction under the sacrificial layer, and depositing a remaining portion of the layer. The layer may be the free layer, the pinned layer, or both.

Abstract: A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.

Abstract: A device includes a sensor surface and a pair of electrodes. The sensor surface includes a first conductive layer separated from a second conductive layer by an intermediary layer, a magnetization direction of the first conductive layer and a magnetization direction of the second conductive layer having a ground state orientation of approximately 0 degrees. An electrical resistance between the pair of electrodes is determined by a magnetic field proximate the sensor surface.

Abstract: Output signals from two or more vertical Hall elements arranged in a circle are combined is ways that reduce an offset voltage as the two or more vertical Hall elements are sequenced to generated a sequential output signal.

Abstract: A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract: A stacked optoelectronic packaged device includes a plurality of stacked components within a package material having a package body providing side walls and a bottom wall for the package, and a lid which seals a top of the package. The stacked components include a first cavity die having a top surface and a bottom surface including at least one through-channel formed in the bottom surface. A bottom die has a top surface including at least one electrical trace and a light source die thereon. At least one of the through-channels of the first cavity die are aligned to the electrical trace, and the first cavity die is bonded to the bottom die with the electrical trace being within the through-channel and not contacting the first cavity die to provide a vacuum sealing structure. A photodetector (PD) is optically coupled to receive the light originating from the light source.

Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

Abstract: A graphene-based magnetic tunnel junction is disclosed. The magnetic tunnel junction can enhance the tunnel magnetoresistance ratio and a device including the magnetic tunnel junction. The magnetic tunnel junction includes: a pinned layer; a free layer; and a graphene with segmented potentials configured between the pinned layer and the free layer. The magnetic tunnel junction may be a series or parallel connection of the above-mentioned basic form. The device including a magnetic tunnel junction may be a magnetic random access memory bit cell, a magnetic tunnel junction transistor device, a magnetic field sensor, etc.

Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.

Abstract: A magnetic tunnel junction cell includes a first electrode having an axis extending in a direction substantially perpendicular to an active surface of a substrate. The magnetic tunnel junction further includes a fixed layer, a U-shaped free layer, a tunnel layer sandwiched between the fixed layer and the U-shaped free layer and a second electrode embedded in the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer are disposed between the first electrode and the second electrode and constitute a magnetic tunnel junction. The tunnel layer may also be U-shaped.

Abstract: Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.

Abstract: Embodiments of the technology implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between the fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series.

Abstract: Provided is a magnetic memory device. The magnetic memory device includes a first magnetization layer, a tunnel barrier disposed on the first magnetization layer, a second magnetization layer disposed on the tunnel barrier, and a spin current assisting layer disposed on at least a portion of a sidewall of the second magnetization layer.

Abstract: A nonvolatile magnetic memory device with a magnetoresistance-effect element includes a laminated structure, a first wiring line, and a second wiring line. The laminated structure includes a recording layer in which an axis of easy magnetization is oriented in a perpendicular direction. The first wiring line is electrically connected to a lower part of the laminated structure. The second wiring line electrically connected to an upper part of the laminated structure. A high Young's modulus region is provided on a side surface of the laminated structure. A Young's modulus value of a material of the high Young's modulus region is greater than a Young's modulus value of a material of the recording layer.

Abstract: A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.

Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract: The present invention is directed to a magnetic random access memory element that includes a multilayered seed structure formed by interleaving a first type sublayer and a second type sublayer to form one or more repeats of a unit bilayer structure and a first magnetic layer formed on top of the multilayered seed structure. The unit bilayer structure is made of the first and second type sublayers with at least one of the first and second type sublayers including therein one or more ferromagnetic elements. The multilayered seed structure may be amorphous or non-magnetic or both. The unit bilayer structure may be made of CoFeB and Ta sublayers.

Abstract: A magnetic junction and method and programming the magnetic junction are described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a perpendicular magnetic anisotropy exceeding its out-of-plane demagnetization energy a quiescent state. The free layer has a magnetostriction such that the perpendicular magnetic anisotropy changes in the presence of a programming voltage applied for the magnetic junction, canting that the magnetic moment by at least five degrees from its quiescent direction. The programming voltage is at least 0.1 volt and not more than 2 volts. The nonmagnetic spacer layer is an insulating tunneling barrier layer and/or the magnetic junction includes an additional insulating layer adjacent to the opposite interface of the free layer.

Abstract: A current sensor includes a magnetic core with a gap in part of a circumference and formed in an annular shape, and a magneto-electric conversion element arranged in the gap, the magneto-electric conversion element detecting magnetic fluxes changing with a measurement target current passing through a hollow part of the magnetic core. The magnetic core is formed by laminating a plurality of materials in a direction except a circumferential direction, and is formed so that magnetic flux densities of two points in an area defined in advance as an area where a sensing part of the magneto-electric conversion element can exist (hereinafter referred to as a sensing part existence area) approximate to each other, the two points being away from each other with a distance in a laminating direction being a length of the sensing part in the laminating direction.

Abstract: A magnetic memory device may include a free magnetic structure and a reference magnetic structure that are separated from each other by a tunnel barrier. The free magnetic structure may include an exchange-coupling layer, and first and second free layers that are separated from each other by the exchange-coupling layer. The first free layer may be provided between the second free layer and the tunnel barrier. A thickness of the first free layer may be greater than a first maximum anisotropy thickness, being the thickness at which the first free layer has maximum perpendicular anisotropy. A thickness of the second free layer may be smaller than a second maximum anisotropy thickness, being the thickness at which the second free layer has maximum perpendicular anisotropy. A magnetic tunnel junction having two free layers with different thicknesses can enable a magnetic memory device that has increased MR ratio and reduced switching current.

Abstract: Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer.

Abstract: Some embodiments include a magnetic tunnel junction which has a conductive first magnetic electrode containing magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and containing magnetic reference material, and a non-magnetic insulator material between the first and second electrodes. The magnetic recording material of the first electrode includes a set having an iridium-containing region between a pair of non-iridium-containing regions. In some embodiments, the non-iridium-containing regions are cobalt-containing regions.

Abstract: Provided is a storage cell that makes it possible to improve TMR characteristics, a storage device and a magnetic head that include the storage cell. The storage cell includes a layer structure including a storage layer in which a direction of magnetization is varied in correspondence with information, a magnetization pinned layer having magnetization that is perpendicular to a film surface and serves as a reference of information stored in the storage layer, and an intermediate layer that is provided between the storage layer and the magnetization pinned layer and is made of a nonmagnetic body. Carbon is inserted in the intermediate layer, and feeding a current in a laminating direction of the layer structure allows the direction of magnetization in the storage layer to be varied, to allow information to be recorded in the storage layer.

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

Abstract: An electric power transmission apparatus includes a resonance circuit, a first signal generation unit, and a second signal generation unit. The resonance circuit is used for contactless electric power transmission. The first signal generation unit is connected to one end of the resonance circuit, and generates a first high-frequency signal which includes one or more harmonic components using a switching method. The second signal generation unit is connected to the other end of the resonance circuit, and generates a second high-frequency signal which includes a specific harmonic component using the switching method. The first high-frequency signal is input to the one end of the resonance circuit, and the second high-frequency signal is input to the other end of the resonance circuit.

Abstract: The present invention relates to a magnetic sensor and a magnetic detecting method of the same capable of detecting at least a magnetic field perpendicular to a substrate and a magnetic field parallel to the substrate in a state where the respective magnetic field components are mixed. One embodiment of the magnetic sensor detects a magnetic field of the orthogonal three axes, and includes a magnetic detector including a magnetic field sensitive material configured to detect a magnetic field component in a first direction, a magnetic field direction converters configured to convert a magnetic field component in a second direction and a magnetic field component in a third direction into magnetic field components in the first direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to both of the first and the second directions.

Abstract: A high speed, low power method to control and switch the magnetization direction of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a pinned magnetic layer, a reference magnetic layer with a fixed magnetization direction and a free magnetic layer with a changeable magnetization direction. The magnetic layers are separated by insulating non-magnetic layers. A current can be applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information. The resistance, which depends on the magnetic state of the device, can be measured to read out the information stored in the device.

Abstract: A magnetic tunnel junction (MTJ) device includes a pinned layer, a tunnel barrier layer on the pinned layer, and a free layer on the tunnel barrier layer. The MTJ device also includes a perpendicular magnetic anisotropic (PMA) enhancement layer on the free layer, a capping layer on the PMA enhancement layer, and a conductive path electrically shorting the capping layer, the PMA enhancement layer and the free layer. A method of fabricating a perpendicular magnetic tunnel junction (pMTJ) device includes forming a capping layer, a perpendicular magnetic anisotropic (PMA) enhancement layer and a free layer. The method also includes forming a conductive layer to short the capping layer, the PMA enhancement layer and the free layer.

Abstract: Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed for use in energy constrained applications in which logic operations are carried out using a minimal number of physical operations. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc. including in clockless applications.

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer has an interface with a tunnel barrier and a second interface with a metal oxide layer to promote perpendicular magnetic anisotropy (PMA) therein. A diffusion barrier is formed on a side of the metal oxide layer opposite the second interface to prevent non-magnetic metals in a hard mask or electrode from migrating to the second interface and degrading free layer PMA. A second diffusion barrier may be formed between a second electrode and a reference layer. The diffusion barrier may be a single layer of SiN, TiN, TaN, Mo, or CoFeX where X is Zr, P, B, or Ta, or is a multilayer such as CoFeX/Mo wherein CoFeX contacts the metal oxide layer and Mo adjoins a hard mask. As a result, coercivity is maintained or increased in the MTJ after annealing at 400° C. for 30 minutes.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a plurality of variable resistance devices connected to a word line, and a plurality of bit lines, each of which provides an electrical pathway between a corresponding one of the variable resistance devices and a read and write circuit. Each of the variable resistance devices includes a free layer and a pinned layer spaced apart from each other and having a tunnel barrier interposed therebetween, an assistant layer spaced apart from the tunnel barrier and having the free layer interposed therebetween, and an exchange coupling layer arranged between the free layer and the assistant layer. The exchange coupling layer has an electric polarization, which results from its ferroelectric property, and having a direction that can be changed by a voltage applied to the corresponding one of the bit lines.

Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract: Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.

Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

Abstract: A method for manufacturing MTJ pillars for a MTJ memory device. The method includes depositing multiple MTJ layers on a substrate, depositing a hard mask on the substrate and coating a photoresist on the hard mask. Further, alternating steps of reactive ion etching and ion beam etching are performed to isolate MTJ pillars and expose side surfaces of the MTJ layers. An insulating layer is the applied to protect the side surfaces of the MTJ layers. A second insulating layer is deposited before the device is planarized using chemical mechanical polishing.