Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.

Abstract: An n/p?/p+ substrate where a p?-type epitaxial layer and an n-type epitaxial layer have been deposited on a p+-type substrate is provided. In the surface region of the n-type epitaxial layer, the n-type region of a photoelectric conversion part has been formed. Furthermore, a barrier layer composed of a p-type semiconductor region has been formed so as to enclose the n-type region of the photoelectric conversion part in a plane and reach the p?-type epitaxial layer from the substrate surface. A p-type semiconductor region has also been formed at a chip cutting part for dividing the substrate into individual devices so as to reach the p?-type epitaxial layer from the substrate surface.

Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.

Abstract: A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the isolation region into the photosensor, thereby suppressing dark current in imagers.

Abstract: An integrated forming, assembly and inspection system includes a plurality of robotic material conveyors. The integrated system also includes a forming subsystem including sheet metal drawing apparatus, a roller hemming subsystem, and an inspection subsystem. The plurality of robotic material conveyors are operable to convey assembly workpieces to and from the subsystems.

Abstract: A front-illuminated-type photodiode array comprises (a) a first-electroconductive-type semiconductor substrate, (b) a first-electroconductive-type electrode placed at the rear-face side of the semi-conductor substrate, (c) a first-electroconductive-type absorption layer formed at the front-face side of the semiconductor substrate, (d) a plurality of second-electroconductive-type regions formed from the surface of the absorption layer to a certain distance into the absorption layer such that the regions are arranged one- or two-dimensionally, (e) a second-electroconductive-type electrode provided at part of each of the second-electroconductive-type regions, (f) an antireflective coating that covers the top surface other than the individual second-electroconductive-type electrodes and that is for preventing reflection of an incoming lightwave, and (g) at least one leakage-lightwave-absorbing layer that is provided between the first-electroconductive-type electrode and the absorption layer and that has an absorp

Abstract: The invention relates to a photodetectors array that will be hybridized on a readout circuit (30) and realized from a wafer of semiconducting material (11). The wafer is divided into pixels (12), each pixel forming a photodetector, the pixels being separated from each other by separation means formed in the wafer and comprising a photogrid for photodetectors, each photodetector having a connection pad (18) to hybridize the photodetectors array to the readout circuit.

Abstract: A photodetector circuit incorporates an avalanche photodiode structure having a contact layer (14) forming an ohmic contact over an annular region (18) with the annular guard ring (8). In the fabrication process, the starting substrate can either be the handle wafer of a p? silicon-on-insulator wafer, or a p-Si substrate with an insulating SiO2 layer (4). A window (6) is produced in the insulating layer (4) by conventional photolithographic and etching. A n+ guard ring (8) is created by diffusing donor impurities into the substrate, and a thinner insulating SiO2 layer (22) is thermally grown so as to cover the exposed surface of the substrate within the window (6). P-type dopant is then implanted through the thin oxide layer to increase the doping level near the surface of the substrate. Subsequently a second window (24) is made in the insulating layer (22), and the layer (12) is then epitaxially grown selectively on the area of the substrate exposed by the window (24) in the insulating layer (22).

Abstract: A MOS image pick-up device including a semiconductor substrate, an imaging region formed on the semiconductor substrate by arraying plural unit pixels, and a peripheral circuit region including a driving circuit for operating the imaging region formed on the semiconductor substrate; the unit pixels include a photodiode, MOS (metal-oxide-semiconductor) transistors and a first device-isolation portion, the peripheral circuit region includes a second device-isolation portion for isolating devices in the driving circuit; wherein each of the first device-isolation portion and the second device-isolation portion is at least one portion selected from an electrically insulating film formed on the substrate in order not to erode the substrate, a electrically insulating film formed on the substrate so as to erode the substrate to a depth ranging from 1 nm to 50 nm, and an impurity diffusion region formed within the substrate. The MOS image pick-up device is incorporated in a camera.

Abstract: A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region.

Abstract: An optical integrated circuit having optical devices is fabricated. These optical devices must be biased in the mutually opposite directions. If such an optical integrated circuit is fabricated using a conductive semiconductor substrate as conventionally, it is not possible to drive the devices by a single power supply since the substrate side is shared as a common polarity by the devices. The present invention realizes a structure where both anode and cathode of each device can be isolated electrically by conventional process technology and provides an optical integrated circuit which can be driven by a single power supply. An optical integrated circuit is formed on a semi-insulative or insulative substrate. A high resistivity region which extends at least from the active layer to the substrate and includes part of an optical waveguide between the devices is formed so as to electrically isolate the anode and cathode of each integrated device from the other device.

Abstract: A primary object of the present invention is to provide a photoelectric conversion apparatus with less leak current in a floating diffusion region. In order to obtain the above object, a photoelectric conversion apparatus according to the present invention includes a photodiode for converting light into a signal charge, a first semiconductor region having a first conductivity type, a floating diffusion region formed from a second semiconductor region having a second conductivity type for converting the signal charge generated by the photodiode into a signal voltage, the second semiconductor region being formed in the first semiconductor region, and an electrode formed above the first semiconductor region through an insulating film and having an effect of increasing a concentration of majority carriers in the first semiconductor region, in which the electrode is not formed above a depletion region formed from the second semiconductor region.

Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.

Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: The present invention relates to an isolation layer for CMOS image sensor and a fabrication method thereof, which are capable of improving a low light level characteristic of the CMOS image sensor. The isolation layer includes: a field insulating layer formed on a predetermined portion of a substrate in the logic area to thereby define an active area and a field area; a field stop ion implantation area formed on a predetermined portion of the substrate in the pixel area, the field stop ion implantation area having a predetermined depth from a surface of the substrate to define an active area and a field area; and an oxide layer deposited on a substrate surface corresponding to the field stop ion implantation area.

Abstract: A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

Abstract: An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substrate. The photosensor and the light emitting element are isolated by the shallow trench isolation structure. An opening is formed in the shallow trench isolation structure to expose part of the substrate. An opaque shield is formed in the opening to prevent photons from the light emitting element from striking the photosensor.

Abstract: This invention concerns a non-volatile memory device with a polarizable layer. The apparatus concerns a substrate, a buried oxide layer within the substrate, and a polarizable layer within the substrate. The polarizable layer is formed in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. The process of creating the polarizable layer comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5–50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25–300 degrees Celsius. An annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Abstract: A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the isolation region into the photosensor, thereby suppressing dark current in imagers.

Abstract: A solid-state imaging device that achieves a reduction in variations appearing on a reproducing screen is provided. The solid-state imaging device includes a plurality of pixel cells that are laid out in matrix form on a semiconductor substrate and a driving unit that is provided to drive the plurality of pixel cells. Each of the plurality of pixel cells includes a photodiode, a MOS transistor, and an element isolating portion 2 that is formed so that the photodiode and the MOS transistor are isolated from each other. The element isolating portion 2 is formed of a STI (Shallow Trench Isolation) that is a grooved portion of the semiconductor substrate. In the semiconductor substrate 7, a STI leakage stopper 1 in which an impurity of a conductive type opposite to a conductive type of source/drain regions in the MOS transistor is introduced is formed to enclose side walls and a bottom face of the element isolating portion 2.

Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all

Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.

Abstract: Embodiments of the invention provide a barrier region for isolating devices of an image sensor. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region is adjacent to at least one pixel cell of a pixel array. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.

Abstract: A detection system for detecting gamma rays including a scintillator crystal for receiving at least one gamma ray and generating at least one ultraviolet ray and an avalanche photodiode for detecting the ultraviolet ray. The avalanche photodiode includes: a substrate having a first dopant; a first layer having a second dopant, positioned on top of the substrate; a passivation layer for providing electrical passivation on a surface of the avalanche photodiode; a phosphorous silicate glass layer for limiting mobile ion transport, positioned above of the first layer; and a pair of metal electrodes for providing an ohmic contact wherein a first electrode is positioned below the substrate and a second electrode is positioned above the first layer. The avalanche photodiode comprises a first sidewall and a second sidewall forming a sloped mesa shape.

Abstract: The present invention provides an image sensor capable of suppressing the dark current due to crystalline defects occurring at an edge of a field oxide layer and a method for fabricating the same. The present invention provides an image sensor including: a semiconductor substrate; an active area including a photodiode area formed in a predetermined position of the substrate, a floating diffusion area having a smaller area than the photodiode area and a channel area having a bottle-neck structure connecting to the photodiode area and the floating diffusion area; a field area for isolating electrically the active area; a field stop layer being formed beneath the field area by having a wider area than the field area through an expansion towards the active area with a first width; and a gate electrode formed on the substrate by covering the channel area and having one side superposed with a second width on one entire side of the photodiode contacted to the channel area.

Abstract: A method of forming a MEMS device produces a device layer wafer having a pre-formed conductive pathway before coupling it with a handle wafer. To that end, the method produces the noted device layer wafer by 1) providing a material layer, 2) coupling a conductor to the material layer, and 3) forming at least two conductive paths through at least a portion of the material layer to the conductor. The method then provides the noted handle wafer, and couples the device layer wafer to the handle wafer. The wafers are coupled so that the conductor is contained between the material layer and the handle wafer.

Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

Abstract: A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the substrate (4) from the upper surface within the termination region (1). Termination trench (12) is at least partly filled with an insulating material (13) which extends from the termination trench (12) to overlie adjacent regions of the device above the surface. A channel stop region (11) extends laterally from a side wall of the termination trench (12) into the substrate (4).

Abstract: A semiconductor photodetection device includes a light incident facet for receiving light from an optical waveguide. Light received at the light incident facet is refracted through a photo-absorption layer to register photonic events. A material may be introduced between the optical waveguide and the light incident facet to improve responsiveness of the device. The light incident facet may be at an angle to the direction of the light emitted from the optical waveguide to cause the incident light to be refracted through several layers of the semiconductor photodetection device.

Abstract: Various circuit devices incorporating junction-traversing dislocation regions and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region in a device region of a semiconductor-on-insulator substrate. The impurity region defines a junction. A dislocation region is formed in the device region that traverses the junction. The dislocation region provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract: A photodetector circuit incorporates an avalanche photodiode (APD) 300 produced by epitaxy on a CMOS substrate 302 with implanted n-well 304 and p-well 306. The n-well 304 has an implanted p+ guard ring 310 delimiting the APD 300. Within the guard ring 310 is an implanted n+ APD layer 312 upon which is deposited an epitaxial p+ APD layer 314, these layers forming the APD 300. The APD may be incorporated in an amplifier circuit 50 providing feedback to maintain constant bias voltage, and may include an SiGe absorption region to provide extended long wavelength response or lower avalanche voltage. Non-avalanche photodiodes may also be used.

Abstract: A method for producing a semiconductor device with a built-in light receiving element is provided. The device comprises a light receiving element region for receiving and converting an optical signal to an electric signal, the light receiving element region being provided on a substrate. The method comprises the steps forming an anti-reflection film in the light receiving element region on the substrate, and forming a protection film, the protection film serving as an etch stop film in a subsequent etching step.

Abstract: A photodiode array device having an absorption layer and a cladding layer formed on one surface of a single substrate, anodes formed on the cladding layer, a cathode formed on the other surface of the substrate, and a plurality of light-receiving regions; a photodiode module including the photodiode array device; and a structure for connecting the photodiode module and an optical connector. The photodiode array device has trenches formed on the one surface of the substrate and having such a depth as to divide the absorption layer into subdivisions, for cutting off propagation of light between adjacent light-receiving regions.

Abstract: An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150° C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials.

Abstract: The present invention provides an image sensor capable of suppressing the dark current due to crystalline defects occurring at an edge of a field oxide layer and a method for fabricating the same. The present invention provides an image sensor including: a semiconductor substrate; an active area including a photodiode area formed in a predetermined position of the substrate, a floating diffusion area having a smaller area than the photodiode area and a channel area having a bottle-neck structure connecting to the photodiode area and the floating diffusion area; a field area for isolating electrically the active area; a field stop layer being formed beneath the field area by having a wider area than the field area through an expansion towards the active area with a first width; and a gate electrode formed on the substrate by covering the channel area and having one side superposed with a second width on one entire side of the photodiode contacted to the channel area.

Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.

Abstract: A photovoltaic generator constructed on an SOI N− layer subdivided into a series of connected isolated tubs whereby the isolated tubs are subdivided by a matrix of trenched wells. A P+ junction is formed into the top surface of each well to define a photovoltaic generator junction for its respective well.

Abstract: A plurality of N-type diffusion layers (105, 108) are formed a specified distance apart on a P-type semiconductor layer (102). A P-type leak prevention layer (109) formed between at least N-type diffusion layers (105, 108) prevents leaking between the diffusion layers (105, 108). A dielectric film (115) is formed in at least a light incident area on a P-type semiconductor layer (102) including the diffusion layers (105, 108) and the leak prevention layer (109). Accordingly, provided are a split type light receiving element positively functioning as a split type light receiving element even when charge is accumulated in the dielectric film and having a uniform sensitivity throughout the entire area on a light receiving surface, and a circuit-built-in light receiving element and an optical disk device using the split type light receiving element.

Abstract: A light-receiving element, comprises an absorption layer formed on a semiconductor substrate, a window layer formed on the absorption layer, a first electrode formed on the window layer, a second electrode formed on the window layer and electrically connected to the first electrode, and a diffusion region which is formed in the absorption layer and the window layer and is formed between the first electrode and the substrate and between the second electrode and the substrate.

Abstract: Provided is a semiconductor device includes a semiconductor element having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type which is formed in the first semiconductor region, an element isolation layer formed between the semiconductor element and an adjacent element, a third semiconductor region of the first conductivity type having a higher concentration than the first semiconductor region formed under the element isolation layer, and a conductor layer formed on a portion of the element isolation layer, in which a fourth semiconductor region of the first conductivity type having a higher concentration than the third semiconductor region is further provided in at least a portion of a region opposite to the conductor layer through the element isolation layer and wiched there between.

Abstract: An image sensor with improved productivity and sensitivity is provided. The image sensor includes a plurality of unit pixels, each unit pixel including an oxide film formed upon a semiconductor substrate; a gate electrode formed on the oxide film; a photodiode N-type region formed within the semiconductor substrate and interfacing with the oxide film, which is space apart from the gate electrode by a predetermined distance and disposed on one side of the gate electrode; and a floating diffusion region formed within the semiconductor substrate and interfacing with the oxide film, which is spaced apart from the gate electrode by a predetermined distance and is disposed on the other side of the gate electrode.

Abstract: The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

Abstract: A photoelectric conversion element comprising a substrate and a light sensor disposed on a surface of the substrate and receiving high speed optical pulse signals and converting them into high frequency waves in which the light sensor comprises at least carbon nano-tubes, as well as a photoelectric conversion device having the element, for directly converting high speed optical pulses signals in a communication band into signals of high frequency waves or electromagnetic waves.

Abstract: A semiconductor photodetection device includes a semiconductor structure including an optical absorption layer having a photo-incidence surface on a first side thereof, a dielectric reflecting layer formed on a second side of the semiconductor structure opposite to the first side, a contact electrode surrounding the dielectric reflecting layer and contacting with the semiconductor structure, and a close contact electrode covering the dielectric reflecting layer and contacting with the contact electrode and the dielectric reflecting layer, wherein the close contact electrode adheres to the dielectric reflecting layer more strongly than to the contact electrode.

Abstract: In a solid-state image pick-up device comprising a plurality of light receiving sensor sections, a vertical transfer path 12 formed close to each of the light receiving sensor sections, and a channel stopper 13 provided between the adjacent vertical transfer paths 12 and formed by an insulating layer having a trench structure, a conductive substance 15 to which a predetermined voltage is applied is buried in the insulating layer 14. The predetermined voltage is a negative voltage if a signal charge is an electron, and is a positive voltage if the signal charge is a hole. Alternatively, the predetermined voltage is a pulse having an opposite phase to that of a read pulse to be applied to a transfer electrode 17 of the vertical transfer path 12.

Abstract: A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.

Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: The present invention relates to a CMOS (Complementary Metal Oxide Silicon) image sensor; and, more particularly, to an image sensor integrated into one chip, together with a memory. The CMOS image sensor according to the present invention comprises: a pixel array formed on a chip, having a plurality of unit pixels; a logic circuit formed on the chip to process signals form the pixel array; and a memory formed on the chip to store outputs from the logic circuit, wherein the pixel array, the logic circuit and the memory are isolated from each other by insulating layers, whereby the pixel array, the logic circuit and the memory are integrated on the same chip.