With Specific Isolation Means In Integrated Circuit Patents (Class 257/446)
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Publication number: 20030183831Abstract: According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.Type: ApplicationFiled: February 27, 2003Publication date: October 2, 2003Inventors: Masumi Taninaka, Hiroyuki Fujiwara, Susumu Ozawa, Masaharu Nobori
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Patent number: 6576940Abstract: In a semiconductor device having a solid state image sensing device of the present invention, a p-type well region 2a in which a plurality of unit cells, each having a photodiode PD, are formed and a p-type well region 2b in which a peripheral circuit element is formed are installed in a separated manner. Thus, it is possible to prevent a hot carrier, transition metals, etc. within the peripheral circuit region from invading the pixel region more effectively. Consequently, it becomes possible to provide a semiconductor device having a solid state image sensing device and a manufacturing method thereof, which can improve the pixel characteristic.Type: GrantFiled: January 25, 2001Date of Patent: June 10, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Atsushi Maeda
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Patent number: 6563187Abstract: The present invention relates to a CMOS (Complementary Metal Oxide Silicon) image sensor; and, more particularly, to an image sensor integrated into one chip, together with a memory. The CMOS image sensor according to the present invention comprises: a pixel array formed on a chip, having a plurality of unit pixels; a logic circuit formed on the chip to process signals form the pixel array; and a memory formed on the chip to store outputs from the logic circuit, wherein the pixel array, the logic circuit and the memory are isolated from each other by insulating layers, whereby the pixel array, the logic circuit and the memory are integrated on the same chip.Type: GrantFiled: June 29, 1999Date of Patent: May 13, 2003Assignee: Hynix Semiconductor Inc.Inventor: Sang Hoon Park
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Patent number: 6553157Abstract: In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.Type: GrantFiled: March 7, 2002Date of Patent: April 22, 2003Assignee: Infineon Technologies AGInventors: Thomas Schultz, Wolfgang Rösner, Lothar Risch
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Patent number: 6545335Abstract: Semiconductor devices in an optoelectronic integrated circuit are electrically isolated from each other by using planar lateral oxidation to oxidize a buried semiconductor layer vertically separating the semiconductor devices.Type: GrantFiled: December 27, 1999Date of Patent: April 8, 2003Assignee: Xerox CorporationInventors: Christopher L. Chua, Philip D. Floyd, Thomas L. Paoli, Decai Sun
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Publication number: 20030057509Abstract: A light-emitting array can be driven by a matrix-type driving operation. When the packaging density of light-emitting elements is to be increased, the width of the element-separating region should be made narrower. The element-separating region extends over a considerable distance and therefore is apt to be adversely affected by particles. This tends to prevent formation of a good element-separating region, lowering manufacturing yield. An n-side electrode is arranged close to a predetermined number of LEDs. An element-separating region is formed to surround the LEDs and the n-side electrode, thereby defining a plurality of n-type semiconductor blocks. The element-separating region has a first portion that extends in a direction parallel to the line of the LEDs aligned and a second portion that extend between adjacent blocks. The first portion is wider than the second portion.Type: ApplicationFiled: September 23, 2002Publication date: March 27, 2003Applicant: Oki Data CorporationInventors: Masumi Taninaka, Masaharu Nobori, Mitsuhiko Ogihara
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Patent number: 6504225Abstract: Various embodiments of a circuit device for detecting the presence of unwanted conductor structures in insulation structure seams and methods of making the same are provided. In one aspect, a circuit device is provided that includes an insulating structure positioned on a substrate and a first conductor structure that has a first member positioned on the insulating structure. A second conductor structure is provided that has a second member positioned on the insulating structure. The second member projects toward the first conductor structure and the first member projects toward the second conductor structure, but the first and second conductor structures are not in physical contact. A current flowing between the first and second conductor structures when a bias is applied between the first and second conductor structures is indicative of a third conductor structure present on the insulating structure and contacting the first and second members.Type: GrantFiled: April 18, 2001Date of Patent: January 7, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Michael McCarthy, David E. Cooper, Denise C. Sale
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Patent number: 6492702Abstract: A circuit-incorporating light receiving device comprises a first semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a diffusion region of the second conductivity type, provided in a first portion of the second semiconductor layer of the first conductivity type, a circuit element provided in the first portion of the first semiconductor layer of the first conductivity type and a second portion of the second semiconductor layer of the first conductivity type. The second semiconductor layer of the first conductivity type and the diffusion region of the second conductivity type form a light detection photodiode portion, and the diffusion region of the second conductivity type has a diffusion depth less than or equal to a penetration depth of short-wavelength signal light.Type: GrantFiled: March 29, 2001Date of Patent: December 10, 2002Assignee: Sharp Kabushiki KaishaInventors: Toshihiko Fukushima, Masaru Kubo, Shigeki Hayashida
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Patent number: 6483163Abstract: A photoelectric conversion device comprises a semiconductor substrate, a same-dopant-type semiconductor layer, a photodiode having a charge-accumulation region, a JFET (which has a gate region, a source region, a channel region, and a drain region, the drain region electrically connected to the substrate 100), a transfer gate for transferring a charge from the photodiode to the gate region, and a reset drain having a charge-drain region for draining excess charges generated by the photodiode, the reset drain also controlling the electric potential of the gate region. Two overflow-control regions are included, one at the boundary between the charge-accumulation region and the charge-drain region within the device, one at the boundary between the charge-accumulation region and the charge-drain region of an adjacent device.Type: GrantFiled: December 4, 2000Date of Patent: November 19, 2002Assignee: Nikon CorporationInventors: Tadao Isogai, Satoshi Suzuki
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Patent number: 6472718Abstract: A semiconductor device includes an electrically conductive III-V doped semiconductor substrate of a first conduction type, a photodiode array having photodiode structures disposed on the III-V doped semiconductor substrate, a first III-V doped semiconductor layer of a second conduction type disposed between the photodiode structures and the III-V doped semiconductor substrate, etching trenches disposed on the III-V doped semiconductor substrate, each of the trenches having inner sides, the inner sides having an insulation layer and a metallization layer for electrically connecting the photodiode structures in series, the metallization layer disposed on the insulation layer, and partition lines separating each of the photodiode structures from others of the photodiode structures for producing an individual photodiode structure when the array is cut through the first III-V doped semiconductor layer along the partition lines.Type: GrantFiled: February 12, 2001Date of Patent: October 29, 2002Assignee: Siemens AktiengesellschaftInventor: Alfred Lell
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Patent number: 6465861Abstract: A radiation imager is disclosed that is resistant to degradation due to moisture by either contact pad corrosion, guard ring corrosion or by photodiode leakage. A contact pad of a large area imager is disclosed that is formed into three distinct and electrically connected regions. The resulting structure of the contact pad regions forms reliable contact that is resistant to corrosion damage. Also disclosed is a data line of an imager, or a display, the resistance of which is reduced by patterning an aluminum (Al) line on top of a transistor island structure, with the formed data line preferably being encapsulated. In addition, a guard ring having first and second regions and photosensitive element are disclosed. The second region comprises an electrical contact between ITO and underlying metal and a second tier which acts as a moisture barrier and is preferably disposed at the corner of the guard ring and separated from the contact pads of the imager in such a manner as to minimize corrosion.Type: GrantFiled: December 22, 1999Date of Patent: October 15, 2002Assignee: General Electric CompanyInventors: Jianqiang Liu, Ching-Yeu Wei, Robert Forrest Kwasnick
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Patent number: 6465862Abstract: Semiconductor photo sensor and semiconductor wafer processing designs are disclosed. The disclosed designs provide significantly improved photo sensor performance within the framework of a CMOS process. CMOS compatible fabrication procedures are presented, that enable tailoring of the 3-dimensional doping profile and defect structure within a photo sensor, to optimize light detection efficiency and minimize noise from dark current.Type: GrantFiled: October 5, 1999Date of Patent: October 15, 2002Inventor: Brannon Harris
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Patent number: 6462365Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.Type: GrantFiled: November 6, 2001Date of Patent: October 8, 2002Assignee: OmniVision Technologies, Inc.Inventors: Xinping He, Chih-huei Wu, Tiemin Zhao
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Patent number: 6455766Abstract: A device, having circuits formed thereon, comprises a circuit including a frequency generator for generating a detectable radio frequency energy when powered and a power generator, coupled to the frequency generator, for generating power when exposed to light.Type: GrantFiled: April 11, 2001Date of Patent: September 24, 2002Assignee: International Business Machines CorporationInventors: Donald J. Cook, Edward J. Nowak, Minh H. Tong
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Patent number: 6445048Abstract: A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode. The regions have a second conduction type, are disposed between the transistor configuration and the substrate edge, and extend from the substrate surface into the substrate and surround the transistor configuration. At least two adjacent insulating trench regions are disposed between the regions and extend from the substrate surface into the substrate for isolating the doped regions from one another. The trenches may have a smaller depth than the doped regions. A method for fabricating a semiconductor configuration includes providing a substrate having a first conduction type and producing regions in the substrate by introducing a dopant. The regions have a second conduction type.Type: GrantFiled: September 7, 2000Date of Patent: September 3, 2002Assignee: Infineon Technologies AGInventor: Frank Pfirsch
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Publication number: 20020117728Abstract: A microelectromechanical system is fabricated from a substrate having a handle layer, a silicon sacrificial layer and a device layer. A micromechanical structure is etched in the device layer and the underlying silicon sacrificial layer is etched away to release the micromechanical structure for movement. One particular micromechanical structure described is a micromirror.Type: ApplicationFiled: August 3, 2001Publication date: August 29, 2002Inventors: Timothy J. Brosnihhan, Michael W. Judy
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Patent number: 6433374Abstract: A photodiode converts light incident thereon into an electric signal by a junction between an N-type epitaxial layer and a P-type epitaxial layer with a sufficiently small junction capacitance. The photodiode is surrounded by a P+-type buried isolating diffused layer and a P-type isolating diffused layer, and thus is electrically separated from a signal processing circuit including a MOS transistor.Type: GrantFiled: October 29, 2001Date of Patent: August 13, 2002Assignee: Sharp Kabushiki KaishaInventors: Naoki Fukunaga, Kazuhiro Natsuaki
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Patent number: 6423993Abstract: A solid-state image-sensing device has pn-junction sensor parts isolated corresponding to pixels by a device isolation layer. The solid-state image-sensing device includes a first-conductivity-type second semiconductor well region formed between a first-conductivity-type first semiconductor well region and the device isolation layer. When the device is operating, a depletion layer of each sensor part spreads to the first semiconductor well region, which is beneath each of the sensor parts.Type: GrantFiled: February 7, 2000Date of Patent: July 23, 2002Assignee: Sony CorporationInventors: Ryoji Suzuki, Takahisa Ueno, Hirofumi Sumi, Keiji Mabuchi
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Publication number: 20020070416Abstract: An array of photodiodes in series on a common semi-insulating substrate has a non-conductive buffer layer between the photodiodes and the semi-insulating substrate. The buffer layer reduces current injection leakage between the photodiodes of the array and allows optical energy to be converted to high voltage electrical energy.Type: ApplicationFiled: December 8, 2000Publication date: June 13, 2002Applicant: The Regents of the University of CaliforniaInventors: Jeffrey D. Morse, Gregory A. Cooper
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Patent number: 6396115Abstract: A detector layer for an optics module includes at least one diode having at least one sloped sidewall. At least one isolation region may be formed adjacent to the at least one sloped sidewall to isolate the at least one diode. Conducting material is disposed on at least a portion of the top surface of the diode. An insulating material is disposed on at least a portion of the diode and extends to the conducting material. A metal is disposed on at least a portion of the insulating material and at least a portion of the conducting material such that the metal is coupled to the conducting material.Type: GrantFiled: May 21, 1999Date of Patent: May 28, 2002Assignee: Seagate Technology LLCInventors: Edward C. Gage, Ronald E. Gerber, George R. Gray, Steve C. Dohmeier, James E. Durnin, Daniel E. Glumac, Tim Gardner, Jill D. Berger, John H. Jerman, John F. Heanue, Ghamin A. Al-Jumaily
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Patent number: 6392282Abstract: An APD is provided, said APD having an N-type first buried region (cathode) formed on a P-type substrate, and P-type first, second layer, and fourth semiconductor region (anode) formed thereon. A vertical type PNP transistor is provided, said vertical type PNP transistor having the N-type first buried region formed on the substrate, a P-type first buried region and a P-type second semiconductor layer (collector) formed on the P-type first semiconductor layer, and an N-type second semiconductor region (base) in the P-type second semiconductor layer. A vertical type NPN transistor is provided, said vertical type NPN transistor having an N-type second buried region and an N-type first semiconductor region (collector) in the substrate, and a P-type third semiconductor region (base) in the N-type first semiconductor region. An NMOS is provided in the surface of the P-type second semiconductor layer. A PMOS is provided in the surface of the N-type second semiconductor region.Type: GrantFiled: July 28, 2000Date of Patent: May 21, 2002Assignee: Hamamatsu Photonics K.K.Inventors: Masanori Sahara, Takashi Suzuki
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Patent number: 6392308Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.Type: GrantFiled: February 28, 2001Date of Patent: May 21, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kuniharu Muto, Atsushi Nishikizawa, Jyunichi Tsuchiya, Toshiyuki Hata, Nobuya Koike, Ichio Shimizu
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Patent number: 6384313Abstract: A solar cell module comprises a plurality of unit cells connected in series, each of the unit cells comprising in this order an electrode, a first semiconductor layer having a first conductivity type and a second semiconductor layer having a second conductivity type. The electrode has a region not covered with the first semiconductor layer. The second semiconductor layer has a main region and a subregion which are separated by a groove. The main region of the second semiconductor layer in one unit cell is electrically connected to the region of the electrode not covered with the first semiconductor layer in another unit cell adjacent to the one unit cell. The region of the electrode not covered with the first semiconductor layer in the one unit cell is electrically connected to the subregion of the second semiconductor layer in the another unit cell. With this structure it is possible to simplify the formation of a bypass diode invention therefore provide solar cell module with high reliability at a low cost.Type: GrantFiled: February 23, 2001Date of Patent: May 7, 2002Assignee: Canon Kabushiki KaishaInventors: Katsumi Nakagawa, Shoji Nishida, Yukiko Iwasaki
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Patent number: 6344666Abstract: In an amplifier-type solid-state image sensor device, each unit cell comprises a photoconverter and a signal scanning circuit in an image sensing region on a semiconductor substrate, a metal film has an opening region for defining regions where light is radiated in the photoconverters of the unit cells, and a center position of the opening region of the metal film is displaced to the side of the center of the image sensing region with respect to a center portion of the photoconverter, so that the amount of light entering the center of the semiconductor chip and the peripheral portions of the semiconductor chip can be made equal, thereby obtaining substantially the same sensitivity at the center and peripheral portions of the semiconductor chip.Type: GrantFiled: September 29, 1999Date of Patent: February 5, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Yamaguchi, Hisanori Ihara, Hiroaki Ishiwata, Akiko Mori
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Metal clad ridge waveguide (“MCRW”) laser semiconductor structure with doped semiconductor substrate
Patent number: 6339233Abstract: A semiconductor device comprises an electrically conductive III-V semiconductor substrate which has mutually opposite first and second main surfaces. At least one pn junction, reverse biased during operation of the semiconductor device, is disposed above the first main surface. At least one functional semiconductor structure is disposed above the at least one pn junction. The functional semiconductor structure is electrically insulated from the second main surface of the III-V semiconductor substrate.Type: GrantFiled: September 30, 1997Date of Patent: January 15, 2002Assignee: Siemens AktiengesellschaftInventor: Alfred Lell -
Patent number: 6323985Abstract: Through silicon optical modulators (TSOM) formed in a silicon integrated circuit comprise a grating array of MOSFET elements. The TSOM's provide optical phase shifts from different areas which contrast with one another coherently. Phase modulated optical beams reflected from the grating interfere with one another and allow the modulation to be easily detected off-chip. In one embodiment, a two dimensional array has a gate structure which is used to modulate a light beam by forming accumulation layers. In another embodiment, a one dimensional array is formed using parallel gate strips, where alternate gates are used as reference reflectors.Type: GrantFiled: December 30, 1998Date of Patent: November 27, 2001Assignee: Intel CorporationInventor: Timothy J. Maloney
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Patent number: 6313484Abstract: A circuit-integrated light-receiving device of the present invention includes: a semiconductor substrate of a first conductivity type; a first semiconductor crystal growth layer of the first conductivity type provided on a surface of the semiconductor substrate, wherein the first semiconductor crystal growth layer includes a first portion whose impurity concentration gradually decreases in a direction away from the surface of the semiconductor substrate and a second portion located in a first region above the first portion whose impurity concentration distribution is uniform in a depth direction; a buried diffusion layer of the first conductivity type located in a second region which is above the first portion of the first semiconductor crystal growth layer and does not overlap the first region; a second semiconductor crystal growth layer of a second conductivity type which is provided across a surface of the first semiconductor crystal growth layer and a surface of the buried diffusion layer; and a separatioType: GrantFiled: December 28, 1999Date of Patent: November 6, 2001Assignee: Sharp Kabushiki KaishaInventors: Isamu Ohkubo, Masaru Kubo, Naoki Fukunaga, Takahiro Takimoto, Mutsumi Oka, Toshimitsu Kasamatsu
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Patent number: 6271537Abstract: Quantum-well sensors having an array of spatially separated quantum-well columns formed on a substrate. A grating can be formed increase the coupling efficiency.Type: GrantFiled: November 19, 1999Date of Patent: August 7, 2001Assignee: California Institute of TechnologyInventors: Sarath D. Gunapala, Sumith V. Bandara, John K. Liu, Daniel W. Wilson
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Patent number: 6252286Abstract: When a light is irradiated on and near separated portions of a light-receiving element, a frequency characteristic grows worse. According the present invention, a light-receiving element is formed on a semiconductor substrate by a junction portion of a first conductivity-type first semiconductor portion and a second conductivity-type second semiconductor portion, i.e. p-n junction. Then, a second conductivity-type separating region is formed on a part of the first semiconductor portion. With application of a reverse-bias voltage lower than a reverse-bias voltage applied to the junction portion when the light-receiving element is driven, the first semiconductor portion is separated into a plurality of portions by a spread of a depletion layer from the junction portion comprising the light-receiving element and the junction portion comprised of the separating region, whereby the frequency characteristic is improved.Type: GrantFiled: March 9, 1999Date of Patent: June 26, 2001Assignee: Sony CorporationInventor: Chihiro Arai
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Patent number: 6248948Abstract: A solar cell module comprises a plurality of unit cells connected in series, each of the unit cells comprising in this order an electrode, a first semiconductor layer having a first conductivity type and a second semiconductor layer having a second conductivity type. The electrode has a region not covered with the first semiconductor layer. The second semiconductor layer has a main region and a subregion which are separated by a groove. The main region of the second semiconductor layer in one unit cell is electrically connected to the region of the electrode not covered with the first semiconductor layer in another unit cell adjacent to the one unit cell. The region of the electrode not covered with the first semiconductor layer in the one unit cell is electrically connected to the subregion of the second semiconductor layer in the another unit cell. With this structure, it is possible to simplify the formation of a bypass diode and therefore provide a solar cell module with high reliability at a low cost.Type: GrantFiled: May 13, 1999Date of Patent: June 19, 2001Assignee: Canon Kabushiki KaishaInventors: Katsumi Nakagawa, Shoji Nishida, Yukiko Iwasaki
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Patent number: 6218691Abstract: The present invention is to provide an image sensor, including: a semiconductor substrate of a first conductive type: a peripheral circuit formed on a first region of the semiconductor substrate, wherein a ground voltage level is applied to the first region; a unit pixel array having a plurality of unit pixels formed on a second region of the semiconductor substrate, wherein the first region is isolated from the second region and wherein a negative voltage level is applied to the second region; and a negative voltage generator for providing the negative voltage for the second region.Type: GrantFiled: June 29, 1999Date of Patent: April 17, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: In Sool Chung, Seong Dong Kim
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Publication number: 20010000068Abstract: A photoelectric conversion device comprises a semiconductor substrate, a same-dopant-type semiconductor layer, a photodiode having a charge-accumulation region, a JFET (which has a gate region, a source region, a channel region, and a drain region, the drain region electrically connected to the substrate 100), a transfer gate for transferring a charge from the photodiode to the gate region, and a reset drain having a charge-drain region for draining excess charges generated by the photodiode, the reset drain also controlling the electric potential of the gate region. Two overflow-control regions are included, one at the boundary between the charge-accumulation region and the charge-drain region within the device, one at the boundary between the charge-accumulation region and the charge-drain region of an adjacent device.Type: ApplicationFiled: December 4, 2000Publication date: March 29, 2001Inventors: Tadao Isogai, Satoshi Suzuki
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Patent number: 6198150Abstract: A quick, deep, clean two step trench process for an SOI/bonded wafer substrate 100 is disclosed. A first isotropic plasma etch using SF6 is made through an opening 40 in the photoresist layer on device layer 16. A second anisotropic plasma etch using SF6 and C12 stops on the isolation/bond oxide layer 14. The bottom of the trench 60 is overetched to form cavities 50 on the isolation/bond oxide layer 14 without removing a substantial portion of that layer.Type: GrantFiled: March 10, 1999Date of Patent: March 6, 2001Assignee: Intersil CorporationInventor: Peter Victor Gelzinis
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Patent number: 6184100Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N− type epitaxial layer, P− type epitaxial layer, P+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P− epitaxial layer, the efficiency in density control at the time of P− type epitaxial growth can be improved.Type: GrantFiled: June 13, 1997Date of Patent: February 6, 2001Assignee: Sony CorporationInventor: Chihiro Arai
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Patent number: 6150708Abstract: An integrated circuit employing both sides of a base substrate or wafer and a method of making the same are provided. In one aspect, the integrated circuit includes a base substrate that has a first side and a second side opposite the first side. The first side has a first semiconductor layer and a first isolation structure positioned thereon wherein the first side surrounds the first semiconductor layer. The second side has a second semiconductor layer and a second isolation structure positioned thereon wherein the second isolation structure surrounds the second semiconductor layer. A first circuit device is positioned on the first semiconductor layer. A second circuit device is positioned on the second semiconductor layer. The method enables simultaneous processing of both sides of a given wafer. Fabrication efficiency is increased through higher throughput and much higher yields per wafer.Type: GrantFiled: November 13, 1998Date of Patent: November 21, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. Jim Fulford, Charles E. May
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Patent number: 6150676Abstract: A MOS type image sensor has an image area that consists of a matrix of pixels and a peripheral circuitry area that drives the image area.Type: GrantFiled: March 11, 1999Date of Patent: November 21, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Michio Sasaki
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Patent number: 6133615Abstract: Photodiode arrays are formed with close diode-to-diode spacing and minimized cross-talk between diodes in the array by isolating the diodes from one another with trenches that are formed between the photodiodes in the array. The photodiodes are formed of spaced regions in a base layer, each spaced region having an impurity type opposite to that of the base layer to define a p-n junction between the spaced regions and the base layer. The base layer meets a substrate at a boundary, with the substrate being much more heavily doped than the base layer with the same impurity type. The trenches extend through the base layer and preferably into the substrate. Minority carriers generated by absorption of light photons in the base layer can only migrate to an adjacent photodiode through the substrate. The lifetime and the corresponding diffusion length of the minority carriers in the substrate is very short so that all minority carriers recombine in the substrate before reaching an adjacent photodiode.Type: GrantFiled: April 13, 1998Date of Patent: October 17, 2000Assignee: Wisconsin Alumni Research FoundationInventors: Henry Guckel, Shamus P. McNamara
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Patent number: 6118142Abstract: A CMOS sensor structure and method of manufacture that includes the fabrication of a special shallow trench isolation structure. Besides isolating the active region for forming the CMOS sensor device, the shallow trench isolation structure has a special reflective plug embedded inside capable of reflecting incoming light onto the sensitive region of the CMOS sensor. Hence, the interactive length of incoming light with the light sensitive region can be increased, thereby increasing the contrast ratio and light sensitivity of the CMOS sensor.Type: GrantFiled: November 9, 1998Date of Patent: September 12, 2000Assignee: United Microelectronics Corp.Inventors: Ming-I Chen, Yung-Chieh Fan
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Patent number: 6114716Abstract: Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.Type: GrantFiled: April 25, 1997Date of Patent: September 5, 2000Assignee: The Whitaker CorporationInventors: Timothy Edward Boles, Joel Lee Goodrich
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Patent number: 6111304Abstract: According to the present invention, a semiconductor device, and method for producing the same, is provided comprising: a resistance component formed in a component active region enclosed by a component separating-insulating layer on a semiconductor base; one pair of first diffusion layers containing a high concentration of impurities which are provided at both ends of the component active region; silicide layer adhering to a first diffusion layer; second diffusion layer containing a low concentration of impurities which is provided in the component active region between the pair of first diffusion layers; wherein a first diffusion layer and silicide layer comprise the terminal areas of the resistance component, and the second diffusion layer comprises a resistance member area of the resistance component.Type: GrantFiled: August 26, 1997Date of Patent: August 29, 2000Assignee: NEC CorporationInventor: Yasuhiro Sonoda
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Patent number: 6100570Abstract: A semiconductor device is provided wherein carrier flows in a monocrystal silicon film having low oxygen concentration. As for a structure of the semiconductor device, a single semiconductor element or a plurality of semiconductor elements are provided on the monocrystal silicon film having low oxygen concentration which is provided on a backing substrate of which at least the surface is made of an insulating material. The backing substrate is provided so that the semiconductor device gets mechanical destructive strength. The insulating material is provided so that some particles never transfers from the backing substrate to the semiconductor film. The silicon film has-low oxygen concentration so that the lifetime of a minor carrier lengthens.Type: GrantFiled: October 19, 1998Date of Patent: August 8, 2000Assignee: Seiko Instruments Inc.Inventor: Yutaka Saito
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Patent number: 6051867Abstract: An integrated circuit sensor structure. The integrated circuit sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A dielectric layer is adjacent to the interconnect structure. The dielectric layer includes a planar surface, and conductive dielectric vias which pass through the dielectric layer and are electrically connected to the interconnect vias. The dielectric layer further includes an interlayer planarization dielectric layer adjacent to the interconnect structure, and a passivating layer adjacent to the interlayer planarization dielectric layer. The integrated circuit sensor structure further includes sensors adjacent to the dielectric layer. The interconnect vias and the dielectric vias electrically connect the electronic circuitry to the sensors.Type: GrantFiled: May 6, 1999Date of Patent: April 18, 2000Assignee: Hewlett-Packard CompanyInventors: Jeremy A. Theil, Gary W. Ray, Frederick A. Perner, Min Cao
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Patent number: 6049117Abstract: A light-receiving element includes a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type which is formed in a predetermined region on a surface of the semiconductor substrate of the first conductivity type; and at least one semiconductor region of the first conductivity type which is formed so as to extend from an upper surface of the first semiconductor layer of the second conductivity type to the surface of the semiconductor substrate of the first conductivity type, thereby dividing the first semiconductor layer of the second conductivity type into a plurality of semiconductor regions of the second conductivity type. In the light-receiving element, a specific resistance of the semiconductor substrate of the first conductivity type is set in a predetermined range such that a condition Xd.gtoreq.Type: GrantFiled: September 20, 1996Date of Patent: April 11, 2000Assignee: Sharp Kabushiki KaishaInventors: Naoki Fukunaga, Masaru Kubo
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Patent number: 6037643Abstract: Circuitry is employed to provide an array of photoelements for generating an electrical signal from light energy. The circuit is essentially comprised of a plurality of photoelements including a light-receiving portion, which may include a phototransistor for receiving light and generating electrical energy therefrom, and a non-light-receiving portion, which may include amplification circuitry for properly biasing the phototransistor base and for amplifying the light signal. Within the array, geometric centers of vertically and horizontally adjacent phototransistors are equidistant from one another to form a symmetrical array of photoelements. A relatively high fill factor is achieved by an efficient, symmetrical layout of the photoelements within the array. One main advantage of the high fill factor of the symmetrical array is that it generates a greater light signal than related designs, which eliminates the need for optical magnification of pixels on an original sheet of paper.Type: GrantFiled: February 17, 1998Date of Patent: March 14, 2000Assignee: Hewlett-Packard CompanyInventor: Derek L. Knee
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Patent number: 6028330Abstract: A sensor device has a field oxide layer deposited over a substrate. The field oxide layer has opposing sharp edges that define a window. A sensor is formed in the window with a distance between the sensor and each sharp edge that defines the window. The distance forms a gap that reduces the effects of the sharp edges on the sensor, thereby reducing the current leakage from the sensor. In addition, a protective layer may be disposed over the distance and the sharp edges of the field oxide layer to further protect the sharp edges from damage that may be caused from further processing.Type: GrantFiled: August 4, 1998Date of Patent: February 22, 2000Assignee: Dyna Image CorporationInventors: Sheng-Ti Lee, Chi-Ting Shen, Chi-Fin Chen, Chien-I Fu, Chao-Jung Chen, Wei-Jung Chen
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Patent number: 6015998Abstract: In an optical material formed of strips of laminated methods, through channels or "trenches" are produced in at least one of the lamination materials in a manner that the material will then consist of "stiff islands" interspersed with flexible regions created by the properly created through channels. The trenching alows a strip to become piece-wise alignable, and also makes it flexible enough to bond it in alignment in a laminate, yet continuous enough to be handled as one sheet for initial placement. "Chain-like" capability can be provided by making the sheet into a form resembling a jig-saw puzzle where the chances of the individual pieces slipping apart is reduced using narrow, slanted trenches. Alternatively, "springy" flexibility can be provided by forming relatively long, thin, bent strips of material that support the islands of continuous sheet. The islands are thus allowed to move two dimensionally relative to each other.Type: GrantFiled: December 17, 1997Date of Patent: January 18, 2000Assignee: Lucent Technolgies, Inc.Inventors: Ernest Eisenhardt Bergmann, Gustav Edward Derkits, Jr.
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Patent number: 6005278Abstract: A divided photodiode includes a semiconductor substrate; a semiconductor layer formed on a surface of the semiconductor substrate; and a plurality of isolating diffusion regions formed in a plurality of regions in the semiconductor layer so as to respectively extend from a surface of the semiconductor layer opposite to the other surface thereof in contact with a surface of the semiconductor substrate and to reach regions under the surface of the semiconductor substrate, thereby dividing the semiconductor layer into at least three semiconductor regions. A first buried diffusion region is further formed under the other isolating diffusion regions except for a particular one located in an isolating section in a combination of a plurality of the semiconductor regions which are adjacent to each other via the isolating section, and a depletion of the semiconductor substrate in a region under the other isolating diffusion region by the application of a reverse bias thereto is suppressed.Type: GrantFiled: January 23, 1998Date of Patent: December 21, 1999Assignee: Sharp Kabushiki KaishaInventors: Naoki Fukunaga, Takahiro Takimoto, Masaru Kubo
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Patent number: 5994751Abstract: In an SOI substrate, an active zone is completely surrounded by a trench filled with insulating material. Disposed adjacent to the trench is a first doped zone which is formed, in particular, by out-diffusion from a doped layer disposed on the wall of the trench. The first doped zone and a second doped zone form a p-n junction of a photodiode.Type: GrantFiled: January 29, 1998Date of Patent: November 30, 1999Assignee: Siemens AktiengesellschaftInventor: Klaus-Gunter Oppermann
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Patent number: 5990505Abstract: A highly reliable solid-state image pickup device with one- or two-dimensionally arranged connecting portions, capable of avoiding corrosion of wirings resulting from chipping of the substrates and eliminating image defect, is achieved by arranging plural substrates, each bearing a plurality of image taking elements, in a planar manner on a supporting substrate and filling the connecting portions of thus arranged substrates with an organic or inorganic material, of which content in chlorine or in each of sodium and potassium does not exceed 200 ppm.Type: GrantFiled: February 20, 1998Date of Patent: November 23, 1999Assignee: Canon Kabushiki KaishaInventor: Kenji Kajiwara
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Patent number: 5982011Abstract: A photodiode structure augmented with active area photosensitive regions is used for detecting impinging radiation. The photodiode includes a semiconductor base layer doped with impurities of a first carrier type, a field oxide layer disposed upon the base layer with an opening formed therethrough, a plurality of auxiliary oxide layers wherein each is separately disposed upon the base layer, and a semiconductor diffusion layer doped with impurities of a second carrier type arranged upon the base layer and in contact with the oxide layers. When the photodiode is electrically energized, a plurality of integral photosensitive regions is created within the depletion region to facilitate the detection of impinging radiation at an increased quantum efficiency.Type: GrantFiled: November 24, 1997Date of Patent: November 9, 1999Assignee: STMicroelectronics, Inc.Inventors: Alexander Kalnitsky, Marco Sabatini