Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, an isolation layer, and a guard ring layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer to be joined to the second semiconductor layer. The isolation layer surrounds a periphery of the third semiconductor layer and is deeper than the third semiconductor layer. The guard ring layer is provided between the third semiconductor layer and the isolation layer, adjacent to the third semiconductor layer, and deeper than the third semiconductor layer.

Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

Abstract: A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.

Abstract: A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

Abstract: A semiconductor device includes: a plurality of first trenches formed inside a plurality of active regions; a plurality of buried gates configured to partially fill insides of the plurality of the first trenches; a plurality of second trenches formed to be extended in a direction crossing the plurality of the buried gates; and a plurality of buried bit lines configured to fill the plurality of the second trenches.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

Abstract: A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer.

Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

Abstract: A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF2, B18H22, C16H10, Si, Ge or As as an implant species to amorphize the silicon, and by annealing the amorphized silicon to re-crystallize the amorphized silicon.

Abstract: In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.

Abstract: A substrate diode of an SOI device may be formed on the basis of contact regions in an early manufacturing stage, i.e., prior to patterning gate electrode structures of transistors, thereby imparting superior stability to the sensitive diode regions, such as the PN junction. In some illustrative embodiments, only one additional deposition step may be required compared to conventional strategies, thereby providing a very efficient overall process flow.

Abstract: The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.

Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.

Abstract: Semiconductor-on-insulator (SOI) devices and associated methods are provided. In one aspect, for example, a method for making a SOI device can include forming a device layer on a front side of a semiconductor layer, bonding a first substrate to the front side of the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a second substrate to the processed surface. In some aspects, the method can further include removing the first substrate from the front side to expose the device layer. In one aspect, forming the device layer can include forming optoelectronic circuitry at the front side of the semiconductor layer.

Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Abstract: Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed.

Abstract: Novel integrated circuits (ICs) on ceramic wafers and methods of fabricating ICs on ceramic wafers are disclosed. In one embodiment, an active layer comprising IC circuit components is coupled to a selected wafer comprising a ceramic. A surface of the ceramic is processed to enable direct bonding between the selected wafer and the active layer. Another embodiment comprises an active layer comprising IC circuit components and a selected wafer comprising a ceramic and an intermediate layer. A surface of the intermediate layer is processed to enable direct bonding. In some embodiments the intermediate layer comprises a material selected from the following: silicon carbide, silicon dioxide, silicon nitride and diamond. Methods of fabrication are described, wherein layer transfer technology is employed to form active layers and to couple the active layers to the selected wafers.

Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.

Abstract: A polysilicon-filled isolation trench in a substrate is effective to isolate adjacent semiconductor devices from one another. A silicon nitride cap is provided to protect the polysilicon in the isolation trench from subsequent field oxidation. The cap has lateral boundaries that extend between the side boundaries of the polysilicon and the sidewalls of the trench. Subsequent field oxide regions formed adjacent to the trench establish a gap dimension from the substrate to a top surface of the field oxide regions adjacent to the polysilicon side boundaries that is no less than half of the field oxide thickness.

Abstract: A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

Abstract: A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer.

Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.

Abstract: A region divided substrate includes a substrate, a plurality of trenches, a conductive layer, and an insulating member. The substrate has a first surface and a second surface opposed to each other. The trenches penetrate the substrate from the first surface to the second surface and divide the substrate into a plurality of partial regions. The conductive layer is disposed on a sidewall of each of the trenches from a portion adjacent to the first surface to a portion adjacent to the second surface. The conductive layer has an electric conductivity higher than an electric conductivity of the substrate. The insulating member fills each of the trenches through the conductive layer.

Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.

Abstract: A method includes forming one or more trenches in a substrate; lining the one or more trenches with a dielectric liner; filling the one or more trenches with a conductive electrode to form one or more trench electrodes; forming a transistor layer on the substrate; connecting each of the one or more trench electrodes to at least one access transistor in the transistor layer; and thinning the substrate to expose at least a portion of each of the trench electrodes.

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Abstract: Disclosed is a method of forming a structure and a resulting structure. The method includes providing a semiconductor substrate; forming a first opening to a first depth in the semiconductor substrate; amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized semiconductor sidewalls in a lower portion of the first opening; enlarging only the lower portion of the first opening using an etch process that is selective to the unamorphized semiconductor sidewalls; filling the first opening with an insulator material to form a deep trench isolation (DTI) structure and implanting a first well region and a second well region into the semiconductor substrate. The first well and the second well are separated from one another by the enlarged lower portion of the first opening. In the structure sidewalls of a top portion of a DTI and sidewalls of an STI are formed of doped, re-crystallized silicon.

Abstract: A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.

Abstract: Semiconductor devices using a group III-V material, and methods of manufacturing the same, include a substrate having a groove, a group III-V material layer filling in the groove and having a height the same as a height of the substrate, a first semiconductor device on the group III-V material layer, and a second semiconductor device on the substrate near the groove. The group III-V material layer is spaced apart from inner side surfaces of the groove.

Abstract: Methods and structure are provided to facilitate isolation of respective ground plane regions in an SOTB semiconductor device. In one aspect a shallow STI trench can be combined with Si:C or Si:C/SiGe layers to confine n-type and p-type regions. In a further aspect, Ge can be implanted at the bottom of a shallow STI trench and subsequently oxidized to form SiGe oxide thereby extending the effective isolation provided by the shallow STI trench. In an aspect, a shallow STI trench can be extended to expose an underlying layer of SiGe, wherein the SiGe is subsequently oxidized to extending the effective isolation provide by the shallow STI trench. Such aspects enable a shallow STI trench to be seamlessly filled while having an extended region of isolation.

Abstract: A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.

Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.

Abstract: A semiconductor device contains a first transistor including a single trench which is formed on a substrate between a source region and a drain region and a gate electrode which is formed in the single trench, a second transistor including at least two trenches which are formed on the substrate between a source region and a drain region and a gate electrode which is formed in the at least two trenches, and also contains a device isolation insulating which isolates the region in which the transistor is formed. The first transistor has first distance between the single trench and the device isolation insulating film and the second transistor has second distance between the adjoining trenches, such the first distance is less than the second distance in a gate width direction.

Abstract: To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR1), a second transistor region (TR2) arranged between the first side and TR1, and a dummy region on the first direction side of TR1. TR1 has a first channel forming region facing the first side. TR2 has a second channel forming region facing the first side. The first channel forming region has a non-facing region that is not facing the second channel forming region. The dummy region faces the non-facing region in the second direction.

Abstract: The present disclosure relates to a stacked body-contacted field effect transistor (FET) that includes multiple body-contacted FETs coupled in series and a lateral isolation band encircling a periphery of the multiple FETs. The multiple FETs include a first end FET having a first body, which is not directly connected to any body of any other of the multiple FETs, and a second end FET having a second body, which is not directly connected to any body of any other of the multiple FETs. The multiple FETs may include inner FETs that incorporate merged source-drains to save space. By keeping the bodies electrically separated from one another, the full benefits of body-contacting may be realized. However, by incorporating multiple FETs within a single lateral isolation band further saves space.

Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.

Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.

Abstract: A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region.

Abstract: A method of fabricating semiconductor devices is disclosed. The method comprises providing a wafer comprising a substrate with a plurality of epitaxial layers mounted on the substrate. Patterns are formed above the plurality of epitaxial layers remote from the substrate. A second substrate of a conductive metal is formed on the plurality of epitaxial layers remote from the substrate and between the patterns. The second substrate, the plurality of epitaxial layers and the substrate are at least partially encapsulated with a soft buffer material. The substrate is separated from the plurality of epitaxial layers at the wafer level and while the plurality of epitaxial layers are intact while preserving electrical and mechanical properties of the plurality of epitaxial layers by applying a laser beam through the substrate to an interface of the substrate and the plurality of epitaxial layers, the laser beam having well defined edges.

Abstract: Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.

Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.

Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

Abstract: A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

Abstract: A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.