Abstract: A semiconductor device comprises an interlayer insulation film, a wiring embedded in the interlayer insulation film and an air gap part formed between a side surface of the wiring and the interlayer insulation film.

Abstract: An integrated circuit, in which the influence of parasitic capacitance between a semiconductor substrate and a resistor and between the semiconductor substrate and a capacitor can be inhibited, and a DC-DC converter provided with the integrated circuit. A shielding layer of an n-type semiconductor is formed between a p-type semiconductor substrate and a resistor formed thereon and between the semiconductor substrate and a capacitor formed thereon. A point BOOT is connected to the shielding layer, at which an electric potential changes in the same way as a change in the reference potential of a functional circuit carrying out a specified operation by using the resistor and the capacitor.

Abstract: An integrated circuit structure includes a semiconductor substrate; and an interconnect structure overlying the semiconductor substrate. A solid metal ring is formed in the interconnect structure, with substantially no active circuit being inside the solid metal ring. The integrated circuit structure further includes a through-silicon via (TSV) having a portion encircled by the solid metal ring. The TSV extends through the interconnect structure into the semiconductor substrate.

Abstract: A semiconductor device includes a SOI (silicon on insulator) substrate having a first region and a second region, a multilayer wiring layer formed on the SOI substrate and having an insulating layer and a wiring layer alternately stacked in this order, a first inductor formed over the SOI substrate, and a second inductor formed over the SOI substrate and positioned above the first inductor.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.

Abstract: A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure.

Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.

Abstract: In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.

Abstract: A method for manufacturing a semiconductor includes forming an active region for an ESD device, an active region for a first polygate and the semiconductor, and a second polygate having a form of a blanket trench on a substrate, forming an interlayer dielectric layer including first and second insulating on the substrate, planarizing the interlayer dielectric layer, forming a contact pattern to open a portion of the interlayer dielectric layer over the first polygate, forming a first polygate trench by performing a first etch process with respect to the second insulating layer below the contact pattern, and performing a second etch process to remove the first insulating layer inside the first polygate trench and to remove the first insulating layer over the active region of the semiconductor other than the second polygate.

Abstract: When forming a trench in a porous low-K dielectric (such as an ILD) of a semiconductor device, a carbon-rich layer is formed in the sidewalls of the trench during trench etching. This carbon-rich layer may protect the trench from being excessively etched, which would otherwise form an undesirable hardmask undercut. The carbon-rich layer may be formed simultaneously with and during the etching process, by increasing the amount of carbon available to be absorbed by the ILD during the trench etching process. The existence of the extra available carbon may slow the etching of the carbon-enriched regions of the dielectric.

Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.

Abstract: A semiconductor package with an electromagnetic shield is disclosed. The semiconductor package includes two substrates (102, 202; 103, 203) and an electromagnetic shield (101, 201). Each substrate has at least one die (108, 208; 112, 212) provided thereon. The electromagnetic shield is disposed between the two substrates for shielding electromagnetic interference between adjacent dies of the two substrates. One of the two substrates defines a cavity (109, 209) for partially accommodating the electromagnetic shield. Accordingly, the overall vertical height and the volume of the semiconductor package are not increased, and the heat dissipation efficiency of the semiconductor package is enhanced.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.

Abstract: Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

Abstract: A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the testing of a circuit involving a transistor can also be costly, time consuming and a barrier towards efficient circuit development and testing. Accordingly, the present invention provides a pre-fabricated, general-purpose pattern comprising an array of conductive islands. The pattern is used as a source and a drain terminal for the formation of a thin-film transistor and as a conductive source for the formation of other electrical components upon the array.

Abstract: According to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer; a trench structure being formed within the first composite structure; and a second composite structure provided on the side walls of the trench structure, wherein the second composite structure includes a first isolation layer covering the part of the side walls formed by the semiconductor layer and formed by an upper part of the buried layer; and a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. A fourth source region is arranged adjacent to third sides of the first and second drain regions and a fifth source region is arranged adjacent to fourth sides of the first and second drain regions. First and second drain contacts are arranged in the first and second drain regions, respectively. At least two of the first, second, third, fourth and fifth source regions and the first and second drain regions communicate with at least two of the N plane-like metal layers.

Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

Abstract: The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity.

Abstract: This invention disclosed a kind of electrode picking up structure in LOCOS isolation process. The active region is isolated by local oxide of silicon (LOCOS). A pseudo buried layer under the bottom of LOCOS is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. This is achieved by deep trench contacts which etch through LOCOS and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency.

Abstract: Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via formed through the silicon epitaxial layer, which may electrically interconnect the first device and the second device. According to embodiments, a method for fabricating a semiconductor device may include forming a first device, forming a silicon epitaxial layer on and/or over the first device, forming a connection via through the silicon epitaxial layer, and forming a second device on and/or over the silicon epitaxial layer such that the second device may be electrically connected to the connection via.

Abstract: Electrically isolated, deep trench isolation (DTI) structures, are formed in a wafer, and a portion of the DTI structures are converted to electrically connected structures to provide a shielding function, or to provide connection to deep buried layers. In one aspect, DTI structures include a polysilicon filling over a liner layer disposed on the inner surface of a deep trench, the polysilicon is removed by isotropic etching, and the deep trench is re-filled with a conductive material. Alternatively, the polysilicon filling remains and a contact is formed to provide an electrical connection to the polysilicon. In another aspect, a deep trench is disposed in the wafer such that a lower portion thereof is located within a deep buried layer, and after the polysilicon is removed, an anisotropic etch removes a portion of the deep trench liner from the bottom of the deep trench, thereby allowing a tungsten deposition to make electrical contact with the deep buried layer.

Abstract: An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a semiconductor layer over a thermal conduction layer, forming an isolation region over the thermal conduction layer, and forming a thermal conduction region in the isolation region.

Abstract: An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone (2) in the first side of the substrate. A circuit component is situated in the doped active zone. A through silicon via extends between the second side and the first side, the via being electrically isolated from the substrate by an insulating layer. A buffer zone is situated between the insulating layer and the doped active zone. This buffer zone is positioned under a shallow trench isolation zone provided around the doped active zone. The buffer zone functions to reduce the electrical coupling between the through silicon via and the doped active zone.

Abstract: A semiconductor device includes a layered region (104) formed in a semiconductor substrate (101) of a first conductivity type, and an electrode pad (106) formed on the semiconductor substrate with an interlayer insulating film (105) interposed therebetween and placed above the layered region. The layered region includes a first impurity diffusion region (102), a second impurity diffusion region (103) formed on the first impurity diffusion region, and a third impurity diffusion region (102x) formed on the first impurity diffusion region and surrounding a periphery of the second impurity diffusion region. a conductivity type of the first impurity diffusion region and a conductivity type of the third impurity diffusion region are a second conductivity type, and a conductivity type of the second impurity diffusion region is the first conductivity type.

Abstract: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

Abstract: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

Abstract: Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.

Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

Abstract: In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented.

Abstract: A semiconductor device capable of restricting a void growth in a copper wiring. The semiconductor device comprises a semiconductor substrate, an insulation layer formed above the semiconductor substrate, a barrier metal layer that is a first damascene wiring buried in the insulation layer, defines the bottom face and the side faces, and also defines a first hollow part at the inner side, a copper wiring layer disposed in the first hollow part and defining a second hollow part at the inner side, a first damascene wiring disposed in the second hollow part and containing an auxiliary barrier metal layer separated from the barrier metal layer, and an insulating copper diffusion preventing film disposed on the first damascene wiring and the insulation layer.

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Abstract: A semiconductor device comprises a semiconductor substrate; a diffusion layer formed on the semiconductor substrate; at least two wiring layers formed opposite to each other over the semiconductor substrate; signal lines for transmitting a signal maintaining a predetermined voltage, each of the signal lines being formed in each of the two wiring layers; shield lines fixed to a constant voltage to shield the signal lines, each of the shield lines being formed adjacent to each of the signal lines in the two wiring layers; and a gate electrode formed over the semiconductor substrate via an insulation film. In the semiconductor device, at least one of the signal lines formed in a lower wiring layer of the at least two wiring layers is electrically connected to the gate electrode opposed in a stacking direction.

Abstract: In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.

Abstract: A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure.

Abstract: An IC includes a substrate having a semiconductor top surface, a plurality of metal interconnect levels having inter-level dielectric (ILD) layers therebetween on the top surface, and a bottom surface. A plurality of through substrate vias (TSVs) extend from a TSV terminating metal interconnect level downward to the bottom surface. The plurality of TSVs include an electrically conductive filler material surrounded by a dielectric liner that define a projected volume. The projected volume includes a projected area over the electrically conductive filler material and a projected height extending upwards from the TSV terminating metal interconnect level to a metal interconnect level above, and a projected sidewall surface along sidewalls of the projected volume. A crack suppression structure (CSS) protects TSVs and includes a lateral CSS portion that is positioned lateral to the projected volume and encloses at least 80% of the projected sidewall surface.

Abstract: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.

Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

Abstract: A semiconductor device has a singulated die having a substrate and a die edge. An interconnect dielectric layer is located on the substrate, and integrated circuit has interconnections located within the interconnect dielectric layer. A trench is located in the interconnect dielectric layer and between a seal ring and a remnant of the interconnect dielectric layer. The seal ring is located within the interconnect dielectric layer and between the trench and the integrated circuit, with the remnant of the interconnect dielectric layer being located between the trench and the edge of the die.

Abstract: A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; a well, having a well contact connection region, formed in the semiconductor substrate; a transistor formed on the well; an isolation region formed between the transistor formed on the well, and the well contact connection region; and a silicide layer formed between a bottom surface of the isolation region, and the semiconductor substrate.

Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.

Abstract: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on a substrate and a raised conductor formed to protrude from the bottom conductor, a dielectric film formed on the raised conductor, and a second conductor formed on the dielectric film to constitute a capacitor element in combination with the raised conductor and the dielectric film.

Abstract: A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode.