Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: A fabrication method for a semiconductor memory device having an isolation structure which includes the steps of forming a pad oxide film on a semiconductor substrate, forming a first nitride film on the pad oxide film, patterning the first nitride film and the pad oxide film, forming an oxynitride film on a portion of the substrate externally exposed by the patterning step, forming side walls of a second nitride film on sides of the first nitride film, removing a portion of the oxynitride film using the side walls as a mask, forming a field oxide film on an exposed portion of the substrate, and removing the remaining pad oxide film, first nitride film, second nitride film, and oxynitride film. The first nitrate film and the pad oxide film may be patterned such that the pad oxide film is undercut to expose more of the substrate and to allow formation of the oxynitride film under the first nitride film. As such, the first nitride film can be used as a mask, rendering unnecessary the formation of side walls.

Abstract: A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask.

Abstract: An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region.

Abstract: A method for fabricating a CMOS image sensor resolves the abnormally elevated output at the first pixel without degrading the integration of the device. The method of the invention lengthens the field oxide layer within the scribe-line region to ensure the substrate and the conducting layer thereon are properly insulated. That prevents the leakage of the carriers generated by the Electro-optical effect to resolve the problem of an abnormally elevated output at the first pixel. In addition, a mask protects the dielectric layer on the scribe-line region from being etched, so the steep difference on the step height is improved to resolve the peeling of the photoresist. The field oxide layer under the dielectric layer covered by the dielectric layer then provides a better insulation.

Abstract: A semiconductor device provided with a wide and shallow first groove and a second groove in the first groove area, having a narrower width than that of the first groove around a predetermined area in a one-conductive area provided in the upper region of a semiconductor substrate as a mesa groove, wherein at least the second groove is covered with an electrical insulator. The upper surface of the electrical insulator is located approximately as high as or lower than the upper surface of the electrical insulating film. Thus, especially in a mesa semiconductor device with a high-voltage resistance, an insulating protective layer having a sufficient thickness can be formed stably over the entire region of a mesa groove. As a result, the variation in high-voltage resistance characteristics can be decreased and the processing yield affected by breakage or cracking in the mesa groove region during subsequent processes caused by the formation of the mesa groove can be improved greatly.

Abstract: A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.

Abstract: In a DRAM adopting a self-aligned contact structure, an opening portion of predetermined size is formed in advance in an insulation film which surrounds an on-field gate electrode formed on an element isolating insulation film. The on-field gate electrode contacts a gate contact through the opening portion. A contact hole for the gate contact can thus be formed in self-alignment as can be the contact holes for a bit-line contact and an active contact. Consequently, the contact hole for the gate contact reaching the on-field gate can be formed simultaneously with the contact holes for the bit-line contact and active contact, thereby greatly reducing the number of manufacturing steps.

Abstract: A method of fabricating semiconductor memory devices which has sufficient cell isolation to achieve miniaturization at the 0.3 to 0.4 .mu.m level. In the semiconductor memory devices of the present application miniaturization is achieved by removing overlap allowances between each gate and each LOCOS and those between each diffusion layer and each LOCOS used to separate the above-described semiconductor memory elements.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: An integrated circuit and method for making it is described. The integrated circuit includes an insulating layer, formed within a trench that separates conductive elements of a conductive layer, that has a low dielectric constant. The insulating layer is convertible at least in part into a layer that is resistant to a plasma that may be used for a photoresist ashing step or to a solvent that may be used for a via clean step. Preferably the insulating layer comprises a silicon containing block copolymer that is convertible at least in part into a silicon dioxide layer. The silicon dioxide layer protects the remainder of the insulating layer from subsequent processing, such as photoresist ashing and via clean steps.

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: Bridged, doped zones are formed in a semiconductor. A silicon nitride layer is deposited and structured on a semi-conductor region with a predetermined dopant concentration. The structure is subjected to thermal oxidation, with the result that at least one oxide region and at least two oxide-free regions, which are separated from one another by the oxide region, are produced on the surface of the semiconductor region. A dopant is introduced into the oxide-free regions and driven into the semiconductor region. A coherent zone is thus produced in the semiconductor region with a dopant concentration at least ten times the dopant concentration of the semiconductor region. This produces a coherent zone having a high dopant concentration which is bridged by the oxide region which separates the oxide-free regions on the surface of the semiconductor region.

Abstract: A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion implantation process of a dopant opposite to a dopant contained in the doped semiconductor substrate such that there is formed a depletion of carriers in the vicinity of the foregoing interface.

Abstract: A semiconductor memory device laid out to have a deep well of a second conductivity type formed in a semiconductor substrate of a first conductivity type, a cell array well of the first conductivity type formed on said deep well, and an isolation well of the second conductivity type formed around said cell array well to reach said deep well so as to incorporate said cell array well, thereby isolating said cell array well from said semiconductor substrate through said isolation well, wherein a circuit element for driving said cell array is formed in said isolation well.

Abstract: An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

Abstract: A field oxide layer for a semiconductor device includes an upper portion of first thickness extending above the major surface of a semiconductor substrate, and a lower portion of second thickness extending below the major surface of the semiconductor substrate. The ratio of first thickness to second thickness is not less than 1 to 2.

Abstract: Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect.

Abstract: Each nonvolatile transistor comprises a floating gate electrode, an ONO film and a control gate electrode. An upper surface of a silicon oxide film is positioned at a height between upper and lower surfaces of the floating gate electrode. The control gate electrode continuously extends on the floating gate electrode and the silicon oxide film in a prescribed arrangement direction.

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

Abstract: A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask.

Abstract: A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

Abstract: A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a compacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

Abstract: In a semiconductor device having a PN junction element separating region, in order to reduce a width of the PN junction element separating region without sacrifice of a punch-through breakdown voltage of the PN junction element separating region, the PN junction element separating region is composed of an upper impurity layer of a first conductivity type having low impurity density and a lower impurity layer of the first conductivity type having a high impurity density and a width of the upper impurity layer is smaller than a width of the lower impurity layer.

Abstract: A Schottky diode assembly includes a Schottky contact formed on a semiconductor substrate and having a semiconductor region of a first conduction type, a metal layer disposed adjacently on the semiconductor region, a protective structure constructed on a peripheral region of the Schottky contact and a doped region in the semiconductor substrate having a second conduction type of opposite polarity from the first conduction type. The doped region extends from a main surface of the semiconductor substrate to a predetermined depth into the semiconductor substrate. The doped region of the protective structure has at least two different first and second doped portions located one below the other relative to the main surface of the semiconductor substrate. The first doped portion is at a greater depth and has a comparatively lesser doping, and the second doped portion has a comparatively higher doping and a slight depth adjacent the main surface of the semiconductor substrate.

Abstract: An integrated circuit includes a substrate and at least two circuits, such as a digital circuit and an analog circuit. The substrate is preferably derived from a bulk substrate wafer. The integrated circuit preferably comprises at least two islands in the substrate for noise isolation between the circuits. The two islands are buried-layers that are implanted, by preference, using conventional MeV techniques. A method of manufacturing an integrated circuit includes a substrate and at least two circuits. The method comprises the step of implanting at least two islands in the substrate for noise isolation between the circuits. The implanting is accomplished by conventional masking and high-energy implantation, such as MeV.

Abstract: A semiconductor device having a bonded wafer structure capable of reducing crystal defect in a power element forming region thereof is disclosed. A recess is formed in a control circuit element forming region of a first n- silicon substrate, then filled with a silicon oxide film and subjected to grinding and polishing to provide a mirror-surface. An n- epitaxial layer is formed on the surface of a second n+ silicon substrate, then the surface of the epitaxial layer is coupled to the surfaces of the silicon oxide film and second circuit region of the first substrate and heat-treated to be bonded thereto.

Abstract: In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.

Abstract: In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an "L" level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.

Abstract: A semiconductor substrate which is optimum for a substrate for integrating a vertical power element and a control circuit element monolithically. A cavity 3 is formed between a dielectric layer 2 and a single crystal silicon substrate 4 in a control circuit element forming region 8, and junction planes 1a and 4a of single crystal silicon substrates 1 and 4 are joined together. Since bonding of regions where a vertical power element is formed is made with flat single crystal silicon planes, no void (non-bonded portion) is generated on the junction plane of the region where the vertical power element is formed. As a result, it is possible to realize a semiconductor device provided with perfect junction having electrical conductivity in a direction perpendicular to the junction interface.

Abstract: A highly integrated flash memory device having a stable cell is provided.

Abstract: A manufacturing method for a semiconductor device is disclosed for effecting improvement of voltage resistance between an N-well and N-type diffusion layer without adversely affecting circuit and transistor characteristics. At the time of forming an N-well, a side wall composed of nitride layer is formed on the oxide layer that is used as a mask in phosphorus implantation, and the N-well is formed using as a mask the oxide layer on which this side wall is provided. The side wall is then removed, boron is implanted, and a channel stopper is formed only between the N-well and N-type diffusion layer. A channel stopper between N-type diffusion layers is formed subsequently as a separate step. In this way, the concentration of the channel stopper between the N-well and N-type diffusion can be set to a concentration different from that of the channel stopper between N-type diffusion layers.

Abstract: A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting when a metal silicide is used in the source/drain regions. A silicon wafer, is formed with a gate electrode material on a gate insulating layer before forming the trenches for isolation. Now, with an etch protective layer on the gate electrode, trenches are etched and filled with an insulating material in the gate electrode material, the gate insulating layer and the silicon wafer to isolate the active regions. After the gate electrode material is etched to define the gate electrodes, the tops of gate electrodes are in essentially the same plane as the tops of the trenches. Preferably in the fabrication process, sidewalls are formed on the walls of the trenches and the gate electrodes.

Abstract: A semiconductor device includes a field insulating film, a channel stopper, and a diffusion layer. The field insulating film is formed on one major surface of a semiconductor substrate of a first conductivity type to surround an element region. The channel stopper of the first conductivity type is formed immediately below the field insulating film. The diffusion layer of an opposite conductivity type is formed to be adjacent to the channel stopper. The impurity concentration peak position of the diffusion layer substantially coincides with that of the channel stopper.

Abstract: A buried collector layer is formed on a semiconductor substrate. An epitaxial layer is formed on the burled collector layer. A plurality of element separating trenches of roughly the same depth and filled with an insulating material are formed in the epitaxial layer. When these trenches are formed deep enough to penetrate the buried collector layer to the semiconductor substrate, an impurity region of conductivity the same as that of the buried collector layer is formed at a predetermined position of the semiconductor substrate and adjoining to at least one bottom portion of a plurality of the trenches. Further, when a separation layer is formed on the semiconductor substrate and adjoining to the buried collector layer to separate the semiconductor device from another adjacent semiconductor device, at least one of a plurality of trenches is formed on a boundary surface between the buried collector layer and the separation layer.

Abstract: A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

Abstract: The invention provides an n-channel MOS field effect transistor with an improved anti-radioactivity. Such transistor includes a p-type silicon substrate. An isolation oxide film is selectively formed on a surface of the p-type silicon substrate. Source and drain diffusion layers of n+-type are formed on first opposite sides of a channel region in the p-type silicon substrate. A gate made of polycrystalline silicon is formed over the channel region through a gate oxide film. Leak guard diffusion layers of p-type are formed on second opposite sides of the channel region in the p-type silicon substrate. The p-type leak guard diffusion layer has a junction surface to the isolation oxide film. The junction surface of the p-type leak guard diffusion layer and the isolation oxide film exists up to a level which is deeper than a depth of the n+-type source and drain diffusion layers.

Abstract: A thin film protected capacitor structure having a thin film capacitor and a protection device is provided on an integrated circuit wafer. The wafer has a low resistivity substrate of a first type disposed under an epitaxial layer of a second type different from the first type. The structure includes a first heavily doped region, which is of the first type, in and through the epitaxial layer, and an oxide layer having a first oxide region disposed above the first heavily doped region. The first heavily doped region and the low resistivity substrate form the first plate of the thin film capacitor. There is also included a metal layer disposed above the first oxide region. A portion of this metal layer forms the second plate of the thin film capacitor. Between the second plate and the first plate, the aforementioned first oxide region represents the insulating dielectric. There is also included a second heavily doped region in the epitaxial layer.

Abstract: A semiconductor integrated circuit device comprises an input terminal for inputting a voltage, an output terminal for outputting a voltage, a MOS driver disposed between the input terminal and the output terminal for adjusting the voltage of the input terminal and transmitting it to the output terminal, and a MOS control circuit for controlling the MOS driver and feeding back voltage information of the output terminal. Each of the MOS driver and the MOS control circuit has a MOS transistor formed on a semiconductor substrate, and each MOS transistor has a source region, a drain region, a channel region disposed between the source region and the drain region, a gate insulating film disposed over the channel region, and a gate electrode disposed over the gate insulating film. The gate insulating films of the MOS transistors have different film thicknesses.

Abstract: A semiconductor device manufactured by isolating an element by forming an insulating film on the surface of a semiconductor substrate at an element isolation region, selectively forming a resist film at a second region on the surface of the semiconductor substrate by photolithography, high speed operation having priority over high integration in the second region, and selectively implanting impurity ions as a channel stopper in a first region by using the resist film as a mask, high integration having priority over high speed operation in the first region.

Abstract: A device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor and an N-channel MOSFET transistor in an emitter switching configuration, both being vertical conduction types. The bipolar transistor has its base and emitter regions buried; the MOSFET transistor is formed with an N region bounded by the base and the emitter regions and isolated by a deep base contact and isolation region. To improve the device performance, especially at large currents, an N+ region is provided which extends from the front of the chip inwards of the isolated region and around the MOSFET transistor. In one embodiment of the invention, a MOSFET drive transistor is integrated which has its drain terminal in common with the collector of the bipolar transistor, its source terminal connected to the base of the bipolar transistor, and its gate electrode connected to the gate electrode of the MOSFET transistor in the emitter switching configuration.

Abstract: A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substrate capacitance and PMOS FETs which require latch-up immunity; and (iii) NPN bipolar transistors which require low collector-to-substrate capacitance.

Abstract: An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Abstract: A high voltage semiconductor component having a low stray current comprises a central region (N.sup.-) surrounded by P-type layers (P.sub.1, P.sub.2) forming with the central region first and second junctions (J.sub.1, J.sub.2). The first and second junctions have an apparent perimeter on a same main surface of the component. A groove is formed between said apparent perimeters and is filled with a passivation glass (18). The surface of the glass is covered, above the perimeter of each junction, with a metallization (21, 22) contacting the layer of the second conductivity type corresponding to the junction.

Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Abstract: A complementary field effect element develops an intensified latch-up preventive property even if the distance between the emitters of parasitic transistors is short, and a method of producing the same are disclosed. The complementary field effect element includes a high concentration impurity layer (16) formed by ion implantation in the boundary region between a P-well (2) and an N-well (3) which are formed adjacent each other on the main surface of a semiconductor substrate (1). Therefore, carriers passing through the boundary region between the P-well (2) and the N-well (3) are decreased, so that even if the distance between the emitters (4, 5) of parasitic transistors is short, there is obtained an intensified latch-up preventive property.

Abstract: An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.

Abstract: A semiconductor device comprises a complementary MOS transistor integrated circuit formed in a semiconductor single crystal silicon disposed on an electrically insulating layer. A thickness of the single crystal silicon in a region in which an N-type MOS transistor is formed is made thicker than the thickness in a region in which a P-type MOS transistor is formed. By this structure, the bottoms of the source region and the drain region of the N-type transistor are separated from the electrically insulating layer by a predetermined distance. The separation of the source region and the drain region from the electrically insulating layer is effective to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.