Abstract: The present invention is primarily directed to obtaining a P channel high voltage transistor with an improved breakdown voltage. A first N type well region is provided in a main surface of a P type semiconductor substrate. A first field oxide film is provided in the main surface of the first N type well region. A P type source region and a P type drain region are provided on the opposite sides of the first field oxide film in the main surface of the first N type well region. A P type impurity injection region is provided immediately under the field oxide film so as to be connected to the P type drain region. A gate electrode is provided between the P type source region and the P type drain region on the first N type well region. An N.sup.+ ion injection region is provided between the P type source region and a channel in the N type well region. The first N type well region located under the P type drain region has its N type impurity concentration uniform at any depth.

Abstract: A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.

Abstract: A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

Abstract: A back biasing technique is provided for increasing the field inversion voltage between adjacent MOS transistors and for reducing parasitic capacitances in an integrated circuit. The use of a charge pump is avoided by connecting the body portions of the MOS transistors to ground and the sources of the MOS transistors to the anode of a diode, the cathode of which are connected to a reference voltage such as to ground. In this manner, the sources are back biased relative to the material in which they are formed by a diode forward voltage drop. This technique is particularly applicable to CMOS circuits operating from a 3.3 volt supply, with p-well doping densities in excess of 1.times.10.sup.17 atoms/cm.sup.3.

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

Abstract: Methods for the construction of field oxide film is disclosed. The methods facilitates the control of the length and thickness of L-shaped spacer, overcoming some difficulties in processing a semiconductor device. Thus, the stresses and defects of semiconductor substrate can be greatly diminished. In addition, the methods bring about an effect of easily achieving the separation process of semiconductor device, an essential process. Superior in suppressing Bird's beak, the methods are capable of securing more large active region in a semiconductor device.

Abstract: An input protective circuit provided between a semiconductor integrated circuit and an input bonding pad formed on a semiconductor substrate includes an N or P type electric field intensity relaxing region for setting a clamp level of the input protective circuit. The electric field intensity relaxing region is formed between an N.sup.+ -type semiconductor region connected to an input wiring layer and a P.sup.+ -type semiconductor region connected to a reference potential wiring layer.

Abstract: A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region.

Abstract: A semiconductor device such as a DRAM is provided, in which a channel stop region of a first conductive type is formed in a semiconductor substrate just below a field insulator. The channel stop region comprises a first part and a second part higher in impurity concentration than the first part. An impurity-doped region such as a source/drain region of an MOS transistor, which is of a second conductive type opposite in polarity to the first conductive type, is in contact with the first part but is not in contact with the second part in the substrate. A leakage current through a p-n junction between the channel stop region and the impurity-doped region can be reduced and as a result, reliability of operation can be improved.

Abstract: An isolation structure is disclosed which isolates an active region (24) from other proximate active regions. The isolation structure utilizes the combination of a LOCOS structure (26) comprising bird's beak structure (26a) and (26b). A trench (34) is formed through the LOCOS structure (26). A channel stop implant region (40) is formed along the sidewalls of the trench (34). A trench plug (46) is used to fill the trench. The isolation structure thereby uses the isolation capabilities of trench isolation structures, but prevents the leakage currents common along trench sidewalls by isolating the trench sidewalls from the active region using the LOCOS structures.

Abstract: A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

Abstract: Steps or grooves are formed in a surface of a semiconductor substrate of a semiconductor device having a plurality of semiconductor elements, and an isolation layer is formed on regions that include the steps or side walls of the grooves.

Abstract: A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region.

Abstract: The semiconductor device somprises a silicon substrate, a boron-doped high resistant silicon carbide layer formed on said silicon substrate and a silicon carbide layer formed on said high resistant silicon carbide layer.