Abstract: According to a disclosed embodiment, an etch stop layer is fabricated on top of a base. An amorphous layer is then formed on top of the etch stop layer. An opening is then etched in the amorphous layer and the etch stop layer. The opening is etched with an opening width substantially equal to a critical dimension. The opening with opening width substantially equal to a critical dimension is then filled with a polycrystalline emitter. The resulting polycrystalline emitter has an emitter width substantially equal to the critical dimension. Moreover, a polycrystalline emitter structure can be fabricated, in which the critical dimension, i.e. the emitter width, is precisely controlled. The result is a polycrystalline emitter structure which is substantially as small as the resolution that the photolithography process would allow.

Abstract: An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.

Abstract: A metal-to-metal capacitor in a semiconductor integrated circuit is converted to a conductive structure by connecting the first metal plate of the capacitor to ground and the second metal plate of the capacitor to a programming voltage, thus causing the insulator material to breakdown and conduct current from the first plate to the second plate.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate including an active region and an isolating region provided so as to enclose the active region; a capacitance insulating film that is provided on the active region and has a boundary portion in contact with the isolating region; an upper electrode provided on the capacitance insulating film so as to be spaced away from the isolating region; an electrode pad provided on the isolating region; a lead conductive film provided over a part of the capacitance insulating film and a part of the isolating region for connecting the upper electrode and the electrode pad; and an interlayer insulating film provided over the substrate.

Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings formed on the second insulating film and connected to the resistor film, in which a thickness T3 of the second insulating film is thinner than a thickness T2 of the resistor film.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: A system and method in accordance with the invention minimizes the redesign burden in tuning and/or customizing PLLs on ICs. Variable resistors are placed in the PLL in places that facilitate tuning. The variable resistors are formed with a set of at least three contacts, where each contact is in electrical communication with a resistive area. A metal layer is used to form leads to the resistive area, where each lead is formed to be in electrical communication with only a selected subset of contacts from the set. In one embodiment, only the uppermost metal layer used in forming the IC is used to form the leads. Because the uppermost metal layer is utilized, the resistor value can be adjusted simply by selecting the subsets of contacts that are to be in electrical communication with the uppermost metal layer. In this manner, only one metal layer needs to be adjusted in tuning and/or customizing a PLL, rather than having to redesign and re-layout all metal layers and vias in the IC.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried therein in the form of buried interconnections. The first and second plugs (9, 19) provide connection not only between an end portion of the resistor layer (5) and first and second interconnection layers (8, 18) but also between the end portion of the resistor layer (5) and the major surface (1S) of the semiconductor substrate (1).

Abstract: A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.

Abstract: Laser Programming of Integrated Circuits. The invention relates to the laser adjustment or laser programming of laser fuses of an integrated circuit on a chip, with laser light, the integrated circuit having a plurality of laser fuses and being connected to a plurality of contact pads on the chip, and the chip being covered with a polymer layer which has at least windows on the plurality of contact pads, and comprising at least one wiring interconnect on the polymer layer which is electrically connected to at least one of the plurality of contact pads and ends at a predetermined location on a surface of the chip.

Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the-amplified current to an associated read data line.

Abstract: A semiconductor device and a manufacturing method for the same can be obtained wherein a semiconductor substrate of a high resistance that can enhance the Q value of a passive circuit element is used and leak current due to the impurity fluctuation that easily occurs in this high resistance semiconductor substrate, and whereby noise resistance of an active element in the high resistance semiconductor substrate is increased. A semiconductor device including a bipolar transistor formed in the main surface of a semiconductor substrate is provided wherein the bipolar transistor includes a semiconductor layer of a first conductive type at a bottom portion thereof and this semiconductor device is provided with a buried layer of a second conductive type, which is located in the semiconductor substrate so as to face the semiconductor layer of the first conductive type.

Abstract: A semiconductor device is provided, which is provided with a high resistance to surge currents. The semiconductor device comprises three N+ diffusion layers 4a, 4b, and 4c in a region surrounded by an element-separating insulating film 3a. The N+ diffusion layer 4a forms a source diffusion layer of an N-channel MOS transistor 11a, the N+ diffusion layer 4c forms a source diffusion layer of another N-channel MOS transistor 11b, and the N+ diffusion layer 4b forms drain diffusion layers for two N-channel MOS transistors 11a and 11b. That is, respective drain diffusion layers of two N-channel MOS transistors are shared. Furthermore, a ring-shaped mask insulating film 18 is formed on the N+ diffusion layer 4b. A silicide layer 6b is formed on the N+ diffusion layer 4b except the area covered by the ring-shaped mask insulating film 18.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: An integrated circuit including a resistor that at least partially overlies a first tub of semiconductor material of a first polarity, where the first tub is formed in a second tub of semiconductor material having the opposite polarity, and the second tub is formed in a semiconductor substrate having the first polarity. The second tub forms the base of a vertical bipolar transistor, the first tub forms the emitter of the transistor, and the substrate forms the collector of such transistor. Where the vertical transistor is a PNP transistor, the first tub is the emitter and consists of P-type semiconductor material, the second tub is the base, and the substrate is the collector. Preferably, the resistor is a strip of polysilicon or a set of multiple, series-connected polysilicon segments. Typically, the integrated circuit is an amplifier and the resistor is a gain-setting resistor.

Abstract: In a semiconductor device comprising a resistance element electrically connected to a bipolar transistor, the bipolar transistor is formed on a silicon substrate and a predetermined resistance element is formed on an insulation film formed on the bipolar transistor based on results of measurements monitored for this transistor, in such a manner that the semiconductor device has prescribed characteristics.

Abstract: A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall. The dopants will diffuse through the layer and form a low resistance connection to the buried layer. The layer may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer is not in itself conducting, the size of the component may be significantly reduced.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: In a semiconductor device comprising a resistance element electrically connected to a bipolar transistor, the bipolar transistor is formed on a silicon substrate and a predetermined resistance element is formed on an insulation film formed on the bipolar transistor based on results of measurements monitored for this transistor, in such a manner that the semiconductor device has prescribed characteristics.

Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.

Abstract: A polycrystalline silicon coated nitride-lined shallow trench technique for isolating active regions on an integrated circuit involves reducing the oxide encroachment and the "bird's beak" structure. The technique involves forming an isolation trench, or recess, in the substrate. This recess is then lined with a layer of silicon dioxide layer, and then a layer of silicon nitride. Subsequently, a polycrystalline silicon material is deposited in the recess and is then oxidized to form a field oxide and planarized. Since the recess is nitride-lined, which prevents oxidizing species from reaching the oxide layer beneath the nitride layer, and the polycrystalline silicon is oxidized, the result is zero oxide encroachment resulting in the elimination of the "bird's beak" structure.

Abstract: The invention relates to a structure for and the method of manufacturing a driver circuit for an inductive load monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well having a second type of doping agent. An insulated well doped with the same type of doping agent as the substrate, which houses at least one power transistor of the driver circuit, is provided within the epitaxial well. The epitaxial well also houses a first and a second active area which house the cathode terminal and anode terminal of a protection diode, respectively.

Abstract: An asymmetric snubber resistor in accordance with the present invention includes a cathode, an N+ region, an N- region, a plurality of P+ regions, and an anode. The N+ region is disposed over the cathode, the N- region is disposed over the N+ region, the plurality of P+ regions are disposed over the N- region, and the anode is disposed over the plurality of P+ regions and exposed portions of the N- region. The asymmetric snubber may also include N regions between the P+ regions. The asymmetric snubber resistor replaces the snubber diode and the snubber resistor in a typical snubber circuit.

Abstract: The continuing miniaturization of integrated circuits leads to a demand for ever higher resistance values. In conventional diffused resistors or poly resistors, an increase in the resistance value also means an increase in the surface area. Such resistors, moreover, are highly dependent on the doping concentration and sensitive to temperature changes. A resistor according to the invention comprises a resistor region 18 with a length and doping concentration which are chosen such that an electric field is applied at which velocity saturation of charge carriers takes place in the envisaged range of operation. The connection regions are connected to the resistor region via rectifying junctions 21, 22. In a specific embodiment, these junctions are formed by pn junctions, so that the resistor has, for example, an npn shape.

Abstract: A bipolar transistor includes a chip having a base electrode and an emitter electrode on a surface thereof and a film resistor provided on a surface of the chip and electrically connecting the base electrode and the emitter electrode to each other, the film resistor having a negative resistance characteristic with temperature change.

Abstract: A bipolar transistor circuit element includes a semiconductor substrate; successively disposed on the substrate, a base layer, an emitter layer, and a collector layer; a bipolar transistor formed from parts of the collector, base, and emitter layers and including a base electrode electrically connected to the base layer and a base electrode pad for making an external connection to the base layer; a base ballasting resistor formed from a part of the base layer isolated from the bipolar transistor and electrically connecting the base electrode to the base electrode pad; and a base parallel capacitor connected in parallel with the base ballasting resistor wherein the base parallel capacitor includes part of the base input pad, a dielectric film disposed on part of the base electrode pad, and a second electrode disposed on the dielectric layer opposite the base electrode pad and electrically connected to the emitter electrode of the bipolar transistor.

Abstract: An inductive driver circuit (10) has a driver transistor (11) that is used for driving loads. An input protection device (13) and a voltage suppression device (12) assist in protecting the transistor (11). The circuit (10), including the driver transistor (11) and the input protection device (13), are formed in a common collector region.

Abstract: Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. The resistive emitter diffusion sections result in a lower emitter ballast resistance due to the higher emitter sheet resistance of PNP devices. This allows all the periphery of the emitter to be active, not just two sides. The device has improved emitter ballast resistance while at the same time remaining efficient with low saturation resistance.

Abstract: A diffused resistor capable of suppressing variation of characteristics caused by leakage of current occurring under high-temperature conditions. An N-type layer is epitaxially grown on a P-type substrate, and an N-type resistor island isolated by a P-type isolation region is formed. A P-type diffused resistor is formed in the island. An N-type region of high impurity concentration is disposed in close proximity to the high-potential end of the P-type diffused resistor. An electrode is brought into contact with not only the high-potential end but also the N-type high-impurity concentration region through the same contact hole. Thus, a parasitic transistor, which is formed from the P-type diffused resistor, the N-type resistor island and the P-type substrate (P-type isolation region), can be prevented from turning on with a minimal increase of the element area.

Abstract: A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).

Abstract: A silicon microwave monolothic integrated circuit device and method of fabricating having a high resistivity silicon substrate with a masking layer of low temperature silicon oxide, silicon nitride and polysilicon sublayers on a first area, and an epitaxial layer over the surface of the silicon substrate in a second area. The active devices are formed over the second area and the passive devices are formed over the first area.

Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.

Abstract: In a bipolar power component, for example an IGBT, having an emitter structure and a drift zone of the opposite conductivity type, the emitter structure is provided with a first contact and the drift zone is provided with a second contact. The first contact and the second contact are connected to a drivable resistor circuit such that, dependent on a control signal at the resistor circuit, the current through the power component optionally flows via the first contact and/or via the second contact to a third contact of the resistor circuit.

Abstract: A semiconductor device includes a first layer made of a first type semiconductor, a second layer provided on the first layer and made of a second type semiconductor, the second layer including low resistance diffusion parts and high resistance diffusion parts, where the first and second type semiconductors are one and the other of n-type and p-type semiconductors, a third layer provided on the low resistance diffusion parts of the second layer and made of the first semiconductor type, thereby forming a pair of transistors which form a flip-flop and use the high resistance diffusion parts as balanced load resistors, and at least first and second isolations isolating the flip-flop.

Abstract: A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium.

Abstract: An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.

Abstract: A Darlington transistor having improved comprehensive electric characteristic and a bipolar transistor having improved high voltage characteristic are obtained. A collector resistivity .rho.N.sup.- (F) of a collector high resistivity layer (11) in a front stage side transistor chip (TF) is set to 80 5/8cm and its collector film thickness tN.sup.- (F) is set to 120 .mu.m, and a collector resistivity .rho.N.sup.- (R) of a collector high resistivity layer (13) in a rear stage side transistor chip (TR) is set to 45 .OMEGA.cm and its collector film thickness tN.sup.- (R) is set to 160 .mu.m. Since .rho.N.sup.- (F)>.rho.N.sup.- (R) and tN.sup.- (F)<tN.sup.- (R) are satisfied, a Darlington transistor having a good comprehensive electric characteristic can be obtained, and also, since .rho.N.sup.- (R)/tN.sup.- (R)<0.6 is satisfied, a bipolar transistor having a good high voltage characteristic can be obtained (FIG. 8).

Abstract: An integrated circuit includes a photo diode having a first electrically isolated portion of an epitaxial layer of a first conductivity type, a first semiconductor layer of a second conductivity type disposed therein, a second semiconductor layer of the first conductivity type disposed in the first semiconductor layer, and a third semiconductor layer of the second conductivity type disposed in the second semiconductor layer.

Abstract: A semiconductor device has a semiconductor substrate including a base region and an emitter region in the base region. The emitter region in the base region has a comb-teeth-shaped outer edge. The emitter region has a window through which the base region is exposed. The window has an extended ares to reach portions of the emitter region near the comb-teeth-shaped outer edge of the emitter region. Consequently, the area of junction between the window and the emitter region os increased to suppress concentration of electrical current in the window and to improve electrical characteristics such as secondary yield breakdown strength.

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Abstract: A semiconductor switching device including a first IGBT and a second IGBT connected in parallel The first IGBT has a low saturation voltage and a long fall time, whereas the second IGBT has a high saturation voltage and a short fall time. An input resistor is connected to the gate of the second IGBT, and a common drive signal is applied to a gate of the first IGBT, and to a gate of the second IGBT through the input resistor. The cutoff of the second IGBT is delayed when the first and second IGBTs are driven by the common drive signal so that the semiconductor switching device is turned off in the short fall time of the second IGBT. The switching speed is increased and the switching loss is decreased. Only a single drive circuit is enough for driving the device, enabling the miniaturization and low cost of the driving circuit.

Abstract: In a bipolar static induction transistor (BSIT) with increased input impedance, gate-voltage control is used for switching operations. The BSIT includes a collector region, a base region, an emitter region, and a source region in the base region. For enhanced turn-off, an auxiliary base region is included; alternatively, a drain region is provided in the base region.

Abstract: A monolithic integrated circuit provides RF and DC coupling for a unit cell of a high power quasi-optic grid amplifier. The monolithic chip includes two heterojunction bipolar transistors (HBTs) connected in a differential pair configuration with a common emitter and integrated collector-base and emitter bias resistors. Each of the plurality of unit cells comprising the quasi-optic grid amplifier includes an emitter-coupled HBT differential pair chip at the center, an input antenna that extends horizontally in both directions from the two base leads, an output antenna that extends vertically in both directions from the two collector leads, and high inductance bias lines for the emitter and collectors. The grid amplifier, which functions as a high frequency, high gain, wide bandwidth, free-space beam amplifier, comprises a plurality of unit cells arranged in a repeating pattern of input and output dipole antennas.

Abstract: A multi-emitter type semiconductor device having multiple transistors coupled in parallel which utilize a common substrate. Between a selected emitter electrode and a base contact, a stabilizing resistive region is formed in the common substrate. In order to reduce the parasitic effects due to this region an additional emitter ballast resistor may be formed on the surface of an insulating layer over the substrate. This supplemental resistor formed on the insulating layer is made from polycrystalline silicon. Alternatively, the supplemental resistor can be combined with the resistance of the stabilizing region in a single resistor located on the surface of the insulating layer.

Abstract: A semiconductor chip has at least one electrical resistor means, at least one semiconductor component arranged in the semiconductor chip, and at least one metallization for the semiconductor component on the semiconductor chip. At least one resistor means is at least partially arranged under the metallization. This permits a space requirement for the resistor means on the semiconductor chip to be reduced.