Abstract: A crystalline oxide semiconductor film which can be used as a semiconductor film of a transistor or the like is provided. In particular, a crystalline oxide semiconductor film with less defects such as grain boundaries is provided. One embodiment of the present invention is a crystalline oxide semiconductor film which is provided over a substrate and has a region including five or less areas where a transmission electron diffraction pattern showing discontinuous points is observed when an observation area is changed one-dimensionally within a range of 700 nm, using a transmission electron diffraction apparatus with an electron beam having a probe diameter of 1 nm.

Abstract: A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract: To provide a novel resistor. To provide a display device having a novel structure that can improve its reliability. To provide a display device having a novel structure that can reduce electrostatic discharge damages. The resistor includes a semiconductor layer and an insulating layer formed over the semiconductor layer, and the semiconductor layer is an oxide represented by an In-M-Zn oxide that contains at least indium (In), zinc (Zn), and M (M is a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) and the insulating layer contains at least hydrogen.

Abstract: A miniaturized transistor having high electrical characteristics can be provided with high yield. High performance, high reliability, and high productivity of a semiconductor device including the transistor can be achieved. The semiconductor device includes a gate electrode over an insulating surface; a base insulating film which is over the insulating surface and from which the gate electrode protrudes; a gate insulating film over the base insulating film and the gate electrode; an oxide semiconductor film over the gate insulating film; and a source electrode and a drain electrode in contact with an oxide semiconductor film. The thickness of the oxide semiconductor film is smaller than the difference between the thickness of the gate electrode and the thickness of the base insulating film.

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

Abstract: A method for the fabrication of thin-film transistors together with micromechanical components, other active electrical components or both on an amorphous or polycrystalline substrate includes disposing the thin-film transistors and the other components on different areas of the substrate.

Abstract: A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate.

Abstract: A method for producing a thin film transistor includes forming a transistor prototype on a substrate. The transistor prototype includes two transparent electrodes adapted to form a source and a drain of a thin film transistor. Next, the two transparent electrodes of the transistor prototype are exposed in an environment full of a plasma. The plasma conducts a surface treatment on the two transparent electrodes of the transistor prototype to form the thin film transistor. The method can solve the problem of excessive contact resistance of the transparent conductive films of conventional thin film transistors.

Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

Abstract: A thin film transistor substrate includes a base substrate and a thin film transistor. The base substrate includes a gate line and a data line. The thin film transistor is connected to the gate line and the data line. The thin film transistor includes a gate electrode, a semiconductor pattern and source, drain electrodes. The gate electrode is disposed on the base substrate. The semiconductor pattern overlaps with the gate electrode. The source, drain electrodes is spaced apart from each other. The source electrode includes a first source layer, a second source layer disposed on the first source layer and a first diffusion barrier disposed between the first source layer and second source layer. The drain electrode includes a first drain layer, a second drain layer disposed on the first drain layer and a second diffusion barrier disposed between the first drain layer and second drain layer.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell region and a mark region, forming a first mask layer above the stacked layer, and forming a second mask layer above the first mask layer; forming the second mask layer into first mask pattern features and forming a first alignment mark pattern feature; forming second mask pattern features and then removing the first mask pattern features; opening part of the second mask pattern features and forming a third mask layer having an opening; removing part of the second mask pattern features; removing the third mask layer; forming a fourth mask layer; etching the first mask layer; removing the fourth mask layer and then removing the second mask pattern features; and etching the stacked layer.

Abstract: Embodiments of the invention provide a thin film transistor, a method of manufacturing the same, an array substrate comprising the thin film transistor and a display device. The method of manufacturing the thin film transistor comprises steps of forming a gate electrode (220), a gate insulating layer (230), an oxide active layer (240), a source electrode (260) and a drain electrode (270) on a substrate (210). After forming the oxide active layer (240), the method further comprises a step of forming an etch barrier layer (250) of a metal oxide on the oxide active layer (240).

Abstract: Exemplary embodiments provide compositions for a solution process, electronic devices fabricated using the same, and fabrication methods thereof. An oxide nano-structure is formed using a sol-gel process. An oxide thin film transistor is formed using the oxide nano-structure.

Abstract: The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level.

Abstract: An embodiment of the invention provides a thin film transistor liquid crystal display (TFT-LCD) array substrate comprising: a gate line and a data line that intersect with each other to define a pixel region; and a pixel electrode and a thin film transistor formed in the pixel region. The thin film transistor comprises: a gate electrode connected with the gate line; a semiconductor island positioned above the gate electrode; and a source electrode and a drain electrode that are formed on the semiconductor island. A surface of the semiconductor island contacting with the source electrode and the drain electrode comprises ohmic contact regions subject to a surface treatment and a region of the semiconductor layer between the source electrode and the drain electrode is covered with a barrier layer. Another embodiment of the invention provides a method of manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate.

Abstract: An n-type organic thin-film transistor including a substrate, a gate, and a dielectric layer covering the substrate and the gate. A semiconductor-insulator polymer blend layer is disposed on the dielectric layer; A source and a drain are disposed on top of the semiconductor-insulator polymer blend layer.

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

Abstract: A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.

Abstract: To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target. In that case, partial pressure of water in a deposition chamber before or in the deposition is set to be lower than or equal to 10?3 Pa, preferably lower than or equal to 10?4 Pa, more preferably lower than or equal to 10?5 Pa. Thus, a dense oxide semiconductor film is obtained. The density of the oxide semiconductor film is higher than 6.0 g/cm3 and lower than 6.375 g/cm3.

Abstract: Embodiments described herein generally take the form of methods and systems for identifying and/or reducing a parasitic capacitance variation in a capacitive integrated touch-sensing module that may arise from proximity to a nearby electronic display.

Abstract: One object of this invention is to provide a structure of integrated power transistor device having low thermal budget metal oxynitrides as the active channel on a CMOS logic and control circuit chip to form an integrated intelligent power switching module for power switching. The other object of this invention is to provide a structure of integrated power amplifier transistor device having low thermal budget metal oxynitride active channel layer on a CMOS logic and control circuit chip to form an integrated intelligent microwave power amplifier for RF power amplification.

Abstract: An object of an embodiment of the present invention is to provide a semiconductor device which includes a transistor including an oxide semiconductor with high field-effect mobility, a small variation in threshold voltage, and high reliability. The semiconductor device includes a transistor which includes an insulating substrate from which oxygen is released by heat treatment and an oxide semiconductor film over the insulating substrate. A channel is formed in the oxide semiconductor film. The insulating substrate from which oxygen is released by heat treatment can be manufactured by implanting oxygen ions into at least a region of an insulating substrate on the side provided with the oxide semiconductor film.

Abstract: A display device includes an array substrate and a color filter substrate. The array substrate including data lines in a periphery circuit area, and the color filter substrate including a common electrode. A portion of the common electrode of the color filter substrate corresponding to the periphery circuit area of the array substrate includes a plurality of stripe electrodes separated from each other, extending in a length direction of the data lines and overlapped with the data lines. For each data line, two adjacent stripe electrodes among the plurality of stripe electrodes overlapped with the data line are connected through a bypass electrode which is substantially not overlapped with the data line. In case of the data lines being broken or shorted with the common electrode, the data line can be repaired by using a separate stripe electrode, thereby enabling normal operation of the circuitry.

Abstract: The present invention provides a display device which is provided with a Cu alloy film having high adhesion to an oxygen-containing insulator layer and a low electrical resistivity. The present invention relates to a Cu alloy film for a display device, said film having a stacked structure including a first layer (Y) composed of a Cu alloy containing, in total, 1.2-20 atm % of at least one element selected from among a group composed of Zn, Ni, Ti, Al, Mg, Ca, W, Nb and Mn, and a second layer (X) composed of pure Cu or a Cu alloy having Cu as a main component and an electrical resistivity lower than that of the first layer (Y). A part of or the whole first layer (Y) is directly in contact with an oxygen-containing insulator layer (27), and in the case where the first layer (Y) contains Zn or Ni, the thickness of the first layer (Y) is 10-100 nm, and in the case where the first layer (Y) does not contain Zn and Ni, the thickness of the first layer (Y) is 12-100 nm.

Abstract: A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

Abstract: A selective crystallization method includes placing a first substrate including first crystallization regions on a second substrate including second crystallization regions such that the first crystallization regions and the second crystallization regions are arranged alternately, and crystallizing the alternately-arranged first crystallization regions and the second crystallization regions with a laser beam. A laser crystallization apparatus can be used in the selective crystallization method.

Abstract: A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the transistor capable of high-speed response and high-speed operation is provided. The transistor includes the oxide semiconductor film including a channel formation region and low-resistance regions in which a metal element and a dopant are included. The channel formation region is positioned between the low-resistance regions in the channel length direction. In a manufacturing method of the transistor, the metal element is added by heat treatment performed in the state where the oxide semiconductor film is in contact with a film including the metal element and the dopant is added through the film including the metal element by an implantation method so that the low resistance regions in which a metal element and a dopant are included are formed.

Abstract: This TFT substrate (100A) includes: a gate connecting layer (3a) formed on a substrate (1) out of a same conductive film as a gate electrode (3) or a transparent connecting layer (2a) formed on the substrate (1) out of a same conductive film as a first transparent electrode (2); an oxide layer (5z) which is formed on an insulating layer (4) and which includes at least one conductor region (5a); and a source connecting layer (6a) formed on the oxide layer (5z) out of a same conductor film as a source electrode (6s). The source connecting layer (6a) is electrically connected to either the gate connecting layer (3a) or the transparent connecting layer (2a) via the at least one conductor region (5a).

Abstract: A flat panel image sensor includes a thin film transistor (TFT) and diode array, a conformal insulating layer on a top surface of the TFT and diode array, a planarized dielectric layer on a top surface of the conformal insulating layer, a first metalized via in the planarized dielectric layer and the conformal insulating layer to contact a metalized portion of the TFT and diode array, a second metalized via in the planarized dielectric layer and the conformal insulation layer to contact a diode portion of the TFT and diode array, and a passivation layer over the first and second vias and an upper surface of the planarized dielectric layer.

Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: The present invention discloses an array substrate, a fabricating method of thereof and a display device. The array substrate comprises a base substrate, and a pattern of a gate, a pattern of a gate insulating layer, a pattern of a pixel electrode, a pattern of an ohmic contact layer, a pattern of an active layer, and a pattern of source-drain electrodes formed on the base substrate. The pattern of the pixel electrode is positioned between the pattern of the gate insulating layer and the pattern of the ohmic contact layer. The technical solutions of the present disclosure can reduce one mask process, thus lowering fabrication cost and improving product yield.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. In the manufacturing method, the needed patterns can be formed by just three photolithography processes, wherein the semiconductor layer and the etch stop layer are formed by just one photolithography process. The method reduces one photolithography process compared to the method of the state of the art, which forms the pattern of the semiconductor layer and the etch stop layer by two photolithography processes respectively, thereby greatly reducing the manufacturing cost and improving the production efficiency.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: The present invention discloses a thin-film-transistor array substrate and a manufacturing method thereof. The array substrate includes a thin-film transistor and a compensation electrode. A gate electrode of the thin-film transistor is a portion of a scan-signal line and has an opening, and the opening extends to a side of the scan-signal line. A drain electrode of the thin-film transistor is disposed correspondingly to the opening. A source electrode of the thin-film transistor extends from a side of a data-signal line and surrounds the drain electrode. The compensation electrode extends from another side of the scan-signal line and corresponds to the gate electrode. Therefore, the present invention is capable of reducing parasitic capacitance between the drain electrode and the gate electrode without increasing the resistance value of the scan-signal line.

Abstract: The present invention provides a thin film transistor. An active layer of the thin film transistor comprises a plurality of active semiconductor sub-layers and a plurality of insulation sub-layers, which are stacked alternately. A source and a drain of the thin film transistor are electrically connected to the plurality of active semiconductor sub-layers. Correspondingly, the present invention further provides a method for manufacturing a thin film transistor, and an array substrate. The present invention can effectively increase channel current of the active layer in a thin film transistor, and solves the problem of small channel current resulted from low carrier mobility of the active layer.

Abstract: A TFT array manufacturing method is disclosed herein and includes steps: forming a first metal layer on a substrate; depositing a first insulating layer to cover the first metal layer; forming an oxide semiconductor layer on the first insulating layer in a TFT area; forming a second insulating layer on the first insulating layer and the oxide semiconductor layer; etching the second insulating layer in the TFT area to expose the oxide semiconductor layer and etching the second insulating layer and the first insulating layer in a signal wire area simultaneously to expose the first metal layer; and forming a second metal layer on the second insulating layer of the TFT area, and the second metal layer being connected the oxide semiconductor layer, and forming the second metal layer on the first metal layer of the signal wire area to contact the first metal, layer.

Abstract: An organic light emitting diode display includes a substrate including a plurality of subpixel areas, a plurality of pixel electrodes positioned corresponding to each of the plurality of subpixel areas on the substrate, a white emission layer formed on the plurality of pixel electrodes; a common electrode covering the white emission layer, a plurality of capping layers positioned corresponding to each of the plurality of subpixel areas on the common electrode, and a color filter layer including a plurality of filter layers corresponding to each of the plurality of subpixel areas. At least two capping layers among the plurality of capping layers have any one of a refractive index and a thickness different from each other.

Abstract: A thin film transistor having low off-state current and excellent electrical characteristics can be manufactured. In an inverted staggered thin film transistor including a semiconductor film in which at least a microcrystalline semiconductor region and an amorphous semiconductor region are stacked, a conductive film and an etching protective film are stacked over the semiconductor film; a mask is formed over the etching protective film; first etching treatment in which the etching protective film, the conductive film, and the amorphous semiconductor region are partly etched is performed; then, the mask is removed. Next, second etching treatment in which the exposed amorphous semiconductor region and the microcrystalline semiconductor region are partly dry-etched is performed using the etched etching protective film as a mask so that the microcrystalline semiconductor region is partly exposed to form a back channel region.

Abstract: A thin film transistor and a manufacturing method thereof. The thin film transistor includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a first semiconductor disposed on the gate insulating layer; a second semiconductor disposed on the first semiconductor and having a different plane shape from the first semiconductor; and a source electrode and a drain electrode that are disposed on the second semiconductor and face each other.

Abstract: Exemplary embodiments provide compositions for a solution process, electronic devices fabricated using the same, and fabrication methods thereof. An oxide nano-structure is formed using a sol-gel process. An oxide thin film transistor is formed using the oxide nano-structure.

Abstract: A varactor comprising two Schottky diodes, each diode comprising a substrate and a plurality of layers formed on the substrate including at least one GaN layer and at least one semi-insulating material layer formed of a material with an energy gap greater than 3.5 and free carrier mobility less than 300 cm2/V-s; the Schottky diodes having cathodes adapted to be connected to an AC voltage input and being configured so that as the AC voltage applied to the cathodes increases the capacitance decreases nonlinearly, the nonlinear transition from high capacitance to low capacitance being adjustable by utilizing the intrinsic carrier concentration of the semi-insulating layer to obtain an optimal nonlinear transition for the predetermined AC voltage applied to the cathodes. A method of making a varactor comprising computer modeling to produce capacitance-voltage curves, modifying at least one semi-insulating region, and modeling power input/output efficiency for a predetermined input signal.

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract: To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.