Abstract: This disclosure provides a shift register unit comprising an access control module and a shift register module. The access control module is used for controlling access of an input signal and a reset signal. The shift register module is used for outputting the accessed input signal or reset signal under the driving of a clock signal. The access control module comprises a depletion field effect transistor. The shift register unit further comprises a connection control module arranged between the access control module and the shift register module for blocking the connection between the access control module and the shift register module when the shift register module performs outputting. By means of the design of the connection control module in this disclosure, when the shift register unit performs outputting, its high potential leakage path is blocked, so as to reduce the leakage current greatly, and ensure normal output of the shift register unit.

Abstract: A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.

Abstract: Peripheral devices for a three-dimensional memory device can be formed over an array of memory stack structures to increase areal efficiency of a semiconductor chip. First contact via structures and first metal lines are formed over an array of memory stack structures and an alternating stack of insulating layers and electrically conductive layers. A semiconductor material layer including a single crystalline semiconductor material or a polycrystalline semiconductor material is formed over first metal lines. After formation of semiconductor devices on or in the semiconductor material layer, metal interconnect structures including second metal lines and additional conductive via structures are formed to electrically connect nodes of the semiconductor devices to respective first metal lines and to memory devices underneath.

Abstract: The present invention provides a method for manufacturing a LTPS TFT substrate and a LTPS TFT substrate. The method for manufacturing the LTPS TFT substrate of the present invention forms a thermally conductive electrical insulation layer having excellent properties of electrical insulation and thermal conductivity on a buffer layer to quickly absorb a great amount of heat during a RTA process to be transferred to an amorphous silicon layer in contact therewith so that the portion of the amorphous silicon at this site shows an increased efficiency of crystallization, whereby polycrystalline silicon has an increased grain size and reduced gain boundaries and thus the mobility of charge carriers of a corresponding TFT device is increased and the influence of the leakage current caused by grain boundary is reduced.

Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.

Abstract: A single field effect transistor capacitor-less memory device, and method of operating the same, including a drain region, a source region, an intrinsic channel region between the drain region and the source region forming the single field effect transistor and a base. The device further includes a fin structure comprising the source region, the intrinsic channel and the drain region, the fin structure extending outwardly from the base, and a double gate comprising a first gate connected to a first exposed lateral face of the intrinsic channel region for transistor control, and a second gate connected to a second exposed lateral face of the intrinsic channel region to generate a potential well for storing mobile charge carriers permitting memory operation, the first gate and the second gate being asymmetric for asymmetric electrostatic control of the device.

Abstract: A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.

Abstract: There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is ?, a gate capacitance per unit area is Co, a maximum gate voltage is Vgs(max), a channel width is W, a channel length is L, an average value of a threshold voltage is Vth, a deviation from the average value of the threshold voltage is ?Vth, and a difference in emission brightness of a plurality of EL elements is within a range of ±n %, a semiconductor display device is characterized in that A = 2 ? ? Id ? * C 0 A ( Vgs ( max ) - Vth ) 2 ? W L ? ( 1 + n 100 - 1 ) 2 * A ? ? ? Vth 2 ? ? ? ? Vth ? ? ( 1 + n 100 - 1 ) * A * L / W .

Abstract: An organic light-emitting display apparatus includes a first substrate, a display unit that defines an active area on the first substrate, a second substrate on the display unit, a circuit pattern on outer sides of the active area on the first substrate, a sealant between the first substrate and the second substrate, the sealant adhering the first substrate to the second substrate and overlapping at least a part of the circuit pattern, and a detecting unit that overlaps the at least a part of the circuit pattern and detects whether the circuit pattern is damaged.

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.

Abstract: In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.

Abstract: A solder print inspecting device includes three-dimensional measurement lighting unit that directs a specific light at a printed substrate, a CCD camera for imaging the printed substrate that is illuminated by the light, three-dimensional calculating unit that performs a three-dimensional measurement of cream solder based on image data, etc., and displaying unit that displays a three-dimensional image showing a three-dimensional shape of the cream solder, along with displaying an arrow image showing an operating direction of a squeegee in a solder printing machine, an arrow image showing a conveying direction of the printed substrate, etc.

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a first circuit including at least one of the first transistors, and the first circuit has a first circuit output connected to at least one of the second transistors, wherein the at least one of the second transistors is connected to a device output that is designed to be connected to external devices, and wherein the at least one of the second transistors is substantially larger than the at least one of the first transistors.

Abstract: A method for producing a low-emissivity layer system includes the steps of forming at least one low emissivity layer on at least one side of the substrate by deposition, and subsequent brief tempering of a deposited low emissivity layer by electromagnetic radiation, avoiding an immediate heating up of the substrate. A device for performing the method includes a flash lamp arrangement.

Abstract: A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed.

Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Abstract: A semiconductor device according to an embodiment includes a stacked body, and a semiconductor pillar. The stacked body includes first insulating layers and conductive layers. The conductive layer includes silicon. At least one of the conductive layers includes a first portion, a second portion, and a third portion. The first portion includes a first element selected from at least one of boron and phosphorus. The second portion includes the first element. The third portion is provided between the first portion and the second portion in a stacking direction of the conductive layers and the first insulating layers. The third portion includes a second element. The second element is selected from at least one of carbon, nitrogen, oxygen, and germanium. The semiconductor pillar pierces through the stacked body. The semiconductor pillar extends in the stacking direction.

Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Abstract: An electronic device comprising an optical gate, an electrical input an electrical output and a wide bandgap material positioned between the electrical input and the electrical output to control an amount of current flowing between the electrical input and the electrical output in response to a stimulus received at the optical gate can be used in wideband telecommunication applications in transmission of multi-channel signals.

Abstract: Example embodiments are directed to a light-sensing circuit, a method of operating the light-sensing circuit, and a light-sensing apparatus including the light-sensing circuit. The light-sensing circuit includes a light-sensitive oxide semiconductor transistor that senses light; and a switching transistor connected to the light-sensing transistor in series and configured to output data. During a standby time, a low voltage is applied to the switching transistor and a high voltage is applied to the light-sensitive oxide semiconductor transistor, and when data is output, the high voltage is applied to the switching transistor and the low voltage is applied to the light-sensitive oxide semiconductor transistor.

Abstract: An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.

Abstract: Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.

Abstract: An electronic device including at least one electronic component and a method of manufacturing the same are provided. The electronic device may include a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer, and a first metal layer disposed on the insulating layer. The insulating layer may have a pattern corresponding to a pattern of the semiconductor layer or the first metal layer. The flexible layer has a Young's modulus less than 40 GPa and is disposed on the substrate to encapsulate the semiconductor layer. At least one first opening penetrates the flexible layer. At least one second metal layer is disposed on the flexible layer and in the first opening and electrically connected to the semiconductor layer.

Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.

Abstract: An ambipolar electronic device is disclosed. The device may include a field-effect transistor (FET), which may have a handle substrate layer, two contacts and an inorganic crystalline layer between the handle substrate layer and the contacts. The inorganic crystalline layer may have a doped channel region between the contacts. The FET may also have a dielectric layer between the contacts, attached to the inorganic crystalline layer, and a gate layer, attached to the dielectric layer. The FET may conduct current, in response to a first gate voltage applied to the gate layer, using electrons as a majority carrier, along the length of the channel region between the contacts. The FET may also conduct current, in response to a second gate voltage applied to the gate layer, using holes as a majority carrier, along the length of the channel region between the contacts.

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract: Provided is an active matrix display device using an organic EL panel including: a plurality of pixel circuits each including an organic light emitting diode arranged in a pixel region of the organic EL panel and a plurality of transistors configured to drive the organic light emitting diode; a plurality of scanning lines arranged along a first direction in the organic EL panel; and a plurality of data lines arranged along a second direction that is orthogonal to the first direction. In at least one set of pixel circuits that are adjacent in the first direction, gate electrodes and impurity diffusion regions of the plurality of transistors have an axisymmetric layout. Gate electrodes of at least one set of transistors that are symmetrically arranged in the at least one set of pixel circuits are integrated.

Abstract: A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is in an amorphous state in a peripheral area at an outer peripheral part of the substrate, and the protection layer is crystallized in an internal area of the protection layer that is inside the peripheral area of the protection layer.

Abstract: A thin film transistor (TFT) and manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor comprises a substrate; an active layer formed on the substrate; a first conductive contact layer and a second conductive contact layer formed on the active layer; an etch-stop layer formed over the first contact layer and the second contact layer; and a source connected with the first contact layer, a drain connected with the second contact layer and a gate arranged between the source and the drain formed over the etch-stop layer. The TFT has a simple structure and better performance.

Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.

Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.

Abstract: There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is ?, a gate capacitance per unit area is Co, a maximum gate voltage is Vgs(max), a channel width is W, a channel length is L, an average value of a threshold voltage is Vth, a deviation from the average value of the threshold voltage is ?Vth, and a difference in emission brightness of a plurality of EL elements is within a range of ±n %, a semiconductor display device is characterized in that A = 2 ? ? I ? ? d ? * C 0 A ( Vgs ( max ) - Vth ) 2 ? W L ? ( 1 + n 100 - 1 ) 2 * A ? ? ? Vth 2 ? ? ? ? Vth ? ? ( 1 + n 100 - 1 ) * A * L / W .

Abstract: Embodiments of the invention provide a thin film transistor and a manufacturing method thereof and a display device. The thin film transistor includes a gate electrode, a gate insulation layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are connected to the active layer by the ohmic contact layer. The ohmic contact layer is provided at a lateral side of the active layer and contacts the lateral side of the active layer.

Abstract: One object is to propose a memory device in which a period in which data is held can be ensured and memory capacity per unit area can be increased. The memory device includes a memory element, a transistor including an oxide semiconductor in an active layer for control of accumulating, holding, and discharging charge in the memory element, and a capacitor connected to the memory element. At least one of a pair of electrodes of the capacitor has a light-blocking property. Further, the memory device includes a light-blocking conductive film or a light-blocking insulating film. The active layer is positioned between the electrode having a light-blocking property and the light-blocking conductive film or the light-blocking insulating film.

Abstract: This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

Abstract: An EL display having high operating performance and reliability is provided. LDD regions 15a through 15d of a switching TFT 201 formed in a pixel are formed such that they do not overlap gate electrodes 19a and 19b to provide a structure which is primarily intended for the reduction of an off-current. An LDD region 22 of a current control TFT 202 is formed such that it partially overlaps a gate electrode 35 to provide a structure which is primarily intended for the prevention of hot carrier injection and the reduction of an off-current. Appropriate TFT structures are thus provided depending on required functions to improve operational performance and reliability.

Abstract: Disclosed is a technique for suppressing fluctuation of device characteristics in thin film transistors using an oxide semiconductor film as a channel layer. In a thin film transistor using an oxide semiconductor film as a channel layer (4), said channel layer (4) is configured from an oxide semiconductor having as main materials a zinc oxide and tin oxide with introduced group IV elements or group V elements, wherein the ratio (A/B) of the impurity concentration (A) of the group IV elements or group V elements contained in the channel layer (4) and the impurity concentration (B) of the group III elements contained in the channel layer (4) satisfies A/B?1.0, and ideally A/B?0.3.

Abstract: A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

Abstract: An organic light emitting diode display device includes a substrate including a pixel portion and a peripheral portion, a semiconductor layer including a pixel switching semiconductor layer and a driving semiconductor layer formed on the pixel portion, and a peripheral switching semiconductor layer formed on the peripheral portion. A first gate insulating layer is formed on the semiconductor layer. A peripheral switching gate electrode is formed on the first gate insulating layer of the peripheral portion, and a pixel switching gate electrode and a driving gate electrode are formed on the first gate insulating layer of the pixel portion. A length of a peripheral switching low concentration doping region formed in the peripheral switching semiconductor layer may be larger than a length of a pixel switching low concentration doping region and a driving low concentration doping region formed in the pixel switching semiconductor layer and the driving semiconductor layer, respectively.

Abstract: A wireless power transmitting device for a wireless power communication system. The wireless power transmitting device includes: a circuit board including an insulating layer and a ground formed on the insulating layer; a core of a magnetic substance disposed on the circuit board to have a concave portion; a wire-wound coil accommodated in the concave portion to have one end for receiving a power through the circuit board and the other end connected to the ground; and a metal layer disposed between the core and the insulating layer to be connected to the ground.

Abstract: Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source electrode over a first region of the channel layer, and a drain electrode over a second region of the channel layer.

Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

Abstract: Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.

Abstract: A thin film transistor substrate may include a gate electrode on a base substrate, a gate insulation layer covering the gate electrode on the base substrate, an active pattern on the gate insulation layer, an etch-stop layer pattern partially exposing the active pattern, a source electrode and a drain electrode in contact with a portion of the exposed active pattern, and an inorganic barrier layer on the source electrode, the drain electrode, and the etch-stop layer pattern. The active pattern may be superimposed over the gate electrode. The source electrode and the drain electrode may be superimposed over both ends of the gate electrode. The inorganic barrier layer may be in contact with a remaining portion of the exposed active pattern.

Abstract: A method of manufacturing a solar cell, including: forming a first conductivity type semiconductor layer extending along a predetermined direction on aback surface of a semiconductor substrate that has a light-receiving surface and the back surface opposite to the light-receiving surface, the first-conductivity-type semiconductor layer being divided into plural island-shaped sections arranged side by side in the predetermined direction; forming a semiconductor layer of a second conductivity type in the predetermined direction on the back surface; and forming conductive layers respectively on the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer by using a conductive paste, the conductive layer to be formed on the first-conductivity-type semiconductor layer being formed by a printing method such that the conductive layer to be formed on the first-conductivity-type semiconductor layer extends on a line of the plural island-shaped sections to bridge adjacent two of

Abstract: A method of manufacturing a thin film transistor having a compound semiconductor with oxygen as a semiconductor layer and a method of manufacturing an organic light emitting display having the thin film transistor include: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer including oxygen ions on the gate insulating layer, and including a channel region, a source region, and a drain region; forming a source electrode and a drain electrode to contact the semiconductor layer in the source region and the drain region, respectively; and forming a passivation layer on the semiconductor layer by coating an organic material, wherein a carrier density of the semiconductor layer is maintained in the range of 1E+17 to 1E+18/cm3 to have stable electrical property.

Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.