Abstract: A thin film transistor substrate may include a gate electrode on a base substrate, a gate insulation layer covering the gate electrode on the base substrate, an active pattern on the gate insulation layer, an etch-stop layer pattern partially exposing the active pattern, a source electrode and a drain electrode in contact with a portion of the exposed active pattern, and an inorganic barrier layer on the source electrode, the drain electrode, and the etch-stop layer pattern. The active pattern may be superimposed over the gate electrode. The source electrode and the drain electrode may be superimposed over both ends of the gate electrode. The inorganic barrier layer may be in contact with a remaining portion of the exposed active pattern.

Abstract: An active device includes a gate, a gate insulation layer, a channel layer, a first passivation layer, a second passivation layer, a source and a drain. The gate insulation layer is disposed on the substrate and covers the gate. The channel layer is disposed on the gate insulation layer and has a semiconductor section disposed corresponding to the gate and a conductive section located around the semiconductor section. The first passivation layer is disposed on the channel layer and covers the semiconductor section. The second passivation layer is disposed on and covers the first passivation layer. The source and the drain are disposed on the gate insulation layer, and extended along peripheries of the conductive section, the first and the second passivation layers to be disposed on the second passivation layer. A portion of the second passivation layer is exposed between the source and the drain.

Abstract: An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed. The gate electrode has an edge region surrounding an interior region of the gate electrode and the edge region of the gate electrode is thicker than the interior region of the gate electrode. A semiconductor layer is formed over the gate electrode. A source electrode and a drain electrode of the thin film transistor are formed that define a channel region in the semiconductor layer. The channel region is located over the interior region of the gate electrode. Additionally, the gate electrode may be formed with a half-tone mask that results in the edge region of the gate electrode being thicker than the interior region of the gate electrode.

Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.

Abstract: The present invention provides a thin film transistor including a first drain electrode, a second drain electrode, a first source electrode, and a second source electrode, wherein the first drain electrode and the first source electrode jointly define a first U-shaped channel facing toward a first direction. Wherein the second drain electrode and the second source electrode jointly define a second U-shaped channel facing a second direction which is different to the first direction, wherein the bottom width of the second U-shaped channel is larger then the bottom width of the first U-shaped channel. The present invention further provides an array substrate of the thin film transistor, and a method for making the array substrate. By way of the forgoing, short-circuit between the source electrode and the drain electrode resulted from the cleaning agent residue located in the bottom of the U-shaped channel of the thin film transistor can be avoided.

Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.

Abstract: There is provided a thin film transistor including an active layer on a substrate (the active layer including polysilicon and a metal catalyst dispersed in the polysilicon, a source area, a drain area, and a channel area), a gate electrode disposed on the channel area of the active layer, a source electrode electrically connected to the source area, and a drain electrode electrically connected to the drain area, wherein the gate electrode, the source area, and the drain area of the active layer include metal ions, the source area and the drain area are separate from each other, and the channel is disposed between the source area and the drain area.

Abstract: A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.

Abstract: To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 ?m to 5 ?m. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.

Abstract: A dielectric layer for an electronic device, such as a thin-film transistor, is provided. The dielectric layer comprises a molecular glass. The resulting dielectric layer is very thin, pure, and stable. Processes and compositions for fabricating such a dielectric layer are also disclosed.

Abstract: Complementary metal oxide semiconductor (CMOS) ultrasonic transducers (CUTs) and methods for forming CUTs are described. The CUTs may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers. The CUTs may be used in ultrasound devices such as ultrasound imaging devices and/or high intensity focused ultrasound (HIFU) devices.

Abstract: In order to form a structure in which an oxide semiconductor layer through which a carrier flows is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which a carrier flows is away from the gate insulating film containing silicon is provided. Specifically, a buffer layer is provided between the gate insulating film and the oxide semiconductor layer. Both the oxide semiconductor layer and the buffer layer are formed using materials containing indium and another metal element. The composition of indium with respect to gallium contained in the oxide semiconductor layer is higher than the composition of indium with respect to gallium contained in the buffer layer. The buffer layer has a smaller thickness than the oxide semiconductor layer.

Abstract: A semiconductor device and method of making the same are provided. The method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.

Abstract: A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating film, and a control electrode. The first semiconductor region includes a silicon carbide of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, includes a silicon carbide of a second conductivity type, and has a first main surface. The third semiconductor region is provided on the second semiconductor region and includes the silicon carbide of the first conductivity type. The film is provided on the surface. The electrode is provided on the film, and has a first region close to the third semiconductor region side, and a second region closer to the first semiconductor region side than the first region. An effective work function of the first region is larger than an effective work function of the second region.

Abstract: The present invention proposes a TFT switch and a method for manufacturing the same. The TFT switch includes a gate, a drain, a source, a semiconductor layer and a fourth electrode. The drain is connected to a first signal, the gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.

Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.

Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.

Abstract: An object is to suppress occurrence of oxygen deficiency. An oxide semiconductor film is formed using germanium (Ge) instead of part of or all of gallium (Ga) or tin (Sn). At least one of bonds between a germanium (Ge) atom and oxygen (O) atoms has a bond energy higher than at least one of bonds between a tin (Sn) atom and oxygen (O) atoms or a gallium (Ga) atom and oxygen (O) atoms. Thus, a crystal of an oxide semiconductor formed using germanium (Ge) has a low possibility of occurrence of oxygen deficiency. Accordingly, an oxide semiconductor film is formed using germanium (Ge) in order to suppress occurrence of oxygen deficiency.

Abstract: The present invention provides an anode connection structure of an organic light-emitting diode and a manufacture method thereof. The structure includes: a thin-film transistor (20) and an anode (40) of an organic light-emitting diode arrange don the thin-film transistor (20). The thin-film transistor (20) includes a low-temperature poly-silicon layer (24) formed on a substrate (22), a gate insulation layer (26) formed on the low-temperature poly-silicon layer (24), a gate formed on the gate insulation layer (26), a protection layer (27) formed on the gate, and a source/drain (28) formed on the protection layer (27). The anode (40) of the organic light-emitting diode is connected to the low-temperature poly-silicon layer (24).

Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.

Abstract: A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.

Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.

Abstract: The present invention provides an array substrate, a method for manufacturing the same and a display device, and relates to technical field of displays. The method for manufacturing an array substrate comprises forming a metal layer on a substrate and removing superficial metallic oxide on the metal layer by a washing process. The method for manufacturing an array substrate according to the present inversion can remove the superficial metal oxide on the metal layer and improve the performance of a TFT.

Abstract: A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.

Abstract: A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Abstract: A high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (SixC1-x) functional layer formed on the AlGaN layer.

Abstract: A semiconductor device of the present invention includes an n-channel first thin film transistor and a p-channel second thin film transistor on one and the same substrate. The first thin film transistor has a first semiconductor layer (27), and the second thin film transistor has a second semiconductor layer (22). The first semiconductor layer (27) and the second semiconductor layer (22) are formed from one and the same film. Each of the first semiconductor layer (27) and the second semiconductor layer (22) has a slope portion (27e, 22e) positioned in the periphery and a main portion (27m, 22m) which is a portion excluding the slope portion. A p-type impurity is introduced into only a part of the slope portion (27e) of the first semiconductor layer with higher density than the main portion (27m) of the first semiconductor layer, the main portion (22m) of the second semiconductor layer, and the slope portion (22e) of the second semiconductor layer.

Abstract: Provided is a method of manufacturing a gradually stretchable substrate. The method includes forming convex regions and concave regions on a top surface of a stretchable substrate by compressing a mold onto the stretchable substrate and forming non-stretchable patterns by filling the concave regions of the stretchable substrate. The stretchable substrate includes a stretchable region defined by the non-stretchable patterns, the non-stretchable patterns have side surfaces in contact with the stretchable region, and the side surfaces of the non-stretchable patterns are formed of protrusions and a non-protrusion between the protrusions repetitively connected to one another.

Abstract: In a flat panel display (FPD) and a method of manufacturing the same, the FPD includes a substrate, a semiconductor layer formed on the substrate, a wiring line formed on the substrate so as to be separated from the semiconductor layer, an insulating layer formed on the semiconductor layer and the wiring line, a gate electrode formed on the insulating layer formed on the semiconductor layer and extended to a top of the wiring line, and a source electrode and a drain electrode coupled to a source region and a drain region, respectively, of the semiconductor layer. Capacitance is formed by the gate electrode and the wiring line.

Abstract: According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.

Abstract: The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract: A thin film transistor, a method of manufacturing the same, and a display device including the same, the thin film transistor including a substrate; a polysilicon semiconductor layer on the substrate; and a metal pattern between the semiconductor layer and the substrate, the metal pattern being insulated from the semiconductor layer, wherein the polysilicon of the semiconductor layer includes a grain boundary parallel to a crystallization growing direction, and a surface roughness of the polysilicon semiconductor layer defined by a distance between a lowest peak and a highest peak in a surface thereof is less than about 15 nm.

Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.

Abstract: A thin film transistor substrate includes a semiconductor pattern on a base substrate, a first insulation member disposed on the semiconductor pattern, a second insulation pattern disposed on the first insulation member, and a gate electrode disposed on the first insulation member and the second insulation pattern. The second insulation pattern overlaps a first end portion of the semiconductor pattern, and exposes a second end portion of the semiconductor pattern opposite to the first end portion. The gate electrode overlaps both the first insulation member and the second insulation pattern.

Abstract: A method of forming an organic thin film transistor the method comprising: seeding a surface outside a channel region with one or more crystallization sites prior to deposition of the organic semiconductor; depositing a solution of the organic semiconductor onto the seeded surface and over the channel region whereby the organic semiconductor begins forming a crystal domain at the or each of the crystallization sites, the or each crystal domain growing from its crystallization site across the channel region in a direction determined by an advancing surface evaporation front; and applying energy to control the direction and rate of movement of the surface evaporation front thereby controlling the direction and rate of growth of the or each crystal domain across the channel region from the one or more crystallization sites outside the channel region.

Abstract: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below a threshold temperature and becomes transparent at a temperature above the threshold temperature.

Abstract: A photosensitive imaging device and a method for forming a semiconductor device are provided. The method includes: providing a first device layer formed on a first substrate, wherein a conductive top bonding pad layer is formed on the first device layer; providing a continuous second device layer formed on a second substrate, wherein a continuous conductive adhesion layer is formed on the continuous second device layer; bonding the first device layer with the second device layer, where the top bonding pad layer on the first device layer is directly connected with the conductive continuous adhesion layer on the continuous second device layer; removing the second substrate; selectively etching the continuous second device and the continuous conductive adhesion layer to form a groove array; and filling up the groove array with an insulation material to form a plurality of second devices. Alignment accuracy may be improved.

Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.

Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.

Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.

Abstract: In a method for manufacturing a semiconductor device including a transistor and a conductive film over a substrate, a first insulating film and a second insulating film are formed over the transistor and the conductive film sequentially. Then, an opening and a recessed portion are formed in the second insulating film using one multi-tone photomask, wherein the opening is deeper than the recessed portion in the second insulating film. By using the opening, a first contact hole exposing one of the electrodes of the transistor is formed through the first and second insulating films and, by using the recessed portion, a second contact hole exposing the first insulating film is formed through the second insulating film. Moreover, an electrode is formed on and in contact with the one of the electrodes in the first contact hole and the first insulating film in the second contact hole.

Abstract: Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled.

Abstract: A thin film transistor is provided. In this thin film transistor, the thickness of the gate is increased. Therefore, the source and drain of this thin film transistor can be disposed on the side wall of the gate to decrease the occupied area of the thin film transistor. An array substrate and a display device using the thin film transistor are also provided.