Abstract: Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a first side and a second side opposite the first side. The first side has a first reticle field and a second reticle field larger than the first reticle field. Plural conductor pads are positioned on the first side in the first reticle field. Plural dummy conductor pads are positioned on the first side in the second reticle field and outside the first reticle field.

Abstract: According to one embodiment, a semiconductor package includes a first substrate, first conductive layers, first semiconductor chips, a second conductive layer, a first terminal, and a second terminal. The first substrate has a first surface. The first conductive layers are provided on the first surface. Each of the first semiconductor chips includes a first electrode and a second electrode. Each of the first conductive layers is connected to at least one of the first electrodes. The second conductive layer is provided on the first surface to be separated from the first conductive layers. The second conductive layer is connected to a plurality of the second electrodes. The first terminal is connected to the first conductive layers. Inductances between the first extension unit and each of the first conductive layers are substantially equal to each other. The second terminal is connected to the second conductive layer.

Abstract: Techniques for designing integrated circuit (IC) package substrates are provided. One of the provided techniques include routing a first set of interconnects in a first region of an IC package substrate based on a first routing template and routing a second set of interconnects in a second region of the IC package substrate based on a second routing template. The first routing template is associated with output pins on the IC package substrate while the second routing template is associated with interconnects on at least one IC die of the multiple IC dies. In one scenario, the first routing template is a common routing template. As such, when a different IC die is used with an identical, or otherwise similar, IC package substrate, interconnects associated with output pins on that IC package substrate does not need to be rerouted as they may be routed based on the common routing template.

Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor layer having an element region and an outer peripheral region, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The metal layer extends to cover at least a portion of a sidewall of the step portion. The method of manufacturing the semiconductor device further includes dividing the semiconductor layer into element regions on an outside of the step portion when viewed from the element region.

Abstract: A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes providing a semiconductor device comprising an integrated circuit die, connectors disposed over the integrated circuit die, and an insulating material disposed over the connectors and the integrated circuit die. The insulating material is removed from over corner regions of the integrated circuit die, and a molding material is disposed over the insulating material and the integrated circuit die. A top portion of the molding material and the insulating material is removed to expose the connectors.

Abstract: An electronic, optoelectronic or electric arrangement contains a circuit carrier having a metallic heat conductor, and a component, which is embedded, inserted or formed in the circuit carrier. The component has at least one electric, electronic or optoelectronic construction element and a rewiring layer, which contains a metallic heat conducting path. A metallic-thermal connection of the rewiring layer and the metallic heat conducting layer of the circuit carrier is provided by the heat conducting path.

Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.

Abstract: A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.

Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

Abstract: A semiconductor device includes: a first semiconductor element; a first substrate provided on the first semiconductor element and including a cavity with reduced pressure; coolant held inside the cavity; a second semiconductor element provided on the first substrate; and a heat spreading member thermally connected to the first substrate and provided with a hole communicated with the cavity.

Abstract: A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

Abstract: A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.

Abstract: The present disclosure provides a CMOS-MEMS device structure. The CMOS-MEMS device structure includes a sensing substrate and a CMOS substrate. The sensing substrate includes a bonding mesa structure. The CMOS substrate includes a top dielectric layer. The sensing substrate and the CMOS substrate are bonded through the bonding mesa structure, and the bonding mesa structure defines a bonding gap between the CMOS substrate and the sensing substrate.

Abstract: A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or more RF devices disposed on the module. The RF-shielding may comprise wirebond structures disposed adjacent to or surrounding an RF device. Two or more intramodule devices may have wirebond structures configured to at least partially block certain types of RF signals disposed between the devices, thereby reducing effects of cross-talk between the devices.

Abstract: A semiconductor device includes a lead frame including a die paddle and a lead, a semiconductor chip, and a clip. The semiconductor chip has a first side and a second side opposite to the first side. The first side is attached to the die paddle and the second side includes a first bond pad and a second bond pad. The clip electrically couples the first bond pad to the lead. The clip contacts the first bond pad at a first edge portion of the first bond pad adjacent to the second bond pad and defines a first cavity between a central portion of the first bond pad and the clip. Solder is within the first cavity to electrically couple the clip to the first bond pad. The semiconductor device includes a first opening to the first cavity to route flux away from the second bond pad during reflow soldering.

Abstract: A multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising at least one outer layer of terminations comprising at least one copper post that is only partially embedded in an outer layer of dielectric such that part of the at least one copper post protrudes beyond surface of the outer layer of dielectric.

Abstract: A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer.

Abstract: A process is disclosed for attaching an RFID tag such as an AK module or QFP package to a flexible surface such as textile or fabric. The process comprises providing a heat fusible label including at least a first layer having a first adhesive layer, a substrate layer including a secondary antenna structure, a heat activated second adhesive layer and a pressure sensitive adhesive (PSA) layer for holding the RFID tag. The process further includes positioning the RFID tag on the PSA layer, pressing the tag against the PSA layer such that the PSA layer holds the tag against the heat fusible label at least temporarily, positioning the heat fusible label with the RFID tag on the flexible surface and applying heat and pressure to the heat fusible label to melt the heat activated layer and to fuse the label to the flexible surface.

Abstract: A high-aspect ratio low resistance through-wafer interconnect for double-sided (TWIDS) fabrication of microelectromechanical systems (MEMS) serves as an interconnection method and structure for co-integration of MEMS and integrated circuits or other microcomponent utilizing both sides of the wafer. TWIDS applied to a three dimensional folded TIMU (timing inertial measurement unit) provides a path for electrical signals from sensors on the front side of the SOI wafer to electronic components on the back side of the wafer, while enabling folding of an array of sensors in a three dimensional shape.

Abstract: A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI) includes a trace portion overlying the passivation layer, and a pad portion connected to the trace portion. A polymer layer includes an upper portion over the PPI, and a plug portion extending into, and encircled by, the pad portion of the PPI.

Abstract: A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface. The top surface defines a first groove. The first groove is substantially ring-shaped. The glue layer is arranged in the top surface and surrounds the first groove. A plurality of glass-frits is distributed in the glue layer.

Abstract: A circuit carrier is disclosed that includes a base body having two flat sides and a plurality of narrow sides, a first conductor track applied to a first flat side of the base body, and a leadframe arranged in the interior of the base body. A method for producing the circuit carrier is also disclosed.

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

Abstract: A device for current measurement comprises a substrate with a first current conductor and a current sensor with a second current conductor. The current sensor is mounted above the first current conductor on the substrate. The second current conductor is formed with integrally attached first and second terminal leads through which the current to be measured is supplied and discharged. The current sensor further comprises a semiconductor chip with a magnetic field sensor mounted on the second current conductor on the side of the second current conductor facing the substrate. The magnetic field sensor is sensitive to a component of the magnetic field extending parallel to the surface of the semiconductor chip and perpendicular to the second current conductor. The second current conductor extends above and parallel to the first current conductor.

Abstract: A method for manufacturing a terminal-strip-equipped electronic component in which terminal strips made of a metal plate are bonded with solder to terminal electrodes of an electronic chip component on two opposing end surfaces. Solder cream is applied to outer surfaces of the terminal electrodes. The terminal strips are thermocompression bonded to the terminal electrodes by placing the electronic chip component between the terminal strips and pressing the terminal strips against the terminal electrodes using a pair of heating elements so as to obtain an electronic component to which the terminal strips are temporarily fixed. The terminal strips are fully fixed to the electronic component by melting the solder cream as a result of heating the electronic component in a heating furnace so as to obtain a terminal-strip-equipped electronic component.

Abstract: A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.

Abstract: An integrated electronic package includes an integrated circuit (IC) die and conductive discrete components. Electrical interconnects are formed directly between bond pads on an active side of the IC die and contacts on the conductive discrete components without an intervening lead frame. The IC die, conductive discrete components and electrical interconnects are embedded in an encapsulation material. Contact surfaces of at least some of the conductive discrete components are exposed from the encapsulation material and can be attached to a printed circuit board in order to mount the integrated electronic package to the printed circuit board.

Abstract: A semiconductor device includes a conductive portion having semiconductor elements provided on a substrate, a case housing the conductive portion, and a lead terminal integrated into the case to be directly connected to the semiconductor elements or an interconnection of the substrate. The lead terminal has a stress relief shape for reliving stress generated in the lead terminal.

Abstract: A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second package has a plurality of pads connected to the pillar bump pins, respectively. A method of forming a package on package (POP) structure includes at least the following steps: providing a first package with a plurality of pillar bump pins; providing a second package with a plurality of pads; and forming the POP structure by connecting the pillar bump pins to the pads.

Abstract: A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

Abstract: A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.

Abstract: A double-sided cooling power module may include a lower-end terminal, at least one pair of power semiconductor chips mounted on the lower-end terminal, at least one pair of horizontal spacers mounted on the at least one pair of power semiconductor chips, an upper-end terminal mounted on the at least one pair of horizontal spacers, and at least one pair of vertical spacers disposed between the upper-end terminal and the lower-end terminal.

Abstract: A manufacturing method of heat dissipation structure applied to mobile device. The heat dissipation structure applied to mobile device includes a heat conduction main body. The heat conduction main body has a heat dissipation side and a heat absorption side. A radiation heat dissipation layer is formed on the heat dissipation side. The heat dissipation structure is disposed in the mobile device to provide a very good heat dissipation effect for the closed space of the mobile device by way of natural convection and radiation. Therefore, the heat dissipation performance of the entire mobile device is greatly enhanced.

Abstract: An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

Abstract: A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface. The top surface defines a first groove. The first groove is substantially ring-shaped. The glue layer is arranged in the top surface and surrounds the first groove. A plurality of glass-fits is distributed in the glue layer.

Abstract: A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Abstract: Radiated noise caused by switching noise of power semiconductor elements in an electrical converter is reduced. The electrical converter is characterized in comprising: a case; a power module mounted on the case and comprising a plurality of power semiconductor elements; a metal plate mounted to the power module and fixed to the case; a control circuit board arranged on the metal plate, for controlling the power semiconductor elements; and a direct-current input terminal electrically connected to a battery. The electrical converter is also characterized in being provided at the bottom with a transmission or motor, and at the top with a connector for connecting the battery and the direct-current input terminal. The electrical converter is further characterized in that the metal plate is curved, and a portion of the curved metal plate is arranged in the space between the control circuit board and the direct-current input terminal.

Abstract: Provided is a small and thin semiconductor device while preventing contamination of a wire bonding terminal caused by creeping-up of a die bond. The semiconductor device includes: a first semiconductor chip having a main surface formed with electrodes; an extension part extended outward from a side end surface of the first semiconductor chip; a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part; a connection terminal provided on the rewiring layer of the extension part; a die bond that fixes the first semiconductor chip and the extension part to a substrate; and in the extension part, a step outside the connection terminal.

Abstract: A method for manufacturing a die assembly, including the steps of: bonding a first wafer of semiconductor material to a second wafer, the second wafer including a respective semiconductor body having a respective initial thickness and forming an integrated electronic circuit; and subsequently reducing the initial thickness of the semiconductor body of the second wafer; and subsequently bonding the second wafer to a third wafer, the third wafer forming a micro-electromechanical sensing structure.

Abstract: A display system with a distributed LED backlight includes: providing a plurality of tile LED light sources, each tile LED light source having a tile and a plurality of similar LED light sources on each tile connected for emitting light therefrom; orienting the plurality of tile LED light sources for illuminating a display from the back of the display; and integrating the plurality of tile LED light sources into a thermally and mechanically structurally integrated distributed LED tile matrix backlight light source.

Abstract: There is provided a semiconductor module and a method for manufacturing the same which make it possible to joint the electrode of the bare-chip transistor and the wiring pattern on the substrate by solder mounting operation, in the same process of solder mounting operation for mounting the bare-chip transistor or other surface mounting devices on the wiring patterns on the substrate. A semiconductor module includes: a plurality of wiring patterns formed on an insulating layer; a bare-chip transistor mounted on one wiring pattern out of the plurality of wiring patterns via a solder; and a copper connector constituted of a copper plate for jointing an electrode formed on a top surface of the bare-chip transistor and another wiring pattern out of the plurality of wiring patterns via a solder.

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal and a second terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract: An embodiment of the invention provides a light emitting diode package. The light emitting diode package includes at least three light emitting diode chips; first leads comprising at least three chip mounting sections on which the at least three light emitting diode chips are mounted, respectively; second leads separated from the first leads and connected to the light emitting diode chips via wires, respectively; and a substrate having the first leads and the second leads formed thereon, wherein the at least three chip mounting sections are arranged around a center of the substrate through which an optical axis of the light emitting diode package passes.

Abstract: A package structure includes a first insulation layer, a first conductive layer, a direct bond copper substrate, and a first electronic component. A first conductive via is formed in the first insulation layer. The first conductive layer is disposed on a top surface of the first insulation layer and in contact with the first conductive via. The direct bond copper substrate includes a second conductive layer, a third conductive layer and a ceramic base. The ceramic base is disposed on a bottom surface of the first insulation layer and exposed to the first insulation layer by press-fit operation. The first electronic component is embedded within the first insulation layer and disposed on the second conductive layer. The first electronic component includes a first conducting terminal. The first conducting terminal is electrically connected with the second conductive layer and/or electrically connected with the first conductive layer through the first conductive via.

Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.

Abstract: An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads are arranged in a ball grid array (BGA), and the BGA includes a plurality of corners. A metal dam is disposed around each of the plurality of corners of the BGA.