Abstract: Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

Abstract: A semiconductor device includes a lead frame having leads arranged in an array that has columns extending in a first direction and rows extending in a second direction. Each lead includes a bond pad portion and a solder pad portion down-set from the bond pad portion. The solder pad portion horizontally extends from the bond pad portion in the first direction. A semiconductor die is mounted on a set of the plurality of leads and electrically connected to the bond pad portion of at least one of the plurality of leads. The semiconductor die, and the plurality of leads are encapsulated by a molding material, wherein the molding material defines a package body, and the solder pad portion of each lead is exposed at a back side of the package body.

Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

Abstract: A semiconductor package structure includes a semiconductor substrate, at least one semiconductor die, an encapsulant, a protection layer, a plurality of conductive elements and a redistribution layer. The semiconductor die is disposed on the semiconductor substrate. The encapsulant covers at least a portion of the semiconductor die, and has a first surface and a lateral surface. The protection layer covers the first surface and the lateral surface of the encapsulant. The conductive elements surround the lateral surface of the encapsulant. The redistribution layer electrically connects the semiconductor die and the conductive elements.

Abstract: A semiconductor substrate has a first doping region arranged at a surface and a second doping region adjacent to the first doping region. A p-n junction between the doping regions is at least partially arranged less than 5 ?m away from a contact area of the first doping region arranged at the substrate surface. A first contact structure is in contact with the first doping region in the contact area of the first doping region and has at least partially an electrically conductive material provided for a diffusion into the semiconductor substrate. The first contact structure is configured so that the conductive material provided for a diffusion into the substrate diffuses at least partially through the first doping region into the second doping region in case predefined trigger conditions occur. A second contact structure is in contact with the second doping region in a contact area of the second doping region.

Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.

Abstract: A method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is characterized by including at least the following steps in this order: a first step in which a semiconductor chip is bonded onto a circular support substrate; a second step in which the semiconductor chip is sealed with resin; a third step in which the resin covering the pads of the semiconductor chip is removed; a fourth step in which a rewiring layer is formed; and a fifth step in which bumps are formed. The method can provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress.

Abstract: An element electrode is located on a surface of a semiconductor element. A metal film is located on the element electrode and includes an inner region and an outer region located around the inner region. The metal film has an opening that exposes the element electrode between the inner region and the outer region. The element electrode has solder wettability lower than solder wettability of the metal film. An external electrode is solder-bonded to the inner region of the metal film.

Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

Abstract: The disclosure provides an internal heat-dissipation terminal, wherein the terminal comprises at least one cavity in which heat-storage material is arranged. The cavity is located in an area without a device in the terminal. The technical solution of the disclosure can be applied to substantially enhance the heat storage capability of the terminal.

Abstract: A display apparatus is provided. The display apparatus includes: a display panel comprising one or more display devices which generate visible light; a display circuit film portion that is disposed such that the display circuit film portion overlaps the one or more display devices and faces a surface of the display panel, which is opposite to a surface of the display panel, on which the visible rays are realized on a user side, and comprises a base film portion and one or more conductive patterns contacting the base film portion and a first conductive connecting member that is disposed in a first via-area to connect the one or more conductive patterns of the display circuit film portion and the one or more display devices.

Abstract: A wire bonding structure includes a bonding target and a wire with its bond portion bonded to the bonding target. The bond portion has a bottom surface in contact with the bonding target, a pressed surface facing away from the bottom surface in a thickness direction of the bond portion, and a side surface connecting the bottom surface and the pressed surface. The pressed surface includes first and second annular portions connected to each other via a bent portion. The first annular portion is parallel to the bottom surface and positioned on the inner side of the second annular portion as viewed in the thickness direction. The second annular portion becomes more distant from the bottom surface in the thickness direction as extending outward as viewed in the thickness direction, starting from the first bent portion.

Abstract: Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.

Abstract: In one embodiment of the present invention, a test probe assembly for testing packaged integrated circuit (IC) devices includes a plurality of probes, a pad and a PCB/interposer. The plurality of probes is configured to repeatedly maintain reliable electrical contact with a corresponding plurality of DUT contacts when under a compliant force. The pad provides mechanical support and/or electric coupling for the plurality of probes. In turn, the PCB/interposer supports the pad. In some embodiments, the plurality of probes includes a hard core material such as diamond. In other embodiments, the surface of the probes is hardened.

Abstract: A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the wide bandgap semiconductor element with a cooling medium, wherein the cooling system comprises a refrigeration device for lowering a temperature of the cooling medium below an ambient temperature of the power device; wherein the cooling system is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor element is below 100° C.

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.

Abstract: A light emitting device includes a semiconductor light emitting element; a mounting substrate; a support substrate; a joining layer which joins the semiconductor light emitting element and the mounting substrate together, is a sintered body of metal particles, and has a pore; and a joining layer which joins the mounting substrate and the support substrate together, is a sintered body of metal particles, and has a pore, in which a porosity of the joining layer is lower than a porosity of the joining layer.

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Abstract: A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric substrate. A single wire bond can be used to bond the IC to the PCB, and a ground plane can be established for the PCB. To minimize inductance losses at high frequency operation, a ground plane defect can be intentionally established by forming at least one opening in the ground plane. The opening can be rectangular when viewed in top plan, although the number of openings formed and opening geometry can be chosen according to the desired operating frequency of the device. The defect can allow for single wire bonding of the IC to the PCB in a manner which allows for high frequency operation without requiring the integration of additional matching network components on the IC and PCB.

Abstract: A method and structure for a PLCSP (Package Level Chip Scale Package) MEMS package. The method includes providing a MEMS chip having a CMOS substrate and a MEMS cap housing at least a MEMS device disposed upon the CMOS substrate. The MEMS chip is flipped and oriented on a packaging substrate such that the MEMS cap is disposed above a thinner region of the packaging substrate and the CMOS substrate is bonding to the packaging substrate at a thicker region, wherein bonding regions on each of the substrates are coupled. The device is sawed to form a package-level chip scale MEMS package.

Abstract: A bonding structure of a chip and an electronic circuit contains: a chip holder, a chip accommodated in the chip holder, multiple conductive feet electrically connected with the chip, and an electronic circuit. The chip and the multiple conductive feet are covered by a packaging material, and a part of each of the multiple conductive feet exposes outside the packaging material to form an extension. The electronic circuit includes a porous substrate and an electric circuit connected on the porous substrate, wherein the electric circuit is formed from conductive inks which penetrate into the porous substrate, and the extension is inserted through the electric circuit, hence the extension is electrically connected with the electric circuit.

Abstract: A length in a first direction of an element body is smaller than a length in a second direction of the element body and smaller than a length in a third direction of the element body, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first and second direction. A difference between a maximum thickness and a minimum thickness of a first electrode portion is smaller than a difference between a maximum thickness and a minimum thickness of a second electrode portion. A difference between a maximum thickness and a minimum thickness of a third electrode portion is smaller than a difference between a maximum thickness and a minimum thickness of a fourth electrode portion. The maximum thickness of the first electrode portion and the maximum thickness of the third electrode portion are larger than thicknesses of respective outer layer portions.

Abstract: A semiconductor device includes: a semiconductor die having first and second opposite surfaces, a die pad having the first surface of the semiconductor die attached thereon, an electrically conductive ground pad at the second surface of the semiconductor die, a device package coupled with the semiconductor die with the ground pad lying between the semiconductor die and the package, and ground wiring or tracks for the semiconductor die between the second surface of the semiconductor die and the ground pad. A further ground connection may be provided between the ground pad at the second surface of the semiconductor die and the die pad having the semiconductor die attached thereon.

Abstract: A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies.

Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through-hole structure forming at least one conductive pathway through a thickness of the insulating core. A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.

Abstract: An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.

Abstract: A semiconductor device 10 includes: multi-layered substrates 12 each having a circuit board 12c; control terminals 14 whose one end is fixed on the circuit board 12c of each multi-layered substrate 12; a resin case 15 which has openings 20 and is arranged to cover the multi-layered substrates 12, through which openings 20 the other ends of the control terminals 14 extend outwardly; and resin blocks 18 which are each inserted into the openings 20 of the resin case 15 and press-fixes the control terminals 14 against the side walls of the respective openings 20. The control terminals 14 each have a low-rigidity portion 14j at a position that is further interior of the resin case 15 than a position where each control terminal 14 is in contact with the resin block 18 in the respective openings 20 of the resin case 15.

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract: There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.

Abstract: A power electronic module including at least one pair of power electronic components, each pair including a first and a second component, each component including a first face, configured to be supported on a support and a second face configured to be electrically connected to an electrical circuit with a smaller thermal contact area than the contact area between the first face and the support, and a first and a second support. The first component in each pair is supported by the first support and is connected to a second electrical circuit of the second support and the second component in each pair is supported on the second support and is connected to a first electrical circuit of the first support.

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract: According to the invention, a pressure receiving space of a pressure sensor is prevented from being charged. In the pressure sensor, a diaphragm is mounted on a base fixed in a cover to form the pressure receiving space in which oil is sealed. A semiconductor pressure detection device is provided in the pressure receiving space, and adjustment lead pins and an earth-terminal lead pin are connected to terminals of the semiconductor pressure detection device by bonding wires. A wiring substrate is provided with the base of the pressure receiving space interposed and faces the base, and a metal foil is provided such that one or more lead pins of the adjustment lead pins and the earth-terminal lead pin are electrically connected in the wiring substrate. Therefore, the charging of the insulative medium sealed in the pressure receiving space is prevented.

Abstract: A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric layer and a plurality of redistribution circuit layers. The chip has a plurality of connection pads. The dielectric layer is disposed on the chip and defined with a plurality of containers therein. The connection pads are exposed from the containers, respectively. The redistribution circuit layers are disposed within the containers and electrically connected with the connection pads, respectively. Via these arrangements, the bonding surfaces between the redistribution circuit layers and the dielectric layer can be increased.

Abstract: An optoelectronic semiconductor component includes a carrier having a carrier top side and an opposing carrier underside, wherein the carrier top sides each have a larger area than the associated carrier undersides, the carrier parts fixedly connect to one another via at least one potting body and the potting body together with the carrier parts represents a bearing component of the semiconductor component so that all carrier undersides end flush with the potting body, the light-emitting semiconductor chips electrically connect in series, the metal layer on the carrier top side is structured into conductor tracks and into electrical connection surfaces, and the electrical connection surfaces on the carrier top side are electrically insulated from the associated carrier underside so that the carrier underside of the carrier part the semiconductor chips are arranged on is potential-free and is completely covered with the metal layer.

Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

Abstract: A sensor has an electronic chip and a sensor chip which are arranged within a functional volume which is at the most 4-5 mm long, a maximum 2-3 mm wide, and the maximum height is 0.5-0.8 mm, thereby potentially providing a compact sensor.

Abstract: A semiconductor device includes: a circuit pattern, at least one or more wires joined thereto, an electrode terminal joining thereto, and a semiconductor element. The electrode terminal includes a horizontally extending portion extending along a main surface and connected to the wire, and a bent portion at which an extending direction of the electrode terminal is changed relative to the horizontally extending portion. Each of the wires has joint portions at which each of the wires and the circuit pattern are joined to each other. In a plan view, the joint portions are located on an outside of a portion where each of the wires and the electrode terminal overlap each other.

Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.

Abstract: In the semiconductor module according to the present invention, a conducting member which is used to electrically connect a semiconductor element arranged on a substrate or a bus bar with another electronic component is provided with a structure having flexibility capable of, in a junction with the semiconductor element, reducing the thermal stress due to difference in a coefficient of linear expansion between the conducting member and the semiconductor element, and absorbing dimensional error in objects to be connected. Therefore, the semiconductor module achieves both increased current capacity of the semiconductor device and improved reliability of the semiconductor module.

Abstract: An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.

Abstract: Buffer structures are provided that can be used to reduce a strain in a conformable electronic system that includes compliant components in electrical communication with more rigid device components. The buffer structures are disposed on, or at least partially embedded in, the conformable electronic system such that the buffer structures overlap with at least a portion of a junction region between a compliant component and a more rigid device component. The buffer structure can have a higher value of Young's modulus than an encapsulant of the conformable electronic system.

Abstract: A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface. The top surface defines a first groove. The first groove is substantially ring-shaped. The glue layer is arranged in the top surface and surrounds the first groove. A plurality of glass-frits is distributed in the glue layer. A thickness of the main body is approximately in a range from 0.5 millimeters to 0.8 millimeters. The glue layer is directly attached the top surface.

Abstract: A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.

Abstract: Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.