Abstract: Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover.

Abstract: A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part.

Abstract: By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.

Abstract: A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.

Abstract: In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Abstract: The thermal interface material including a thermally conductive metal a thermally conductive metal having a first surface and an opposing second surface, a diffusion barrier plate coupled to the first surface of the thermally conductive metal and the second surface of the thermally conductive metal, and a thermal resistance reducing layer coupled to the diffusion barrier plate.

Abstract: A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer.

Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.

Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.

Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side.

Abstract: A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials.

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated includes an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract: A method for producing a plurality of optoelectronic devices is specified, comprising the following steps: providing a connection carrier assemblage having a plurality of device regions, wherein at least one electrical connection region is provided in each of the device regions, providing a semiconductor body carrier, on which a plurality of separate semiconductor bodies connected to the semiconductor body carrier are arranged, wherein the semiconductor bodies each have a semiconductor layer sequence having an active region, arranging the connection carrier assemblage and the semiconductor body carrier relative to one another in such a way that the semiconductor bodies face the device regions, mechanically connecting a plurality of semiconductor bodies to the connection carrier assemblage in a mounting region of a device region assigned to the respective semiconductor body, electrically conductively connecting the respective semiconductor body to the connection region of the device region assigned to the semi

Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.

Abstract: The electronic module comprises a dielectric 1031 substrate having a first surface and a second surface and an installation cavity extending through the dielectric substrate and having a perimetrical side wall. The electronic module further comprises a first wiring layer 1032 on the first surface, a second wiring layer 1033 on the second surface, and a feed through conductor 1034 on the perimetrical side wall and electrically connecting at least one conductor in the first wiring layer to at least one conductor in the second wiring layer. There is also at least one IC inside the installation cavity. The electronic module further comprises a first insulating layer 1035 on the second wiring layer, a second insulating layer 1036 on the first wiring layer, and a third wiring layer 1037 on the first insulating layer. First microvias 1038 inside the first insulating layer make electrical connections between the second wiring layer and the third wiring layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first lead adjacent and staggered to a second lead, the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion; connecting an integrated circuit device with the first internal connection portion and with the second internal connection portion; forming an encapsulation over the integrated circuit device with the first lead and the second lead exposed; and forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.

Abstract: A semiconductor device includes an electronic component having an electrode pad provided on an electrode pad forming face, and a rear face positioned on a side opposite to the electrode pad forming face; an insulating member provided to seal a periphery of the electronic component, and having a first face exposing the electrode pad forming face of the electronic component and a second face exposing the rear face of the electronic component; a multi-layer wiring structure body provided to cover the first face of the insulating member, the electrode pad, and the electrode pad forming face, and including a plurality of insulating layers laminated on each other, and a wiring pattern; and a piercing electrode piercing the insulating member from the first face to the second face. The wiring pattern is directly connected to the electrode pad and the piercing electrode.

Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.

Abstract: Disclosed is a semiconductor device wherein the adhesion of resin to a substrate is improved at a low cost. A semiconductor element and one or two substrates opposing one or both of the surfaces of the semiconductor element are sealed by a resin, a resin bonding coat which is formed by spraying a metal powder by a cold spray method is formed on one or both of the substrates, and recess portions which are widened from a film surface in a depth direction are formed on the resin bonding coat.

Abstract: A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

Abstract: A leadframe and semiconductor device package with multiple semiconductor device die paddles for accepting multiple semiconductor devices is disclosed, wherein the leadframe increases semiconductor device density and reduces cost by integrating the multiple dies into a semiconductor device package with a relatively small footprint. The leadframe may include at least one full-metal die paddle and at least one reduced-metal die paddle, which may form a unified or hybrid die paddle. The leadframe may enable electrical coupling of multiple semiconductor devices to a common leadfinger and/or die paddle, where internal leadfingers coupled to the common leadfingers and/or die paddles may receive the electrical coupling means from the semiconductor device. Surfaces of one or more die paddles of the leadframe may be exposed to the outside of the semiconductor device package to enable electrical testing of and/or provide heat dissipation from one or more of the semiconductor devices attached to the leadframe.

Abstract: An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's.

Abstract: A wiring process between the provided power semiconductor module and the external circuit is simple. In the power semiconductor module, a power semiconductor element and a cylindrical conductor are joined to one surface of a lead frame. An opening of the cylindrical conductor is exposed at a surface of transfer molding resin. Sealing with the transfer molding resin is performed such that terminal portions of the lead frame protrude from peripheral side portions of the transfer molding resin. The cylindrical conductor is conductive with a control circuit. The terminal portions of the lead frame are each conductive with a main circuit.

Abstract: A system for dissipating heat from a semiconductor board includes a first substrate including an opening formed therein, a second substrate attached to a surface of the first substrate, and a microchip positioned in the opening and bumped to the second substrate. The system further includes a heat sink directly adhered to the microchip. A method of manufacturing a heat dissipating semiconductor board includes forming an opening in a first substrate and positioning a microchip in the opening. The method further includes directly adhering the microchip to a heat sink, bonding the microchip to a second substrate and boding a surface of the first substrate to the second substrate.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.

Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.

Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.

Abstract: Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with conductive material to form conductive contacts.

Abstract: Chip carriers are provided. The chip carrier includes a carrier body having a cavity therein and at least one conductive through silicon via (TSV) penetrating the carrier body under the cavity. The cavity includes an uneven sidewall surface profile. The at least one conductive through silicon via (TSV) is exposed at a bottom surface of the carrier body opposite to the cavity. Related methods are also provided.

Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.

Abstract: Disclosed herein are various embodiments of widebody coil isolators containing multiple coil transducers, where integrated circuits are not stacked vertically over the coil transducers. The disclosed coil isolators provide high voltage isolation and high voltage breakdown performance characteristics in small packages that provide a high degree of functionality at a low price.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface at an opposite side thereof. The first surface has an active layer with a light-receiving part. The semiconductor device also includes an adhesive layer provided to surround the light-receiving part on the first surface of the semiconductor substrate; a light-transmissive protective member disposed above the light-receiving part of the semiconductor substrate with a predetermined gap and adhered via the adhesive layer; and plural external connection terminals arranged in a predetermined array on the second surface of the semiconductor substrate are included. Each center point of the external connection terminals forming two facing edges is positioned inside of an area of the adhesive layer projected on the second surface among the outermost external connection terminals.

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; processing a top edge of the support structure along an outermost periphery thereof, to include a recess for preventing mold bleed, the recess surrounded by the lead finger system; and encapsulating the recess and the electrical interconnect system with an encapsulation material to interlock the encapsulation material.

Abstract: Provided is a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. The semiconductor device of the present invention includes: a package substrate; a semiconductor chip mounted on the package substrate; a first land formed in a first principal surface of the package substrate; a second land formed in a second principal surface of the package substrate; first connection terminals connected to the second land and having the connection thereto not allowed to be checked with the semiconductor chip; a connection interconnection for connecting the first land and the second land; a second connection terminal formed in the second principal surface of the package substrate; and a branch interconnection for connecting the connection interconnection and the second connection terminal.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first terminal; connecting an integrated circuit to the first terminal; forming a second terminal connected over the first terminal and the integrated circuit by a vertical conductive post integral with the first terminal or the second terminal; and encapsulating the integrated circuit and the vertical conductive post leaving portions of the first terminal and the second terminal exposed.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: A semiconductor device includes a semiconductor integrated circuit device (1). In the semiconductor integrated circuit device (1), a semiconductor integrated circuit (5) is formed on a center of the surface of a semiconductor substrate (3), and a plurality of electrode terminals (71, 73, . . . ) are provided on the surface of the semiconductor substrate (3). A protection film (9) is provided on the surface of the semiconductor substrate (3) such that the surfaces of the electrode terminals (71, 73) are exposed. The electrode terminals (71, 73, . . . ) include an electrode terminal (73) having a thin portion (74). The surface of the thin portion (74) is located below the surfaces of the electrode terminals except for the electrode terminal (73) having the thin portion (74) among the electrode terminals (71, 73, . . . ).