Abstract: A lead pin for a package substrate includes a coupling pin, a head portion, and a flowing prevention portion. The coupling pin is to be inserted into a hole which is formed in an external substrate. The head portion is formed at one end of the coupling pin. The flowing prevention portion is formed on the top surface of the head portion and prevents a solder paste from flowing toward the coupling pin on the top surface of the head portion when the head portion is mounted on the package substrate.

Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Abstract: A pressure loss section H1 (H2) extends from a position corresponding to a corner of a resin package, and S1 is the minimum value of the opening area of the pressure loss section H1 (H2) perpendicular to the direction of resin flow (X axis) in the pressure loss section H1 (H2) during resin molding, while S2 is the average value of the opening areas of excess resin reservoirs H3 to H5 perpendicular to the direction of resin flow (Y axis) within excess resin reservoir H3 to H5 during molding. In this lead frame, S1<S2 is satisfied.

Abstract: A light emitting diode (LED) package includes a substrate, a first LED chip and a second LED chip. The substrate includes first to fourth electrodes, and an interconnection electrode. A mounting area is defined at center of a top surface of the substrate. The first to fourth electrodes are respectively in four corners of the substrate out of the mounting area. The first interconnection electrode is embedded in the substrate to electrically connect the first and the third electrodes. The first LED chip and the second LED chip are arranged in the mounting area. Each LED chip includes an anode pad and a cathode pad. The first to fourth electrodes are respectively connected to the four pads of the first and the second LED chips via a plurality of metal wires, and no metal wire connection is formed between the first and the second LED chips.

Abstract: A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.

Abstract: A package has a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, a chemical activator in the interconnect area, and an adhesive responsive to the chemical activator in the interconnect area. A package has a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, a chemical activator on one of either the pad chip or the spring chip, and an adhesive responsive to the chemical activator on the other of either the pad chip or the spring chip.

Abstract: An electronic-component-housing package comprises a container including a rectangular mount on which an electronic component is to be mounted and a sidewall surrounding the mount. The electronic-component-housing package comprises a lead terminal extending from an inside of a space enclosed by the sidewall to an outside of the space. A tip part of the lead terminal is extending along one side of the mount.

Abstract: An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is over the top surface of the conductive pillar. The cap layer extends along the edge sidewalls of the conductive pillar for a length. A solder material is over a top surface of the cap layer.

Abstract: An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

Abstract: A semiconductor assembly with an integrated circuit (IC) and a companion device. An exemplary semiconductor assembly includes a printed circuit board (PCB) and first and second ICs. The PCB has first contacts on a top surface and second contacts on a bottom surface. The first contacts are vertically aligned with the second contacts and are electrically coupled by vias in the PCB. The first IC has first terminals respectively coupled to the first contacts of the PCB, the first terminals including first input/output (IO) terminals. The second IC includes at least one die, and second terminals coupled to at least a portion of the second contacts of the PCB. The second terminals include second IO terminals of the companion die, and are respectively coupled to those of the second contacts that are vertically aligned with those of the first contacts respectively coupled to the first IO terminals.

Abstract: Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.

Abstract: A power module includes: a sealing body including a semiconductor element having a plurality of electrode surfaces, a first conductor plate connected to one electrode surface of the semiconductor element via solder, and a sealing material for sealing the semiconductor element and the first conductor plate, the sealing body having at least a first surface and a second surface on the opposite side of the first surface; and a case for housing the sealing body. The case is configured by a first heat radiation plate opposed to the first surface of the sealing body, a second heat radiation plate opposed to the second surface of the sealing body, and an intermediate member that connects the first heat radiation plate and the second heat radiation plate. The intermediate member has a first thin section having thickness smaller than the thickness of the first heat radiation plate, more easily elastically deformed than the first heat radiation plate, and formed to surround the first heat radiation plate.

Abstract: A method of manufacturing a semiconductor device is disclosed. One embodiment includes placing multiple semiconductor chips onto a carrier, each of the semiconductor chips having a first face and a second face opposite to the first face. An encapsulation material is applied over the multiple semiconductor chips and the carrier to form an encapsulating body having a first face facing the carrier and a second face opposite to the first face. A redistribution layer is applied over the multiple semiconductor chips and the first face of the encapsulating body. An array of external contact elements are applied to the second face of the encapsulating body.

Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.

Abstract: A semiconductor device includes a lead frame 1 having a first lead 6, a second lead 7 and a third lead 8. A power transistor 2 is placed on the first lead 6, and the power transistor 2 is connected to the first lead 6. The power transistor 2 has a drain electrode on one side opposite to a first lead 6 side, and this drain electrode is connected to a Cu chip 3 on the power transistor 2. The Cu chip 3 is connected to the second lead 7 via Al wires 4. As a result, during wire bonding of the Al wires 4, it becomes possible to absorb shocks due to wire bonding by the Cu chip 3, or disperse pressure due to wire bonding by the Cu chip 3, or diffuse heat due to wire bonding by the Cu chip 3.

Abstract: A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader.

Abstract: Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.

Abstract: This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, fabricating a glass package includes joining a cover glass panel to a glass substrate panel, and singulating the joined panels to form individual glass packages, each including one or more encapsulated devices and one or more signal transmission pathways. In another aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass.

Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Abstract: A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.

Abstract: Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter is larger than that of a contact portion. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Diameter of the contact portion is substantially the same as diameter of an under bump metal at the semiconductor chip side, when mechanical stress is applied, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.

Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.

Abstract: A source driver of a film package type including a film substrate; a semiconductor chip on a surface of the film substrate, the semiconductor chip having a plurality of terminals, the plurality of terminals including input terminals, output terminals, and third terminals; an input terminal wiring region for receiving first wiring lines which are connected to the input terminals; an output terminal wiring region for receiving second wiring lines which are connected to the output terminals; sprocket portions at opposite ends of the film substrate; and a heat conducting patterns for connecting the third terminals. This makes it possible to provide a source driver, a method for manufacturing the source driver, and a liquid crystal module, each of which can increase a heat dissipation amount.

Abstract: A multiple element emitter package is disclosed for increasing color fidelity and heat dissipation, improving current control, increasing rigidity of the package assembly. In one embodiment, the package comprises a surface-mount device a casing with a cavity extending into the interior of the casing from a first main surface is provided. A lead frame is at least partially encased by the casing, the lead frame comprising a plurality of electrically conductive parts carrying a linear array of light emitting devices (LEDs). Electrically conductive parts, separate from parts carrying the LEDs have a connection pad, wherein the LEDs are electrically coupled to a connection pad, such as by a wire bond. This lead frame arrangement allows for a respective electrical signal can be applied to each of the LEDs. The emitter package may be substantially waterproof, and an array of the emitter packages may be used in an LED display such as an indoor and/or outdoor LED screen.

Abstract: Some embodiments provide surface mount devices that include a first electrode comprising a chip carrier part, a second electrode disposed proximate to the chip carrier part, and a casing encasing a portion of the first and second electrodes. The first electrode can extend from the chip carrier part toward a perimeter of the casing, and the second electrode can extend away from the chip carrier part and projects outside of the casing. In extending away from the chip carrier part the first electrode divides into a plurality of leads separated by an aperture that join into a single first joined lead portion with a first width before projecting outside of the casing and maintains the first width outside of the casing. The second electrode can attain a second width prior to projecting outside of the casing and maintains the second width outside the casing.

Abstract: In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion.

Abstract: Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.

Abstract: An electronic component is provided between at least two wiring boards. An electrode of the electronic component is electrically connected to at least one of the wiring boards. Also, the wiring boards and are electrically connected to each other. Additionally, the gap between the wiring boards and is sealed with a resin. The electronic component built-in substrate is featured in that a bonding pad formed on one of the wiring boards and is electrically connected to an electrode of the electronic component by a bonding wire, and that at least a connection portion between the electrode of the electronic component and the bonding wire is coated with a protection material.

Abstract: The present invention discloses a semiconductor device package and the method for the same. The method includes preparing a first substrate and a second substrate; opening a die opening window through the second substrate by using laser or punching; preparing an adhesion material; attaching the first substrate to the second substrate by the adhesion material; aligning a die by using the aligning mark of the die metal pad and attaching the die onto the die metal pad with force by the adhesion material; forming a first dielectric layer on top surfaces of the second substrate and the die and pushing the first dielectric layer into gap between the side wall of the die and the side wall of the die opening window under vacuum condition; opening a plurality of via openings in the first dielectric layer; and forming a redistribution layer in the plurality of via openings and on the first dielectric layer.

Abstract: A wiring substrate includes a wiring layer, an insulating layer formed on the wiring layer, a connection pad formed on the insulating layer, and a via conductor formed to penetrate the insulating layer, and connecting the wiring layer and the connection pad, wherein the wiring layer located under the connection pad is formed to have via receiving electrode portion whose area is smaller than an area of the connection pad, and a wiring portion separated from the via receiving electrode portion, in an area corresponding to the connection pad, and the via receiving electrode portion is connected to the connection pad via the via conductor.

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract: A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

Abstract: A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.

Abstract: A chip package device includes a substrate having a chip bonding area and at least one contact pad, a chip having an active surface and an inactive surface, at least one wire, an adhesive layer, a heat dissipation element, and an encapsulation. The chip is disposed on the chip bonding area with its inactive surface facing the substrate. The chip includes at least one bonding pad disposed on the active surface. The wire correspondingly connects the at least one bonding pad and the at least one contact pad. The adhesive layer covers the active surface of the chip and encloses a portion of the wire extending over the bonding pad. The heat dissipation element is attached to the adhesive layer and covers the chip. The encapsulation partially encloses the periphery of the assembly including the chip, the adhesive and the heat dissipation element, and has an indented opening to expose the surface of the heat dissipation element.

Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.

Abstract: In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

Abstract: A circuit component comprising a substrate, and a conductive layer over the substrate, wherein the conductive layer comprises a first portion between a first opening in the conductive layer and a second opening in the conductive layer, wherein the first and second openings are enclosed by the conductive layer, wherein a void is over the substrate and under the conductive layer, wherein the first portion and the first and second openings are over the void.

Abstract: In at least one aspect, a semiconductor light emitting device may include a first lead, a second lead provided being apart from the first lead, a semiconductor light emitting element provided on the first lead, a wiring electrically connecting the semiconductor light emitting element and the second lead, a first resin being optically transparent to light from the semiconductor light emitting element, the first resin covering the semiconductor light emitting element, and a second resin provided on the first resin, the first lead and the second lead, and being optically transparent to light from the semiconductor light emitting element, wherein a part of the first lead which is covered with the second resin is symmetric with respect to a vertical line passing through the semiconductor light emitting element in a cross-sectional view cut along a plane, the plane passing the semiconductor light emitting element and being parallel with a direction to which the first lead is extended.

Abstract: The present disclosure provides an embodiment of a micro-electro-mechanical system (MEMS) structure, the MEMS structure comprising a MEMS substrate; a first and second conductive plugs of a semiconductor material disposed on the MEMS substrate, wherein the first conductive plug is configured for electrical interconnection and the second conductive plug is configured as an anti-stiction bump; a MEMS device configured on the MEMS substrate and electrically coupled with the first conductive plug; and a cap substrate bonded to the MEMS substrate such that the MEMS device is enclosed therebetween.

Abstract: A semiconductor device includes: a first semiconductor device including an interconnect substrate having a cavity structure and a semiconductor element mounted on a bottom part of the cavity structure; and a second semiconductor device provided on and connected to the first semiconductor device via connection terminals. A sealing material is provided between the first semiconductor device and the second semiconductor device. A sloped portion is formed, at a corner portion at which the bottom part and a side wall of the cavity structure in the first semiconductor device meets, to be sloped toward a center part of the cavity structure and have a tapered shape which becomes continuously wider in the direction from an upper part to a lower part.

Abstract: According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.

Abstract: A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Abstract: An integrated circuit package that comprises a lead frame 105, an integrated circuit located on the lead frame and a shunt resistor coupled to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.

Abstract: A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.

Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.

Abstract: A light emitting diode (LED) module includes a lead frame having a number (N) of conducting arms spaced apart from each other, where N?3, and at least one LED die mounted on one of any two neighbor conducting arms. Any two neighbor conducting arms are electrically coupled each other.

Abstract: An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.