Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: A semiconductor device in accordance with an embodiment comprises a semiconductor chip; a die pad having a chip mount surface for mounting the semiconductor chip; first leads electrically connected to the semiconductor chip; a thermosetting resin part for securing end parts of the first leads to the die pad; and a thermoplastic resin part for sealing the semiconductor chip, the die pad, and the thermosetting resin part.

Abstract: A semiconductor device in which a flip chip is mounted which can change a potential of a specific terminal without changing a design of a package external. The semiconductor device includes an IC chip having a bump for an external terminal, and a package in which the IC chip is mounted. The package includes an inner lead portion that supplies a first signal or a second signal to the external terminal. The inner lead portion has a pattern of an inner lead that can change a signal to be supplied to the external terminal to the first signal or the second signal according to a position at which the IC chip is mounted.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts.

Abstract: A contactless communication medium which can prevent invasion of static electricity and has an outer surface which can satisfy requirements on the flatness thereof. The contactless communication medium has a sealing member including an insulating layer and a conductive layer provided in a stacked manner and having a shape covering an IC module is located such that the insulating layer is on the IC module side. Owing to this, static electricity coming from outside is diffused by the conductive layer and blocked by the insulating layer. Thus, adverse influence of the static electricity on the IC module is prevented. The contactless communication medium can also satisfy the requirements on the flatness of an outer surface thereof.

Abstract: A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip. The semiconductor device also includes a second semiconductor package stacked on the first semiconductor package. The second semiconductor package has at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip. At least one signal connection member is disposed in the first sealing member of the first semiconductor package. The at least one signal connection member electrically connects the at least one first semiconductor chip with the leads of the at least one second semiconductor chip.

Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.

Abstract: A semiconductor device has a connection structure in which a power semiconductor chip is mounted on an insulating substrate having conductor patterns bonded to front and rear surfaces thereof and the insulating substrate is bonded to a heat-dissipating base member to dissipate heat generated from the power semiconductor chip to outside. The conductor pattern bonded to the heat-dissipating base member is formed such that a thickness of a circumferential portion of a bonding surface of the conductor pattern bonded to the insulating substrate is less than that of a center of the bonding portion.

Abstract: A microelectronic assembly includes a dielectric element that has oppositely-facing first and second surfaces and first and second apertures extending between the surfaces. The dielectric element further includes conductive elements. First and second microelectronic elements are stacked one on top of the another. The second microelectronic element has a plurality of contacts at a surface, which is spaced from the first surface of the dielectric element. Leads extend from contacts of the first and second microelectronic elements through respective apertures to at least some of the conductive elements. A heat spreader is thermally coupled to at least one of the first microelectronic element or the second microelectronic element.

Abstract: In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom body, a lead top body, and a lead top conductive layer directly on the lead top body, the lead top conductive layer having a top protrusion and a top non-vertical portion, the lead bottom body having a horizontally contiguous structure; connecting an integrated circuit to the top protrusion; and forming an encapsulation covering the integrated circuit and exposing a top non-vertical upper side of the top non-vertical portion.

Abstract: Methods, systems, and apparatuses for wafer-level package-on-package structures are provided herein. A wafer-level integrated circuit package that includes at least one die is formed. The wafer-level integrated circuit package includes redistribution interconnects that redistribute terminals of the die over an area that is larger than an active-surface of the die. Electrically conductive paths are formed from the redistribution interconnects at a first surface of the wafer-level integrated circuit package to electrically conductive features at a second surface of the wafer-level integrated circuit package. A second integrated circuit package may be mounted to the second surface of the wafer-level integrated circuit package to form a package-on-package structure. Electrical mounting members of the second package may be coupled to the electrically conductive features at the second surface of the wafer-level integrated circuit package to provide electrical connectivity between the packages.

Abstract: A plastic package (100) in which a semiconductor chip (101) is adhesively (102) attached to a metal stripe (110a) having an agglomerate structure, and electrically connected to bondable and solderable metal stripes (120) having particulate structures; metal stripes (120) are touching metal stripes (110b) of agglomerate structure to form vertical stacks (150); coats of solder (140) are welded to the agglomerate metal stripes (100a and 110b).

Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.

Abstract: Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

Abstract: A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements.

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die attach pad integrally connected to a connector portion and a lead; attaching an integrated circuit die to the die attach pad; connecting an internal interconnect to the integrated circuit die and the lead; forming an encapsulation over the integrated circuit die; removing the connector portion to separate the die attach pad and the lead; and forming an isolation cover between the die attach pad and the lead.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: A semiconductor device includes a semiconductor die. The semiconductor die includes a first bond pad having a plurality of connection points, the first bond pad arranged on a first portion of the semiconductor die, wherein the first portion corresponds to an outer periphery of the semiconductor die, and a second bond pad and a third bond pad arranged within a second portion of the semiconductor die, wherein the second portion is within the outer periphery of the semiconductor die. A lead external to the semiconductor die is configured to provide a voltage potential to the semiconductor die. A first lead wire is connected between the lead and a first connection point. A second lead wire is connected between the second bond pad and a second connection point. A third lead wire is connected between the third bond pad and a third connection point.

Abstract: A package and integrated circuit assembly is configured to perform signal conditioning on a signal. The assembly includes a line card having line card contacts that correspond to conductors in the line card connector. Two or more integrated circuits are configured to perform signal conditioning on the signal and the two or more integrated circuits are configured within a package into at least a first row and a second row on the package. The package includes a grid array of bonding pads to electrically connect to the two or more integrated circuits through bond wires or down bonds such that the structure of the grid array corresponds in physical arrangement or bond pad pitch to the line card contacts. This assembly also includes an electrical connection from the two or more integrated circuits to the line card through the package.

Abstract: In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device and a package substrate core having an upper and a lower surface. At least one pair of metal layers coats the upper and lower surfaces of the package substrate core. One pair of solder mask layers coats the outer metal layers of the at least one pair of metal layers. A plurality of vias is formed across the package substrate core and the at least one pair of metal layers. Advantageously, the plurality of vias is substantially distributed according to a homogeneous pattern in an area that is to be covered by the damage-sensitive device. A method for the production of such semiconductor package substrate is also described.

Abstract: An LED includes a base, a first lead and a second lead mounted to the base, a light emitting chip electrically connected to the first lead and the second lead, and an encapsulant sealing the chip. The first lead and the second lead each include a first beam and a second beam connected to each other. Each of the first beam and the second beam has two opposite ends protruding beyond two opposite lateral faces of the base, respectively, for electrically connecting with a circuit board.

Abstract: There is disclosed an integrated circuit (IC) package or semiconductor package including integrated spark or arc gaps which are uniquely configured to reduce the susceptibility of the package to being damaged from an electrostatic discharge (ESD) event. In an exemplary embodiment, each arc gap is collectively defined by an arc gap extension integrally connected to and protruding from the die pad of the package, and a corresponding lead thereof.

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract: A carrier body for a semiconductor component, in particular for an optoelectronic semiconductor component, is specified. Said carrier body has a connecting layer and a conductor layer, which are connected to one another via main areas facing one another. The connecting layer, the conductor layer or both the connecting layer and the conductor layer has/have at least one thinned region in which the layer thickness of said layer(s) is less than the maximum layer thickness of said layer(s). The connecting layer is either completely electrically conductive and electrically insulated at least from parts of the conductor layer or it is electrically insulating at least in parts. Furthermore, a semiconductor component comprising the electrical connection conductor and also a method for producing the carrier body are specified.

Abstract: A semiconductor device has a flipchip type semiconductor die with contact pads and substrate with contact pads. A flux material is deposited over the contact pads of the semiconductor die and contact pads of the substrate. A solder tape formed as a continuous body of solder material with a plurality of recesses is disposed between the contact pads of the semiconductor die and substrate. The solder tape is brought to a liquidus state to separate a portion of the solder tape outside a footprint of the contact pads of the semiconductor die and substrate under surface tension and coalesce the solder material as an electrical interconnect substantially within the footprint of the contact pads of the semiconductor die and substrate. The contact pads on the semiconductor die and substrate can be formed with an extension or recess to increase surface area of the contact pads.

Abstract: A semiconductor unit includes a base having a surface where a first insulation layer is disposed, a second insulation layer spaced apart from the first insulation layer to form a region therebetween and disposed parallel to the surface of the base where the first insulation layer is disposed, a single conductive layer disposed across the first insulation layer and the second insulation layer, and a semiconductor device bonded to the conductive layer.

Abstract: A vertical mount pre-molded type package for use with a MEMS sensor may be formed with a low moisture permeable molding material that surrounds a portion of the leadframes and forms a cavity in which one or multiple dies may be held. The package includes structures to reduce package vibration, reduce die stress, increase vertical mount stability, and improve solder joint reliability. The vertical mount package includes a first leadframe having first leads and molding material substantially surrounding at least a portion of the first leads. The molding material forms a cavity for holding the MEMS sensor and forms a package mounting plane for mounting the package on a base. The cavity has a die mounting plane that is substantially non-parallel to the package mounting plane. The first leads are configured to provide electrical contacts within the cavity and to provide electrical contacts to the base.

Abstract: A semiconductor package includes a chip, a carrier, a bonding wire and a molding compound. The chip includes a pad. The carrier includes a finger and has an upper surface and a lower surface opposite to the upper surface, wherein the upper surface supports the chip. The bonding wire is extended from the finger to the pad for electrically connecting the chip to the carrier, wherein the bonding wire defines a projection portion on the upper surface of the carrier, a straight line is defined to pass through the finger and pad, there is a predetermined angle between the tangent line of the projection portion at the finger and the straight line. The molding compound seals the chip and the bonding wire, and covers the carrier.

Abstract: In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

Abstract: Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.

Abstract: A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects.

Abstract: A semiconductor device of the invention includes a first wiring layer including a signal wiring line formed therein, and a second wiring layer stacked on the first wiring layer and including a power-supply plane and/or ground plane formed therein, the power-supply plane or the ground plane is not formed at least within a part of the region of the second wiring layer facing the signal wiring line of the first wiring layer.

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Abstract: An electronic device includes an electronic component, a joining member to be mechanically joined with the electronic component, and a metal conductor located between the electronic component and the joining member to mechanically join the electronic component and the joining member. The metal conductor is made of porous noble metal to have pores, and includes an end surface without being covered by the electronic component and the joining member. Furthermore, a reinforcing resin is impregnated from the end surface of the metal conductor to the pores inside of the metal conductor, so as to mechanically reinforce the metal conductor.

Abstract: A semiconductor apparatus comprising an integrated semiconductor circuit device having pluralities of electrode pads, pluralities of first external terminals connected to the electrode pads of the integrated semiconductor circuit device, an inductor disposed in a region surrounded by the first external terminals, and a resin portion sealing them, the integrated semiconductor circuit device being arranged on an upper surface of the inductor, and the inductor being exposed from a lower surface of the resin portion together with the first external terminals.

Abstract: A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area.

Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.