Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
  • Patent number: 9679937
    Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: June 13, 2017
    Assignee: Sony Corporation
    Inventor: Atsushi Okuyama
  • Patent number: 9679810
    Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Shishir K. Ray, Andrew H. Simon, Oleg Gluschenkov, Siddarth A. Krishnan, Michael P. Chudzik
  • Patent number: 9680476
    Abstract: A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: June 13, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda
  • Patent number: 9673087
    Abstract: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.
    Type: Grant
    Filed: September 6, 2015
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Satya V. Nitta, Shom Ponoth
  • Patent number: 9666534
    Abstract: The present disclosure provides an interconnect structure, including a low k dielectric layer with an air gap region and a non-air gap region. A first conductive line is positioned in the air gap region, and a second conductive line is positioned in the non-air gap region of the low k dielectric layer. A height of the first conductive line is different from a height of the second conductive line. The present disclosure also provides a method for manufacturing a semiconductor interconnect structure, including forming a photoresist layer over a hard mask layer with openings exposing a low k dielectric layer; treating the low k dielectric layer to be more hydrophilic through the openings of the hard mask layer; and removing the treated low k dielectric region to form an air gap in the air gap region.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chih-Yuan Ting
  • Patent number: 9666791
    Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Ruilong Xie, Xiuyu Cai, Seowoo Nam, Hyun-Jin Cho
  • Patent number: 9659991
    Abstract: A back-side illumination image capturing apparatus includes a semiconductor substrate having a first surface for receiving incident light and a second surface located on the opposite side as the first surface, and including a photoelectric conversion portion, and a gate electrode disposed above the second surface. The apparatus further includes a first insulating layer disposed above the second surface of the semiconductor substrate, an interlayer insulation film disposed on the first insulating layer, a contact plug connected to the gate electrode, and a light-cutting portion for cutting light, of the incident light, that has passed through the photoelectric conversion portion. The light-cutting portion passes through at least part of the interlayer insulation film. The first insulating layer is located between the light-cutting portion and the semiconductor substrate.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 23, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Patent number: 9659865
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 23, 2017
    Assignee: Sony Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 9659841
    Abstract: A method of producing a semiconductor device, comprising the steps of forming a through hole in a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a first conductive layer disposed on the second main surface so that the through hole passes through the semiconductor substrate from the first main surface to the second main surface; forming an insulation film to extend from a bottom portion of the through hole to the first main surface through a side surface of the through hole; coating an organic member on the insulation film on the side surface of the through hole and the first main surface; removing an air bubble in the organic member and between the organic member and the insulation film; and forming a first opening portion in the organic member.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: May 23, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akihiko Nomura
  • Patent number: 9653333
    Abstract: A method of manufacturing a light-emitting device comprises the steps of: providing a semiconductor light-emitting stack having a first connecting surface and a first alignment pattern; providing a substrate having a second connecting surface and a second alignment pattern; detecting the position of the first alignment pattern and the position of the second alignment pattern; and moving at least one of the substrate and the semiconductor light-emitting stack to make the first alignment pattern be aligned with the second alignment pattern.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 16, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Chia-Liang Hsu, Yi-Ming Chen, Hsin-Chih Chiu
  • Patent number: 9647662
    Abstract: A superconducting system is provided that includes a coplanar superconducting circuit. The coplanar superconducting circuit includes a first ground plane region, a second ground plane region electrically isolated from the first ground plane region by portions of the coplanar superconducting circuit, and a tunable coupler having a first port and a second port. The tunable coupler comprises a variable inductance coupling element coupled between the first port and the second port, a first termination inductor having a first end coupled between a first end of the variable inductance element and a second end coupled to the first ground plane region, and a second termination inductor having a first end coupled between a second end of the variable inductance element and a second end coupled to the second ground plane region.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 9, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Mohamed O. Abutaleb, Anthony Joseph Przybysz, Joel D. Strand, Ofer Naaman
  • Patent number: 9646881
    Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Gregory M. Fritz, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9640547
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: May 2, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 9640483
    Abstract: A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John Hongguang Zhang
  • Patent number: 9640435
    Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yuan Ting, Chung-Wen Wu
  • Patent number: 9640396
    Abstract: Novel double- and triple-patterning methods are provided. The methods involve applying a shrinkable composition to a patterned template structure (e.g., a structure having lines) and heating the composition. The shrinkable composition is selected to possess properties that will cause it to shrink during heating, thus forming a conformal layer over the patterned template structure. The layer is then etched to leave behind pre-spacer structures, which comprise the features from the pattern with remnants of the shrinkable composition adjacent the feature sidewalls. The features are removed, leaving behind a doubled pattern. In an alternative embodiment, an extra etch step can be carried out prior to formation of the features on the template structure, thus allowing the pattern to be tripled rather than doubled.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: May 2, 2017
    Assignee: Brewer Science Inc.
    Inventors: Qin Lin, Rama Puligadda, James Claypool, Douglas J. Guerrero, Brian Smith
  • Patent number: 9633964
    Abstract: A wiring substrate includes a connection pad formed in the outermost wiring layer, a dummy pad formed in the outermost wiring layer, and a dummy wiring portion formed in the outermost wiring layer, the dummy wiring portion connecting the connection pad and the dummy pad. The maximum width of each of the connection pad and the dummy pad is set to be larger than the width of the dummy wiring portion. A bump of an electronic component is flip-chip connected to a connection pad through a resin-containing solder.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: April 25, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kei Murayama
  • Patent number: 9633949
    Abstract: The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
  • Patent number: 9634137
    Abstract: An integrated power transistor circuit includes a contact structure with a first section and a second section. The first section contacts doped regions of transistor cells in a cell array. The second section includes one or more first subsections which adjoin the first section and extend beyond the cell array in the region of selected transistor cells. A second subsection adjoins the one or more first subsections and forms a tapping line, for example for making contact with source regions of power transistor cells. In the region of the cell array, an electrode structure rests on the contact structure. This electrode structure is absent over the second section. The tapping line can thus be formed at a short distance from the electrode structure, with the result that the active chip area is only insubstantially reduced by the tapping line.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Britta Wutte
  • Patent number: 9627737
    Abstract: A high-frequency transmission line in which the alternating-current resistance is low is provided. A high-frequency transmission line 2 is a high-frequency transmission line 2 to transmit an alternating-current electric signal, and contains metal and carbon nanotube, and the carbon nanotube is unevenly distributed at a peripheral part 8 of a cross-section that is of the high-frequency transmission line 2 and that is perpendicular to a transmission direction of the alternating-current electric signal.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: April 18, 2017
    Assignee: TDK CORPORATION
    Inventors: Makoto Yoshida, Kenichi Yoshida, Tohru Inoue, Takaaki Domon, Takashi Ota, Katsunori Osanai
  • Patent number: 9627250
    Abstract: A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wen Wu, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 9627315
    Abstract: A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 18, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Takeshi Morita
  • Patent number: 9620840
    Abstract: A high-frequency transmission line in which the alternating-current resistance is low and that is hard to disconnect is provided. A high-frequency transmission line 2 is a high-frequency transmission line 2 to transmit an alternating-current electric signal, and contains metal and carbon nanotube, and the carbon nanotube is unevenly distributed at a central part 6 of a cross-section that is of the high-frequency transmission line 2 and that is perpendicular to a transmission direction of the alternating-current electric signal.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: April 11, 2017
    Assignee: TDK CORPORATION
    Inventors: Makoto Yoshida, Kenichi Yoshida, Tohru Inoue, Takaaki Domon, Takashi Ota, Katsunori Osanai
  • Patent number: 9613900
    Abstract: An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephan A. Cohen, Eric G. Liniger
  • Patent number: 9613842
    Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick, Edmund J. Sprogis
  • Patent number: 9601443
    Abstract: A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Shih-Hsun Hsu, Shih-Cheng Chang, Shang-Yun Hou, Hsien-Wei Chen, Chia-Lun Tsai, Benson Liu, Shin-Puu Jeng, Anbiarshy Wu
  • Patent number: 9595469
    Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: March 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Patent number: 9589974
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: March 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Iijima, Yoshiaki Himeno, Takamasa Usui
  • Patent number: 9589887
    Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: March 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
  • Patent number: 9583152
    Abstract: A layout structure of a semiconductor memory device including a sub wordline driver is disclosed. The semiconductor memory device layout having a sub wordline driver in which a PMOS region is located includes: a plurality of active regions; and a main word line formed to pass through the active regions. The main word line includes three gate lines.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 28, 2017
    Assignee: SK hynix Inc.
    Inventor: Jae Hong Jeong
  • Patent number: 9570347
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
  • Patent number: 9565776
    Abstract: The present invention provides a method for treating a substrate that supports metal fine particles for forming a plating layer on a circuit pattern or TSVs in various substrates, in which further micronization treatment is enabled compared with the conventional methods, and the formation of a stable plating layer is enabled. The present invention is a method for treating a substrate, the method including bringing a substrate into contact with a colloidal solution containing metal particles in order to support the metal particles that serve as a catalyst for forming a plating layer on the substrate, in which the colloidal solution contains metal particles formed of Pd and having a particle size of 0.6 nm to 4.0 nm and a face-to-face dimension of the (111) plane of 2.254 ? or more. When an organic layer such as SAM is formed on a surface of the substrate before this treatment, the binding force of the Pd particles can be increased.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 7, 2017
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Noriaki Nakamura, Junichi Taniuchi, Hitoshi Kubo, Yuusuke Ohshima, Tomoko Ishikawa, Shoso Shingubara, Fumihiro Inoue
  • Patent number: 9564447
    Abstract: Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: February 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj K. Patil, Ajey P. Jacob, Min-hwa Chi
  • Patent number: 9558993
    Abstract: A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width that is larger than a width of the extending line. The pad includes a protruding portion extending from a lateral portion of the pad. The pattern structure may be formed by simplified processes and may be employed in various semiconductor devices requiring minute patterns and pads.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehwang Sim, Jaeho Min, Jaehan Lee, Keonsoo Kim
  • Patent number: 9559136
    Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: January 31, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aiko Kato, Yu Nishimura, Hiroaki Naruse, Keita Torii
  • Patent number: 9559050
    Abstract: A method for manufacturing a semiconductor device includes forming a first conductor pattern and a second conductor pattern running side by side with each other, including forming a first portion of the first conductor pattern and a second portion of the second conductor pattern by patterning using a first mask, and forming a second portion of the first conductor pattern and a first portion of the second conductor pattern by patterning using a second mask. A first inter-conductor capacity is formed by the first portion of the first conductor pattern and the first portion of the second conductor pattern. A second inter-conductor capacity is formed by the second portion of the first conductor pattern and the second portion of the second conductor pattern.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tetsuya Watanabe
  • Patent number: 9553017
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed. A hard mask layer is formed overlying the upper surface of the ILD layer laterally adjacent to the metal layer. The metal layer is removed to expose the metal line while leaving the hard mask layer intact. An interconnect is formed with the metal line adjacent to the hard mask layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Xunyuan Zhang
  • Patent number: 9553043
    Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Fang-Yu Fan, Yu-Hsiang Kao, Dian-Hau Chen, Shyue-Shyh Lin, Chii-Ping Chen
  • Patent number: 9553217
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a passivation film on a substrate including a first element region, a second element region adjacent to the first element region in a first direction, a third element region adjacent to the first region in a second direction, and a first scribe region extending to the first direction between the first element region and the third element region, forming a first trench in the passivation film between the first scribe region and the first element region, forming a second trench in the passivation film between the third element region and the first scribe region, and forming a film on the passivation film where the trenches have been formed by coating. The each of trenches is formed continuously along the first and the second element region.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 24, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masao Ishioka, Nobutaka Ukigaya
  • Patent number: 9543228
    Abstract: A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: January 10, 2017
    Assignees: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kouichi Kanda, Nobumasa Hasegawa
  • Patent number: 9543200
    Abstract: Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: January 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kunsang Park, Sukyoung Kim, Jisoon Park, Ju-Il Choi, Byung Lyul Park, Gilheyun Choi
  • Patent number: 9536864
    Abstract: This disclosure provides a package structure and its fabrication method. The package structure includes: a protective insulation layer; a wiring layer including at least one metal wire and disposed on the protective insulation layer; and a first package unit disposed on the wiring layer and including a plurality of metal pillars, a first integrated-circuit chip and a first molding compound layer; wherein the plural metal pillars are located in a pillar region and electrically connected to the at least one metal wire, the first integrated-circuit chip is located in a device region and electrically connected to the at least one metal wire, and the first molding compound layer filling up the remaining part of the first package unit.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: January 3, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventor: Shih-Ping Hsu
  • Patent number: 9536821
    Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Homma, Katsuhiko Hotta, Takashi Moriyama
  • Patent number: 9530814
    Abstract: A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate having a front side and a back side, at least two pixels disposed in the first side, a shallow trench isolation disposed in the front side between the at least two pixels, and a crosstalk reduction element disposed in the back side at a location above the shallow trench isolation. The crosstalk reduction element reduces optical and electrical crosstalk and improves the image quality of the CMOS image sensor.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: December 27, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Wenjie Peng, Minwei Xi
  • Patent number: 9524962
    Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andrei Sidelnicov, Andreas Kurz, Alexandru Romanescu
  • Patent number: 9524933
    Abstract: A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines on the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein the second metal material has a different anti-electromigration ability from the first metal material.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: December 20, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Chenglong Zhang
  • Patent number: 9515155
    Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
  • Patent number: 9515148
    Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: December 6, 2016
    Assignees: International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Wai-Kin Li, Chieh-Yu Lin, Yannick Daurelle
  • Patent number: 9508927
    Abstract: A method of manufacturing a phase change memory includes: (i) forming a first dielectric layer, a conductive contact and a first electrode over a semiconductor substrate; (ii) forming a second dielectric layer having an opening over the first dielectric layer, the opening exposing a top surface of the first electrode; (iii) forming a barrier layer lining a sidewall of the opening; (iv) forming a phase change element in the opening, wherein the phase change element includes a base and a peripheral wall extending upwards along the barrier layer from a periphery of the base, and an inner side of the peripheral wall defines a recess having an inlet and a bottom portion; (v) forming a heater filled in the recess; and (vi) forming a second electrode over the heater. A phase change memory is disclosed herein as well.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 29, 2016
    Assignees: Ningbo Advanced Memory Technology Corporation, Being Advanced Memory Taiwan Limited
    Inventors: Yi-Fang Tao, Yu-Jen Lin
  • Patent number: 9510439
    Abstract: Systems and methods described herein provide for a circuit board having multiple fault containment regions therein. The circuit board includes a first fault containment region defined, at least in part, by first and second metal layers coupled to ground. The first fault containment region includes a first signal layer between the first and second metal layers, a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer, and a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer. The circuit board also includes a second fault containment region in a plurality of layers below the first fault containment region.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: November 29, 2016
    Assignee: Honeywell International Inc.
    Inventors: Kenneth Lee Martin, Lucilo De La Torre, James Frederick Peterson, Jonathan Cole