Abstract: A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.

Abstract: Provided is a display apparatus having improved display quality by reducing defects due to static electricity. The display apparatus includes: a substrate including a display area and a peripheral area surrounding the display area, the display area including a main area and a first protruding area and a second protruding area extending from the main area and protruding toward the peripheral area in a first direction, the second protruding area being spaced apart from the first protruding area in a second direction that intersects the first direction, a groove portion is disposed between the first protruding area and the second protruding area; a display unit including a first light emitter and a second light emitter; a first load matching part electrically connected to the first light emitter; and a second load matching part electrically connected to the second light emitter.

Abstract: A thin film transistor array substrate includes a substrate, at least one thin film transistor, a capacitor, an interlayer insulating layer, and a node connection line. The at least one thin film transistor is on the substrate. The capacitor is on the substrate and includes: a bottom electrode on the substrate; a top electrode overlapping the bottom electrode, the top electrode including an opening having a single closed curve shape; and a dielectric layer between the bottom electrode and the top electrode. The interlayer insulating layer covers the capacitor. The node connection line is on the interlayer insulating layer and electrically connects the capacitor to the at least one thin film transistor. An overlapping area of the bottom electrode and the top electrode is divided by the opening into two separate areas.

Abstract: A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties.

Abstract: The method of manufacturing a semiconductor device includes: forming a conductive film including a first metal-containing film and an anti-reflection film including a second metal-containing film which is laminated on the first metal-containing film, the second metal-containing film being different from the first metal-containing film and laminated on the first metal-containing film; patterning the conductive film; forming side wall protection films on side surfaces of the patterned conductive film; etching the anti-reflection film in the patterned conductive film, after formation of the side wall protection films; forming a passivation film on the first metal-containing film and the side wall protection films; and forming, in the passivation film, an opening portion in which a part of a top surface of the first metal-containing film is exposed.

Abstract: Back end of line (BEOL) structures and methods generally includes forming at least two adjacent conductors separated by a space formed in a first dielectric material, wherein a liner layer is intermediate the first dielectric material and each of the at least two adjacent conductors. A second dielectric material in the space between the at least two adjacent conductors and in contact with the first dielectric material at a bottom surface thereof, wherein the first dielectric material is different from the second dielectric material, and wherein the first dielectric material has a nitrogen enriched surface at an interface between the first dielectric material and the second dielectric material. The nitrogen enriched surface can be formed by plasma nitridation, thermal nitridation, or laser annealing in the presence of nitrogen gas, ammonia, or a combination thereof.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a gate structure over a fin structure. The method also includes forming an S/D contact structure over a S/D structure and depositing a protection layer over the S/D contact structure. The protection layer and the S/D contact structure are made of different materials. The method further includes forming an etching stop layer over the protection layer and forming a dielectric layer over the etching stop layer. The method includes forming a first recess through the dielectric layer and the etching stop layer to expose the protection layer and forming an S/D conductive plug in the first recess. The S/D conductive plug includes a barrier layer directly on the protection layer, and the protection layer and the barrier layer are made of different materials.

Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.

Abstract: The disclosed embodiments provide a method for integrating an optical interposer with one or more electronic dies and an optical-electronic (OE) printed circuit board (PCB). This method involves first applying surface-connection elements to a surface of the optical interposer, and then bonding the one or more electrical dies to the optical interposer using the surface-connection elements. Next, the method integrates the OE-PCB onto the surface of the optical interposer, wherein the integration causes the surface-connection elements to provide electrical connections between the optical interposer and the OE-PCB.

Abstract: A method includes providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate; forming a buffer layer over the substrate; forming a dielectric layer over the buffer layer; performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer; and performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening.

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects (21a to 21d) provided in I/O cell rows (10A, 10B) are connected to a power supply interconnect (23) provided between the I/O cell rows (10A, 10B) via power supply interconnects (25a to 25d). The power supply interconnect (23) is thicker than the in-row power supply interconnects (21a to 21d).

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

Abstract: A semiconductor device includes a substrate, a conductive pad region electrically coupled to the substrate, a first dielectric layer over the conductive pad region, and a passivation layer over the first dielectric layer, wherein the passivation layer includes a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer. The laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary.

Abstract: A method of manufacturing a multilayer wiring board is disclosed, the method being capable of reinforcing the multilayer wiring layer and thereby improving the reliability of connection and the flatness on the surface of the multilayer wiring layer. The method includes providing a laminated sheet having a substrate, a first release layer and a metal layer; forming a first wiring layer on the metal layer; alternately stacking insulating layers and wiring layers on the laminated sheet on which the first wiring layer is formed to give a laminate provided with a multilayer wiring layer; stacking a reinforcing sheet on the laminate provided with the multilayer wiring layer at the side opposite to the laminate sheet, while interposing the second release layer; separating the substrate from the metal layer; and separating the reinforcing sheet from the laminate provided with the multilayer wiring layer to give the multilayer wiring board.

Abstract: Methods and systems for improving the performance of a computer performing an electronic design. One or more nets of a netlist are sorted based on an amount of slack and a net of the one or more nets that is unprocessed and that has a least amount of slack is selected as a current target net. A layer of a higher bucket that is unprocessed for the currently selected target net is selected, the higher bucket being higher than a bucket of the current target net. A determination of whether capacity is available to route the current target net on the selected layer of the higher bucket is made and the current target net is routed on the selected layer of the higher bucket in response to capacity being available. One or more nets that are competing for resources with the current target net on the selected layer of the higher bucket are identified as candidate nets in response to capacity not being available.

Abstract: Semiconductor devices and methods for forming the semiconductor devices include first line trenches formed in a dielectric layer on a substrate. Sacrificial spacers are formed on sidewalls of the dielectric layer in the first line trenches. Second line trenches are formed in the dielectric layer, the first line trenches and the second line trenches including alternating rows of trenches separated by the sacrificial spacers. The first line trenches and the second line trenches are filled with conductive material to form conductive lines. The sacrificial spacers are replaced with an isolation material.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.

Abstract: Techniques for single trench damascene interconnect formation using TiN HMO are provided. In one aspect, a method for forming interconnects on a substrate includes: forming an underlayer on the substrate; forming a hardmask on the underlayer; patterning trenches in the hardmask that extend down to the underlayer; forming the interconnects in the trenches; removing the hardmask; and burying the interconnects in an ILD. The trenches can be patterned in the hardmask using a process such as sidewall image transfer. An interconnect structure is also provided.

Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.

Abstract: The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure.

Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a substrate having a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a restraint layer, a plurality of contact plugs, and a plurality of through silicon vias. The restraint layer is disposed on the semiconductor substrate, and the contact plugs are inserted into the restraint layer. The through silicon vias extend from a bottom surface of the semiconductor substrate to a front surface opposite to the back surface and the through silicon vias are in contact with the contact plugs, respectively.

Abstract: The present disclosure provides a semiconductor package, including a first conductive feature configured as an I/O terminal of the semiconductor package, a first passivation layer, a capacitor, and a second passivation layer. The first conductive feature includes a redistribution portion and a via portion. The maximum width of the redistribution portion along a first direction is more than 10 times the maximum width of the via portion along the first direction. The first passivation layer is surrounding the via portion of the first conductive feature. The capacitor is substantially within the first passivation layer and electrically coupled to the first conductive feature. The second passivation layer is formed on the first passivation layer and surrounding the redistribution portion of the first conductive feature. A method of manufacturing the semiconductor package is also provided.

Abstract: A circuit module 2 comprises: a wiring structure 4; an electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which the electronic component 6a, 6b is embedded; and a metal layer 10 provided on a side surface S1 of the insulating resin layer 8 and a side surface S2 of the wiring structure 4. The surface roughness of the side surface S1 of the insulating resin layer 8 is expressed as R1. The surface roughness of the side surface S2 of the wiring structure 4 is expressed as R2. R1 and R2 differ from each other.

Abstract: In accordance with some embodiments of the present disclosure, a semiconductor structure and a fabricating method thereof are provided. The method for forming a semiconductor structure comprises: forming a base substrate; forming a gate structure on the base substrate; forming openings in the base substrate on both sides of the gate structure; forming a barrier layer on sidewalls of the openings adjacent to the gate structure; and forming a doped layer in the openings, and forming a source region or a drain region in the doped layer.

Abstract: A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Abstract: A semiconductor device includes a semiconductor substrate, a metal layer, a dielectric layer, and a via. The metal layer is disposed above the semiconductor substrate. The dielectric layer is disposed between the metal layer and the semiconductor substrate. The via is embedded in the dielectric layer and comprises a first portion and a second portion between the first portion and the semiconductor substrate. The first portion of the via has a first width. The second portion of the via has a second width greater than the first width of the first portion.

Abstract: A via and a method of fabricating a via in an integrated circuit involve forming a trench in dielectric material deposited above a first cap of a first metal level. The method includes patterning a collar from insulator material directly above the first cap, and etching through the first cap, within an area surrounded by the collar, to a first metal layer of the first metal level directly below the first cap. A liner is conformally deposited. The liner lines sidewalls of the collar. A metal conductor is deposited to form the via and a second metal layer of a second metal level.

Abstract: A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.

Abstract: Reliability of a semiconductor device is improved. A first pad electrode is formed in an uppermost layer of a multilayer wiring layer, an insulating film of a non-organic material is formed over the first pad electrode, and an organic insulating film is formed over the insulating film. In the organic insulating film, an opening reaching the first pad electrode and a groove reaching the insulating film are formed. Over the organic insulating film, a plurality of re-wirings each having a barrier metal film and a conductive film are formed. In a plan view, the groove is formed in an area between the re-wirings. At the same time, a width of the groove is smaller than a width of a first portion or a width of a second portion of the re-wirings, respectively, neighboring to each other and extending in a first direction.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Abstract: A method of increasing a tolerance to misalignment errors in forming an interconnect via includes: providing a dielectric substrate including at least first and second adjacent metal conductors laterally from one another in a lower metal wiring layer of the integrated circuit; forming a capping layer over at least a portion of an upper surface of the substrate; forming an insulting layer on at least a portion of the capping layer; forming an opening through the insulating and capping layers to expose the first metal conductor; forming a conductive pedestal on the first metal conductor, the conductive pedestal capping an overlay region in the substrate between the first and second metal conductors resulting from misalignment of the opening relative to the first metal conductor; forming a conductive liner on sidewalls of the opening and on the conductive pedestal; and filling the opening with a conductive material to form the via.

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate and laterally separated in a first direction from a first closest air-gap by a first distance. A second metal wire is arranged within the ILD layer and is laterally separated in the first direction from a second closest air-gap by a second distance that is larger than the first distance. A via is disposed on an upper surface of the second metal wire.

Abstract: A variable resistance memory device includes a metal interconnection layer on a substrate, an interlayer insulating layer on the metal interconnection layer and defining a contact hole for exposing a portion of the metal interconnection layer, a barrier metal layer including a plurality of sub-barrier metal layers inside the contact hole, a plug metal layer on the barrier metal layer and burying the contact hole, and a variable resistance structure on the barrier metal layer and the plug metal layer.

Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

Abstract: A semiconductor interconnect structure and a method of fabricating the same are provided. The semiconductor interconnect structure includes a sea of interconnect lines including metal lines and neighboring dummy lines. The semiconductor interconnect structure further includes a dielectric layer arranged between the sea of lines.

Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.

Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.

Abstract: A solar cell can include a photoelectric conversion unit including a semiconductor substrate, a tunneling layer disposed on the semiconductor substrate, a first conductive type region and a second conductive type region disposed on the tunneling layer at a same side of the semiconductor substrate, and a barrier region disposed between the first and second conductive type regions; and an electrode disposed on the photoelectric conversion unit and including an adhesive layer disposed on the first and second conductive type regions, and an electrode layer disposed on the adhesive layer, in which the adhesive layer has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the photoelectric conversion unit and is less than a coefficient of thermal expansion of the electrode layer.

Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.

Abstract: An image pickup apparatus includes a silicon layer, a wire layer that contains an insulator having a lower dielectric constant than silicon oxide, a cover glass that covers a light receiving portion on a light receiving surface of the silicon layer, and a silicon substrate that covers a back surface of the wire layer, in which a guard ring is formed along an outer edge on the wire layer, a through-hole having a bottom surface that is configured by an electrode pad configured by a conductor of the wire layer and having an outer periphery portion in contact with the silicon layer over a whole periphery is provided in a region of the silicon layer that is not covered with the cover glass, and the insulator of the wire layer is not exposed to an inner surface of the through-hole.