Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
  • Patent number: 10128209
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Lan-Lin Chao, Cheng-Tai Hsiao, Xin-Hua Huang, Hsun-Chung Kuang
  • Patent number: 10128189
    Abstract: A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tigran Zohrabyan, YangJae Shin, Konstantin Bregman, Rolando A. Villanueva, Yunle Sun
  • Patent number: 10118263
    Abstract: Component-locating templates or masks for use with positioning fluid-flow components on monolithic ceramic substrates are provided, as well as techniques for the manufacture of such templates.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: November 6, 2018
    Assignee: Lam Researech Corporation
    Inventors: Michael C. Kellogg, Andrew C. Lee, Christopher J. Pena
  • Patent number: 10115684
    Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: October 30, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
  • Patent number: 10115749
    Abstract: The present disclosure relates to an array substrate and the manufacturing method thereof. The manufacturing method includes depositing a conductive layer on a substrate, forming three poles of at least one thin film transistor (TFT), a first signal line, and a second signal line by etching the conductive layer via a first mask, The method also includes depositing an intermediate layer in sequence, forming a first connecting bridge connecting a first portion and a second portion by etching the intermediate layer via a second mask, depositing a conductive electrode, and forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask. In this way, the time of the manufacturing process of the array substrates may be reduced such that the manufacturing cost may be decreased.
    Type: Grant
    Filed: June 12, 2016
    Date of Patent: October 30, 2018
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Zijian Li
  • Patent number: 10109617
    Abstract: A solid state drive package is provided. The solid state drive package may include an integrated circuit substrate including: a lower redistribution layer; a first chip and a second chip provided on the lower redistribution layer; and a connection substrate provided on the lower redistribution layer, the connection substrate provided on an outer periphery of the first chip and the second chip; and a plurality of third chips provided on the integrated circuit substrate. The plurality of third chips are electrically connected to the first chip and the second chip via the connection substrate and the lower redistribution layer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Ryul Lee, Boseong Kim, Taeduk Nam, Wangju Lee
  • Patent number: 10110135
    Abstract: An electromagnetic induction device, and a power supply apparatus and a display apparatus having the same are disclosed, the electromagnetic induction device comprising: a substrate layer comprising at least one substrate configured to be laid one upon another and a thin-film coil pattern, which is formed on at least one of both surfaces of the substrate and through which an electric current of a signal flows, the at least one substrate having an opening provided at an inner area of the thin-film coil pattern; a core configured to have a shape corresponding to a circulation path of magnetic flux generated by change in an electric current flowing in the thin-film coil pattern, and arranged to penetrate the inner area of the thin-film coil pattern through the opening of the substrate layer; and a heat dissipation layer disposed on one surface of the substrate, the heat dissipation layer configured to dissipate heat from at least one of the substrate layer and the core.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-yong Joo, Jin-hyung Lee
  • Patent number: 10109597
    Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: October 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Basab Chatterjee
  • Patent number: 10103097
    Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: October 16, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng Zou, Alex See, Huang Liu, Hai Cong
  • Patent number: 10096522
    Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Meng-Hung Shen, Ru-Gun Liu, Wei-Cheng Lin
  • Patent number: 10090167
    Abstract: Semiconductor devices and methods of forming the same are disclosed. A dielectric layer is formed over an underlying layer. A first mask layer and a second mask layer are formed on the dielectric layer such that the first mask layer is interposed between the second mask layer and the dielectric layer. An opening is formed in the first mask layer, the second mask layer and the dielectric layer. Subsequently, the second mask layer is removed. The opening is extended and corners of the first mask layer are rounded. A conductive feature is formed in the extended opening.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 10083905
    Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10083858
    Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas Vincent Licausi, Guillaume Bouche
  • Patent number: 10079205
    Abstract: An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. At least a portion of the conductive structure tapers along a direction from the non-insulator structure to the dielectric structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10079221
    Abstract: A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips may include a plurality of through-vias, each formed at a corresponding location in the plurality of through-vias, and each of the plurality of through-vias is electrically coupled with a through-via in a neighboring stacked chip in a diagonal direction. The semiconductor apparatus includes a plurality of through-via arrays, and performs repair operation with a unit of the through-via array.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: September 18, 2018
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Patent number: 10079173
    Abstract: One illustrative method disclosed includes, among other things, forming a layer of insulating material comprising a first insulating material above a substrate and forming a metallization blocking structure in the layer of insulating material at a location that is in a path of a metallization trench to be formed in the layer of insulating material, the metallization blocking structure comprising a second insulating material that is different from the first insulating material. The method also includes forming the metallization trench in the layer of insulating material on opposite sides of the metallization blocking structure and forming a conductive metallization line in the metallization trench on opposite sides of the metallization blocking structure.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 18, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Geng Han
  • Patent number: 10075694
    Abstract: A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node. Sensing circuits are coupled to elementary elements of different levels. The outputs of the sensing circuits are used to generate a number, which serves as an identification number of the semiconductor chip.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: September 11, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Patent number: 10074631
    Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Hsien-Wei Chen, Der-Chyang Yeh, An-Jhih Su
  • Patent number: 10074659
    Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Kiyotada Funane
  • Patent number: 10074557
    Abstract: A first film having a repetitive line pattern is formed on an under film. A second film is formed on a side surface of the first film. The second film has an etching selectivity different from that of the first film. A third film is formed on an upper surface and a side surface of the second film. The third film has an etching selectivity different from those of the first and second films. A resist pattern with an opening is formed on the third film. A recess that exposes upper surfaces of the first, second and third films is formed by etching the third film by using the resist pattern as an etching mask. An upper surface of the under film is exposed by etching the first and third films. A through hole that penetrates through the under film is formed by etching the under film.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 11, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Hidetami Yaegashi
  • Patent number: 10074610
    Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 11, 2018
    Assignee: Sony Corporation
    Inventors: Naoki Saka, Daisaku Okamoto, Hideki Tanaka
  • Patent number: 10074609
    Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 11, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Seid Hadi Rasouli, Animesh Datta, Ohsang Kwon
  • Patent number: 10068852
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Patent number: 10068859
    Abstract: A structure for arresting the propagation of cracks during the dicing of a semiconductor wafer into individual chips includes a monolithic metallic plate that traverses multiple dielectric layers peripheral to an active region of a chip. One or more metallic plates may be formed using lithography and electroplating techniques between the active device region and a peripheral kerf region, where each metallic plate includes a concave feature that faces the kerf region of the wafer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas A. Polomoff, Mohamed Rabie, Victoria L. Calero Diaz Del Castillo, Danielle Degraw, Michael Hecker
  • Patent number: 10062607
    Abstract: A method for forming metallization in a workpiece includes electrochemically depositing a second metallization layer on the workpiece comprising a nonmetallic substrate having a dielectric layer disposed over a substrate and a continuous first metallization layer disposed on the dielectric layer and having at least one microfeature comprising a recessed structure, wherein the first metallization layer at least partially fills a feature on the workpiece, where the first metallization layer is a cobalt or nickel metal layer, and wherein the second metallization layer is a cobalt or nickel metal layer that is different from the metal of the first metallization layer, electrochemically depositing a copper cap layer after filling the feature, and annealing the workpiece to diffuse the metal of the second metallization layer into the metal of the first metallization layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 28, 2018
    Assignee: APPLIED Materials, Inc.
    Inventors: Ismail T. Emesh, Roey Shaviv, Mehul Naik
  • Patent number: 10062619
    Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Juergen Thees, Peter Baars
  • Patent number: 10055077
    Abstract: The present invention relates to a touch panel having pen touch and electrode touch functions. Specifically, the present invention relates to a touch panel, which can enhance visibility of a view area and simplify the process of manufacturing the touch panel by improving wiring of sensing patterns for pen touch and arranging overlap structures, which are created as the sensing patterns cross each other, in a separate area other than the view area.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 21, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Seongsu Oem, Young Sun You, Sun Hwa Lee, Kwang Yong Jin, Yongjae Choi
  • Patent number: 10056322
    Abstract: An interposer which can better prevent detachment of a conductive layer pattern due to thermal expansion and thermal contraction. The interposer includes a substrate having a through hole; an insulative resin layer formed on a surface of the substrate and including a conductive via; a wiring layer disposed on the substrate with the insulative resin layer interposed therebetween; an inorganic adhesive layer formed only on a side surface of the through hole; and a through electrode filled in a connection hole which is formed by the inorganic adhesive layer in the through hole so as to penetrate between both surfaces of the substrate, wherein the through electrode is electrically connected to the wiring layer via the conductive via, and a thermal expansion coefficient of the inorganic adhesive layer is larger than a thermal expansion coefficient of the substrate and smaller than a thermal expansion coefficient of the through electrode.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 21, 2018
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Koji Imayoshi, Syuji Kiuchi
  • Patent number: 10049946
    Abstract: A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g. germanium) and an upper portion of another type of semiconductor (e.g. indium arsenide. The lower portion of the column provides a channel region for a transistor of one type, while the upper column provides a channel region for a transistor of another type. This provides a complementary pair that occupies a minimum of integrated circuit surface area. The complementary transistors can be utilized in a variety of circuit configurations. Described are complementary transistors where the lower transistor is p-type and the upper transistor is n-type.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Richard Kenneth Oxland
  • Patent number: 10043886
    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a dielectric layer at a same level as the dummy gate stack, removing the dummy gate stack to form an opening in the dielectric layer, filling a metal layer extending into the opening, and etching back the metal layer, with remaining portions of the metal layer having edges lower than a top surface of the dielectric layer. The opening is filled with a conductive material, and the conductive material is over the metal layer. The metal layer and the conductive material in combination form a replacement gate. A source region and a drain region are formed on opposite sides of the replacement gate.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10043910
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of gate spacers and a gate stack. The gate spacers are over the semiconductor substrate. The gate stack is over the semiconductor substrate and between the gate spacers. The gate stack includes a carbon-containing titanium nitride layer and an N-work function conductor layer over the carbon-containing titanium nitride layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
  • Patent number: 10038099
    Abstract: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 10026644
    Abstract: Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate, wherein the first word lines and the second word lines are arranged periodically and extend in a first direction. Bit lines are formed over the first and second word lines, wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word lines to the substrate.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: July 17, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 10014278
    Abstract: A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: July 3, 2018
    Assignee: SK hynix Inc.
    Inventor: Ho Young Son
  • Patent number: 10013521
    Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joachim Keinert, Jens Noack, Monika Strohmer, Holger Wetter
  • Patent number: 10014102
    Abstract: An inductor may include: a body, and a first and a second external electrode formed on end surfaces of the body. The body may include a coil support layer, a conductive coil formed on at least one surface of the coil support layer, a lamination part formed in a gap of the conductive coil and on an upper surface thereof, an insulating coating part formed to enclose an overall surface of the conductive coil on which the lamination part is formed, and upper and lower cover layers covering the overall surface of the conductive coil on which the insulating coating part is formed.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 3, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woon Chul Choi, Sung Hyun Kim, Hye Yeon Cha
  • Patent number: 10008563
    Abstract: Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar Van der Straten, Chih-Chao Yang
  • Patent number: 10008256
    Abstract: A layout structure of a sub word line of a semiconductor memory device is disclosed. A sub word line driver of a semiconductor memory device includes: a plurality of first active regions arranged in a line shape in a first direction; a plurality of second active regions spaced apart from the plurality of first active regions a predetermined distance in a second direction, and arranged in a line shape in the first direction; a first main word line disposed over the first active regions, and formed in a diagonal direction in the first active regions; a second main word line disposed over the second active regions, and formed in a diagonal direction in the second active regions; and a pickup active region disposed between the first main word line and the second main word line.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 26, 2018
    Assignee: SK hynix Inc.
    Inventor: Young Min Kim
  • Patent number: 10002833
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: June 19, 2018
    Assignee: MediaTek Inc.
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
  • Patent number: 10002999
    Abstract: Disclosed is a thermoelectric conversion material with high performance. The thermoelectric material according to the present disclosure may be represented by the following chemical formula 1: CuxSe??<Chemical Formula 1> where 2<x?2.6.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 19, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Kyung-Moon Ko, Tae-Hoon Kim, Cheol-Hee Park
  • Patent number: 9999136
    Abstract: The present invention concerns an electronic module with at least one component embedded in insulating material.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 12, 2018
    Assignee: GE Embedded Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 9997459
    Abstract: A semiconductor device includes a semiconductor body having a front face, a back face and an active zone at the front face. A front surface metallization layer having a front face and a back face is disposed over the semiconductor body so that the back face of the front surface metallization layer faces the front face of the semiconductor body and is electrically connected to the active zone. An upper barrier layer made of amorphous molybdenum nitride is disposed on the front face of the front surface metallization layer.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Jochen Hilsenbeck, Jens Peter Konrath, Stefan Krivec
  • Patent number: 9991207
    Abstract: Test key structures, integrated circuit packages and methods of forming the same are disclosed. One of the test key structures includes a first pattern over a polymer layer, and at least one second pattern covering the first pattern. Besides, the second pattern and the first pattern have substantially the same outer profile, one of the first pattern and the second pattern includes a dielectric material and the other of the first pattern and the second pattern includes a metal material.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Yun Chen, Hsien-Wei Chen, Li-Hsien Huang
  • Patent number: 9991210
    Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: June 5, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
  • Patent number: 9984976
    Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: May 29, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yana Cheng, Yong Cao, Srinivas Guggilla, Sree Rangasai Kesapragada, Xianmin Tang, Deenesh Padhi
  • Patent number: 9972571
    Abstract: The semiconductor structure includes a semiconductor substrate; field-effect devices disposed on the semiconductor substrate, wherein the field-effect devices include gates with elongated shape oriented in a first direction; a first metal layer disposed over the gates; a second metal layer disposed over the first metal layer; and a third metal layer disposed over the second metal layer. The first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction. The second metal layer includes a plurality of second metal lines oriented in the first direction. The third metal layer includes a plurality of third metal lines oriented in the second direction. The first metal lines have a first thickness, the second metal lines have a second thickness, the third metal lines have a third thickness, and the second thickness is less than the first thickness and the third thickness.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: May 15, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang
  • Patent number: 9953916
    Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
  • Patent number: 9953941
    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 24, 2018
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Paul M. Enquist
  • Patent number: 9946117
    Abstract: According to one embodiment, a display device includes a first substrate including a display area and a terminal area, a second substrate opposed to the display area, a first sealing member formed between the first and second substrate and surrounding the display area, a second sealing member formed between the first sealing member and a first edge of the second substrate located at the terminal area side, and a first spacer formed between the first and second sealing member and formed at least in contact with the second sealing member. The first spacer includes a first side surface at the second sealing member side and a second side surface at the first sealing member side, and the first side surface at least partly projects toward the first edge.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 17, 2018
    Assignee: Japan Display Inc.
    Inventors: Yusuke Morita, Nobuko Fukuoka, Kazuya Daishi
  • Patent number: 9947583
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee