Multiple Metal Levels On Semiconductor, Separated By Insulating Layer (e.g., Multiple Level Metallization For Integrated Circuit) Patents (Class 257/758)
  • Patent number: 9502358
    Abstract: An integrated circuit includes a signal line and a plurality of shielding structures. The signal line is routed along a first direction and is in a first metallization layer. Each shielding structure includes a plurality of non-contiguous shielding patterns aligned along the first direction. The plurality of shielding structures includes a first and a second shielding structures in a second metallization layer that adjoins the first metallization layer and a third and a fourth shielding structures in a third metallization layer that adjoins the first metallization layer. The first metallization layer is between the second and the third metallization layers. The first and the second shielding structures are separated from each other along a second direction perpendicular to the first direction. The third and the fourth shielding structures are separated from each other along the second direction.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 9502346
    Abstract: An integrated circuit that includes a substrate, a metal layer over the substrate and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer and an ultra-thick metal (UTM) layer is in the via.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hung Lu, Ching-Chen Hao
  • Patent number: 9496173
    Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Christopher M. Pelto, Andrew W. Yeoh
  • Patent number: 9490213
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 8, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 9485874
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: November 1, 2016
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 9472448
    Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 9472560
    Abstract: A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney, Marco Domenico Tiburzi
  • Patent number: 9461003
    Abstract: A semiconductor device includes a circuit pattern on a substrate, a shielding pattern on the circuit pattern and constituted by a plurality of parallel bars, and lower overlay marking on the shielding pattern and constituted by a plurality of parallel bars which define parallel slits between the bars. The pitch of the bars of the shielding pattern is smaller than the pitch of the bars of the lower overlay marking.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: October 4, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jimyung Kim, Yigwon Kim, Suhyun Kim, Kwangsub Yoon, Bumjoon Youn, Narak Choi
  • Patent number: 9455184
    Abstract: A method comprises depositing a first alloy layer over a substrate, depositing a metal layer over the first alloy layer, depositing a second alloy layer over the metal layer, patterning the first alloy layer, the metal layer and the second alloy layer to form a metal structure and depositing a dielectric layer over the metal structure through a chemical vapor deposition (CVD) process.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fu Yeh, Hsiang-Huan Lee
  • Patent number: 9449933
    Abstract: A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface of the metal trace.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Ming-Da Cheng, Wen-Hsiung Lu, Bor-Rung Su
  • Patent number: 9449874
    Abstract: A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: September 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theodorus E. Standaert, Vamsi K. Paruchuri
  • Patent number: 9443869
    Abstract: A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 9443808
    Abstract: A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: September 13, 2016
    Assignee: SYNAPTICS DISPLAY DEVICES GK
    Inventors: Hisao Nakamura, Yuichi Nakagomi, Yasuhiro Kumagai
  • Patent number: 9437537
    Abstract: A semiconductor device including conductive lines configured to include first lines extending generally in parallel in a first direction and second lines extending generally in parallel in a second direction to intersect the first direction from the respective ends of the first lines and each second line having a width wider than the first line, and dummy patterns formed between the second lines.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: September 6, 2016
    Assignee: SK hynix Inc.
    Inventors: Hyun Sub Kim, Sung Bo Shim
  • Patent number: 9437552
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: September 6, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Patent number: 9431505
    Abstract: A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 9425054
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; performing a pre-treatment including a first hydrogen annealing on a surface of the substrate; forming a gate dielectric layer over the substrate; performing a post-treatment including a second hydrogen annealing on the substrate including the gate dielectric layer; and forming a gate electrode over the gate dielectric layer.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: Tae-Hyeok Lee, Kyu-Tae Park
  • Patent number: 9425066
    Abstract: A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: August 23, 2016
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang
  • Patent number: 9419018
    Abstract: A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: August 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hidekazu Miyairi, Shunpei Yamazaki, Motomu Kurata
  • Patent number: 9418877
    Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: August 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim, Jae Sik Lee
  • Patent number: 9419217
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: August 16, 2016
    Assignee: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Lidia Vereen, Bruce Bateman, David Eggleston, Louis Parrillo
  • Patent number: 9397039
    Abstract: A semiconductor device includes: a second conductive layer formed over a first conductive layer; and a dummy conductive layer formed between the first and second conductive layers with through-holes formed therein. The first and second conductive layers include signal lines electrically coupled to each other through signal metal contacts passing through the through-holes, and the second conductive layer includes power lines electrically coupled to the dummy conductive layer through power metal contacts.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: July 19, 2016
    Assignee: SK hynix Inc.
    Inventor: Min Su Park
  • Patent number: 9397048
    Abstract: A semiconductor structure includes a substrate, a first through hole disposed in the substrate and filled with conductive material, and a second through hole disposed in the substrate and filled with isolation material, which a Young's modulus of the isolation material is smaller than a Young's modulus of the conductive material to balance stress from the conductive material.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: July 19, 2016
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 9391046
    Abstract: A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: July 12, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yeonglm Park, HeeJo Chi, HyungMin Lee
  • Patent number: 9385100
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a base material, an insulation layer on the traces, the insulation layer having a top surface coplanar with the top surface of the base material; and an integrated circuit die connected to the bonding sites.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 5, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Hun Teak Lee, YoungChul Kim, Hyunll Bae, HeeSoo Lee, HeeJo Chi
  • Patent number: 9378893
    Abstract: A capacitor provides a plurality of selectable capacitance values, by selective connection of six capacitor sections of a capacitive element each having a capacitance value. The capacitor sections are provided in a plurality of wound cylindrical capacitive elements. Two vertically stacked wound cylindrical capacitance elements may each provide three capacitor sections. There may be six separately wound cylindrical capacitive elements each providing a capacitor section. The capacitor sections have a common element terminal.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: June 28, 2016
    Assignee: American Radionic Company, Inc.
    Inventor: Robert M. Stockman
  • Patent number: 9373682
    Abstract: An integrated circuit includes a guard ring structure including a guard ring with integrated well taps to reduce the silicon area required for the guard ring structure. In some embodiments, the guard ring structure includes an N-type guard ring surrounded by inner and outer P-type guard rings. The N-type guard ring is formed with interleaving deep N-wells and P-wells that are formed on an N-type buried layer and are electrically shorted together. The inner and outer P-type guard rings are formed in P-wells. The interleaving deep N-wells and P-wells of the N-type guard ring may be connected to ground or be left floating. By integrating P-well contacts in the N-type guard ring, P-well contacts, or P-taps, for the P-type guard ring can be eliminated.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 21, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 9373601
    Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: June 21, 2016
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Yuan Chang Su, Cheng-Lin Ho, Chung-Ming Wu, You-Lung Yen
  • Patent number: 9374886
    Abstract: A signal line that is easily inflected includes a laminated body including at least insulator layers that include flexible material and are laminated from a positive direction side in a z axis direction to a negative direction side therein in this order. A ground conductor is securely fixed to a main surface on the positive direction side of the insulation sheet in the z axis direction. A signal line is securely fixed to a main surface on the positive direction side of the insulator layer in the z axis direction. A ground conductor is securely fixed to a main surface on the positive direction side of the insulator layer in the z axis direction. The ground conductors and the signal line define a stripline structure. The laminated body is inflected so that the insulator layer is located on an inner periphery side, compared with a location of the insulator layer.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: June 21, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noboru Kato, Jun Sasaki
  • Patent number: 9373591
    Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 21, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jong-yeul Jeong
  • Patent number: 9362367
    Abstract: Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: June 7, 2016
    Assignees: Auburn University, Rutgers, The State University of New Jersey
    Inventors: John R. Williams, Ayayi C. Ahyi, Tamara F Isaacs-Smith, Yogesh K. Sharma, Leonard C. Feldman
  • Patent number: 9362525
    Abstract: Disclosed is a method for contacting a device with a conductor 6, the device 1 comprising a substrate 2 with at least one cell 3, a contact region 4 and an encapsulation 5, wherein the encapsulation 5 encapsulates at least the contact region 4, the method comprising the steps of arranging the conductor 6 on the encapsulation 5, and interconnecting the conductor 6 with the contact region 4 without removing the encapsulation 5 between the conductor 6 and the contact region 4 beforehand. This invention is advantageous as the encapsulation 5 between the conductor 6 and the contact region 4 does not need to be removed beforehand anymore.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: June 7, 2016
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jeroen Henri Antoine Maria Van Buul, Holger Schwab
  • Patent number: 9355933
    Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming Hung Tseng, Chen-Shien Chen
  • Patent number: 9355910
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 31, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 9349636
    Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Hui Jae Yoo, Tejaswi K. Indukuri, Ramanan V. Chebiam, James S. Clarke
  • Patent number: 9341563
    Abstract: An aggregate board, comprising: an insulator having a front face and a rear face; a pair of a first front face wiring pattern and a second front face wiring pattern, a plurality of which are arranged on the front face of the insulator; a pair of a first rear face wiring pattern and a second rear face wiring pattern, a plurality of which are arranged on the rear face of the insulator; at least one first inner layer wiring pattern that is separated from the second front face wiring pattern and the second rear face wiring pattern, that is connected to the first front face wiring pattern and the first rear face wiring pattern, and that extends in a first direction in an interior of the insulator; at least one second inner layer wiring pattern that is separated from the first front face wiring pattern and the first rear face wiring pattern, that is connected to the second front face wiring pattern and the second rear face wiring pattern, and that has a part that extends in a second direction which is different fro
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 17, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Koichi Amari
  • Patent number: 9337082
    Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Junjing Bao, Wai-Kin Li
  • Patent number: 9337090
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: May 10, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Patent number: 9337208
    Abstract: A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is formed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 10, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Pei-Ci Jhang, Chun-Min Cheng
  • Patent number: 9337141
    Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: May 10, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang
  • Patent number: 9331017
    Abstract: This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Tao Wu, Islam A. Salama
  • Patent number: 9330967
    Abstract: A method of fabricating a semiconductor device with reduced leak paths is disclosed. The method comprises etching a void in non-conductive material in the semiconductor device to provide a conduction path between isolated material, forming a non-conductive surface layer on an unintended conductive item adjacent to the void, and filling the void with a conductive material. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void using plasma oxidation operations. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void using plasma oxidation operations. The unintended conductive item may comprise a conductive impurity or conductive residue. The void may comprise a trench or a hole for a via.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Guan-Jie Shen
  • Patent number: 9324709
    Abstract: Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source/drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Viraj Y. Sardesai, Raghavasimhan Sreenivasan
  • Patent number: 9318547
    Abstract: A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n? drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n+ semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p+ base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p+ base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n+ semiconductor regions in the channel regions; and a p+ floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p+ base regions and
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 19, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Kumagai
  • Patent number: 9318431
    Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 9312326
    Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: April 12, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Renatas Jakushokas, Vaishnav Srinivas, Robert Won Chol Kim
  • Patent number: 9312222
    Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yuan Ting, Chung-Wen Wu
  • Patent number: 9306156
    Abstract: In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Sun Noh, Jong-Chul Park, Shin Kwon, Hyung-Joon Kwon, Chae-Lyoung Kim, Hye-Ji Yoon
  • Patent number: 9305859
    Abstract: In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 5, 2016
    Assignees: ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED, SKYWORKS SOLUTIONS (HONG KONG) LIMITED
    Inventors: Richard K. Williams, Keng Hung Lin
  • Patent number: 9302906
    Abstract: In one embodiment, a method of forming a MEMS device includes providing a silicon wafer with a base layer and an intermediate layer above an upper surface of the base layer. A first electrode is defined in the intermediate layer and an oxide portion is provided above an upper surface of the intermediate layer. A cap layer is provided on an upper surface of the oxide portion and a second electrode is defined in the cap layer. The method further includes etching the oxide portion to form a cavity such that when the second electrode and the cavity are projected onto the intermediate layer, the projected second electrode encompasses the projected cavity.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 5, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Ando Feyh, Andrew B. Graham