Encapsulated Patents (Class 257/787)
  • Patent number: 8587012
    Abstract: The present disclosure provides a light emitting diode (LED) package, which includes a first substrate with electrodes disposed on a top thereof and a second substrate with an LED chip disposed on a top thereof. The LED chip is connected with the electrodes via wires. A first package layer is disposed on the top of the first substrate to cover the wires and electrodes. A fluorescent layer is disposed on the top of the second substrate to cover the LED chip. The present disclosure also provides a mold and a method of manufacturing the LED package.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: November 19, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Shiun-Wei Chan, Chih-Hsun Ke
  • Patent number: 8587125
    Abstract: A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: November 19, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Publication number: 20130300002
    Abstract: A resin-sealed module is provided which reduces the warpage of a substrate and the detachment between a sealing resin and the substrate which occur during re-reflow, has the excellent flatness of the top and bottom surfaces, and reduces the occurrence of the short failures. A resin layer made of a thermoplastic resin is arranged on top of a substrate, and a resin layer made of a thermosetting resin is arranged on top of this resin layer, thereby reducing the warpage of the substrate and the detachment between the sealing resin and the substrate which occur during re-reflow.
    Type: Application
    Filed: July 12, 2013
    Publication date: November 14, 2013
    Inventors: Yasuo Yokoyama, Tetsuya Kitaichi
  • Patent number: 8581396
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 12, 2013
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 8581372
    Abstract: According to one embodiment, a semiconductor storage device includes a plate and an external connection terminal. The plate is molded in a resin mold section. A semiconductor memory chip is placed on the plate. The external connection terminal is exposed to the outer circumferential surface of the semiconductor storage device. The plate includes a plurality of exposed portions exposed to the outer circumferential surface of the resin mold section. The plurality of exposed portions is electrically insulated from each other inside the resin mold section.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Asada, Taku Nishiyama, Atsuko Seki
  • Patent number: 8581395
    Abstract: A hybrid integrated circuit device having high mount reliability includes a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Moriyama, Tomio Yamada
  • Patent number: 8581387
    Abstract: A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side thereof, and a wire in the via electrically insulated from the semiconductor substrate having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate. The through wire interconnect also includes a first contact on the wire proximate to the first side of the semiconductor substrate, a second contact on the second end of the wire, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. The through wire interconnect can also include a bonding member bonded to the first end of the wire and to the substrate contact having a tip portion forming the first contact.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8581421
    Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 12, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa, Hirokazu Yoshino
  • Patent number: 8574960
    Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: November 5, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 8575763
    Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: November 5, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Masanori Yoshida, Fumitomo Watanabe
  • Patent number: 8569892
    Abstract: A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: October 29, 2013
    Assignee: NEC Corporation
    Inventors: Kentaro Mori, Daisuke Ohshima, Shintaro Yamamichi, Hideya Murai, Katsumi Maeda, Katsumi Kikuchi, Yoshiki Nakashima
  • Patent number: 8569082
    Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: October 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Steven A. Kummerl, Sreenivasan K Koduri
  • Patent number: 8569895
    Abstract: A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 29, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SooMoon Park, ByoungWook Jang, DongSoo Moon
  • Patent number: 8569875
    Abstract: A biometric sensor device, such as a fingerprint sensor, comprises a substrate to which is mounted a die on which is formed a sensor array and at least one conductive bezel. The die and the bezel are encased in a unitary encapsulation structure to protect those elements from mechanical, electrical, and environmental damage, yet with a portion of the sensor array and the bezel exposed or at most thinly covered by the encapsulation or other coating material structure.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: October 29, 2013
    Assignee: Authentec, Inc.
    Inventors: Robert Henry Bond, Alan Kramer, Giovanni Gozzini
  • Patent number: 8564012
    Abstract: A method for manufacturing an optoelectronic apparatus includes attaching bottom surfaces of first and second packaged optoelectronic semiconductor devices (POSDs) to a carrier substrate (e.g., a tape) so that there is a space between the first and second POSDs. An opaque molding compound is molded around portions of the first and second POSDs attached to the carrier substrate, so that peripheral surfaces of the first POSD and the second POSD are surrounded by the opaque molding compound, the space between the first and second POSDs is filled with the opaque molding compound, and the first and second POSDs are attached to one another by the opaque molding compound. The carrier substrate is thereafter removed so that electrical contacts on the bottom surfaces of the first and second POSDs are exposed. A window for each of the POSDs is formed during the molding process or thereafter.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: October 22, 2013
    Assignee: Intersil Americas LLC
    Inventors: Seshasayee S. Ankireddi, Lynn K. Wiese
  • Patent number: 8558399
    Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: October 15, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Kambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
  • Patent number: 8558400
    Abstract: A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Woo Park, Eunchul Ahn
  • Patent number: 8558368
    Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 15, 2013
    Assignee: GEM Services, Inc.
    Inventors: Anthony Chia, Liming Wong, Hongbo Yang, Anthony C. Tsui, Hui Teng, Ming Zhou
  • Patent number: 8558364
    Abstract: An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: October 15, 2013
    Assignee: Innovative Micro Technology
    Inventor: Jeffery F. Summers
  • Patent number: 8557629
    Abstract: Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: October 15, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Seong Kim, Dong Joo Park, Kwang Ho Kim, Hee Yeoul Yoo, Jeong Wung Jeong
  • Publication number: 20130264724
    Abstract: The invention relates to a method for encapsulating an electronic arrangement against permeants, wherein an electronic arrangement is made available on a substrate, wherein, in a vacuum, that area of the substrate which embraces that region of the electronic arrangement which is to be encapsulated, preferably said area and that region of the electronic arrangement which is to be encapsulated, is brought into contact with a sheet material comprising at least one adhesive compound and a composite is produced therefrom. The invention also relates to an apparatus for implementing the method and to an encapsulated electronic arrangement produced thereby.
    Type: Application
    Filed: November 3, 2011
    Publication date: October 10, 2013
    Applicant: Tesa SE
    Inventors: Klaus Telgenbüscher, Judith Grünauer, Jan Ellinger
  • Patent number: 8552546
    Abstract: Provided is a semiconductor package. The semiconductor package may include a first semiconductor package having first semiconductor chips sequentially stacked on a substrate. In example embodiments, the first semiconductor chips may have a cascaded arrangement in which first sides and second sides of the semiconductor chips define cascade patterns. The cascaded arrangement may extend in a first direction to define a space between the first sides of the first semiconductor chips and the substrate. The semiconductor package may also include at least one first connection wiring at the second sides of the semiconductor chips, the at least one first connection wiring being configured to electrically connect the substrate with the first semiconductor chips. In addition, the semiconductor package may further include a first filling auxiliary structure adjacent to the first sides of the first semiconductor chips.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Sang Song, Seok-Keun Lim, In-Wook Jung, Bong-Ken Yu, Sang-Wook Park, Ji-Seok Hong
  • Patent number: 8552539
    Abstract: A shielded package includes a shield assembly having a shield fence, a shield lid, and a shield lid adhesive electrically coupling the shield lid to the shield fence. The shield fence includes a porous sidewall through which molding compound passes during molding of the shielded package. Further, the shield fence includes a central aperture through which an electronic component is die attached and wire bonded.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: October 8, 2013
    Assignee: Amkor Technology, Inc.
    Inventor: Donald Craig Foster
  • Patent number: 8552498
    Abstract: A semiconductor device in which defects in characteristics due to electrostatic discharge is reduced and a method for manufacturing the semiconductor device are provided. The semiconductor device has at least one of these structures: (1) a structure in which a first and second insulating films are in direct contact with each other in a peripheral region of a circuit portion, (2) a structure in which a first and second insulators are closely attached to each other, and (3) a structure in which a first conductive layer and a second conductive layer are provided on outer surfaces of the first insulator and the second insulator, respectively, and electrical conduction between the first and second conductive layers is achieved at a side surface of the peripheral region. Note that the conduction at the side surface can be achieved by cutting a plurality of semiconductor devices into separate semiconductor devices.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yoshiaki Oikawa
  • Publication number: 20130256923
    Abstract: A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer.
    Type: Application
    Filed: May 30, 2013
    Publication date: October 3, 2013
    Inventors: Yoke Hor Phua, Yung Kuan Hsiao
  • Publication number: 20130256922
    Abstract: In a method for fabricating a semiconductor device, a carrier and at least one semiconductor chip are provided.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: Infineon Technologies AG
    Inventors: Michael Bauer, Daniel Porwol, Ulrich Wachter
  • Patent number: 8546960
    Abstract: A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Yamazaki
  • Patent number: 8546194
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; forming a conductive post on the base carrier, the conductive post having a top protrusion with a protrusion top side; mounting a base integrated circuit over the base carrier; and forming a base encapsulation over the base integrated circuit, the base encapsulation having an encapsulation top side and an encapsulation recess with the conductive post partially exposed within the encapsulation recess, the encapsulation top side above the protrusion top side.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: October 1, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: JoonYoung Choi, YongHyuk Jeong, DaeSik Choi
  • Patent number: 8541891
    Abstract: A semiconductor device having a first rectangular chip on which wires, electrode pads and chip mounting area are provided, a first dame formed on the first rectangular chip around the electrode pads and the chip mounting area so as to cover the wires and an under fill formed by filling liquid resin between a second rectangular chip mounted on the chip mounting area in a flip-chip manner and the first rectangular chip.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: September 24, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Yoshihiro Saeki
  • Patent number: 8541872
    Abstract: A method of manufacture of an integrated circuit package system includes: forming a non-inverted internal stacking module including: fabricating an internal stacking module (ISM) substrate having an ISM component side and an ISM coupling side, coupling an internal stacking module integrated circuit to the ISM component side, coupling stacking structures, adjacent to the internal stacking module integrated circuit, on the ISM component side, and molding a stacking module body having a top surface that is coplanar with and exposes the stacking structures; forming a base package substrate under the non-inverted internal stacking module; coupling middle structures between the base package substrate and the ISM coupling side; and forming a base package body on the base package substrate, the middle structures, and the non-inverted internal stacking module including exposing the top surface of the stacking module body to be coplanar with the base package body.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: September 24, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 8541260
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a apace between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surfaces, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 24, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Patent number: 8536718
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a material layer including grooves in a fillet region that are substantially parallel and adjacent an integrated circuit; and forming a resin between the substrate and the integrated circuit that contacts a trench trace exposed by the grooves.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: September 17, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, Oh Han Kim
  • Patent number: 8536715
    Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: September 17, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Patent number: 8536689
    Abstract: An integrated circuit package system is provided including an integrated circuit package system including an integrated circuit and a lead frame. The lead frame has a multi-surface die attach pad and the integrated circuit is mounted to the multi-surface die attach pad.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: September 17, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Il Kwon Shim, Sheila Rima C. Magno, Dennis Guillermo
  • Patent number: 8536688
    Abstract: An integrated circuit leadframe and a fabrication method for fabricating the integrated circuit leadframe include forming a leadframe having leads around a die pad that has a peripheral die pad rim. A discrete, alternately staggered surface configuration is formed in the die pad rim. The discrete, alternately staggered surface configuration creates space in the die pad for connecting and separating ground bond wire-bonds and down bond wire-bonds, and provides for locking encapsulant firmly to the die pad.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: September 17, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Hoon Ahn, Pandi Chelvam Marimuthu
  • Patent number: 8531043
    Abstract: An integrated circuit package system includes: providing a substrate; mounting a first package above the substrate, the first package having a mold cavity exposing an exposed portion on a first integrated circuit from a first package encapsulation; mounting a second package above the first package and attached to the exposed portion of the first integrated circuit; mounting a structure above the second package and connected to the substrate around the first package; and encapsulating the first package and the second package with an outer encapsulation having a completely planar top or a planar top co-planar to a top surface of the structure.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: September 10, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Jong-Woo Ha, Reza Argenty Pagaila
  • Patent number: 8531034
    Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hak-Kyoon Byun, Dae-Young Choi, Mi-Yeon Kim
  • Patent number: 8531015
    Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: September 10, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi C. Marimuthu, Shuangwu Huang, Nathapong Suthiwongsunthorn
  • Patent number: 8524595
    Abstract: A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mirng-Ji Lii, Hsin-Hui Lee
  • Patent number: 8525285
    Abstract: A semiconductor device having a substrate including a photodiode; a resin layer formed on an upper surface of the substrate, the resin layer not covering a light receiving region of the photodiode, the resin layer including at least one groove surrounding the light receiving region; and a molding resin portion formed by mold-sealing the photodiode with the resin layer thereon so as not to cover the light receiving region.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: September 3, 2013
    Assignee: Sony Corporation
    Inventors: Shuji Yoneda, Masato Oishi, Tamotsu Shinohara, Shinji Watanabe, Koji Miyata, Seiji Fukae, Kenji Yamauchi, Yoichi Goto, Masakazu Baba
  • Patent number: 8525351
    Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 3, 2013
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Patent number: 8525306
    Abstract: To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yukinori Tashiro, Yoshinori Miyaki
  • Patent number: 8525355
    Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: September 3, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hidenori Takayanagi, Yukiharu Takeuchi, Hiroki Toyazaki, Toshio Gomyo
  • Publication number: 20130221544
    Abstract: A molding die for molding a substrate to be included in a microchip includes a first die and a second die contactable with and separable from the first die. A molding space for molding the substrate and a gate for introducing resin into the molding space are formed between the first die and the second die. A molding surface of the first die includes a first-die substrate molding region which molds the one surface of the substrate, a gate-defining region which defines the gate, and a rising region which is located between the gate-defining region and the first-die substrate molding region and extends from an edge of the first-die substrate molding region toward the second die. The gate-defining region is closer to the second die than the first-die substrate molding region. A microchip and a manufacturing apparatus also are provided.
    Type: Application
    Filed: October 25, 2011
    Publication date: August 29, 2013
    Applicant: Konica Minolta, Inc.
    Inventor: Kanji Sekihara
  • Patent number: 8519529
    Abstract: A semiconductor apparatus includes: a wiring board; a lid; and gap filling resin. A semiconductor chip is mounted on the wiring board. The lid includes inlet portions for injecting resin. The semiconductor chip is covered with the lid on the wiring board. The gap filling resin bonds the wiring board and the lid inside the lid.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: August 27, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Chiho Ogihara
  • Patent number: 8518747
    Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Swee Kwang Chua
  • Patent number: 8519519
    Abstract: A semiconductor device includes a lead frame that has a die interconnect portion and at least first and second die pads. The die interconnect portion is isolated from the die pads. The device also includes a first die and a second die attached to the first and second die pads and electrically connected to each other by way of the die interconnect portion. The first die is encapsulated in a first medium and the second die is encapsulated in a second medium, the first medium being different from the second medium.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: August 27, 2013
    Assignee: Freescale Semiconductor Inc.
    Inventors: Beng Siong Lee, Guat Kew Teh, Wai Keong Wong
  • Publication number: 20130214430
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; and forming an under-fill between the integrated circuit and the substrate having a cast side.
    Type: Application
    Filed: September 23, 2011
    Publication date: August 22, 2013
    Inventor: STATS ChipPac Ltd.
  • Publication number: 20130214434
    Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.
    Type: Application
    Filed: April 5, 2013
    Publication date: August 22, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Patent number: 8513542
    Abstract: An integrated circuit leaded stacked package system includes forming a no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: August 20, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Heap Hoe Kuan, Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano