Abstract: An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (412-414) of the leadframe; and (c) longitudinally injecting molding material into the cavities along the columns via a plurality of longitudinal gates (46-49, 56-59) of the leadframe to package the dice in the cavities, the longitudinal gates situated between the cavities along the columns.

Abstract: A semiconductor device includes a first substrate. The first substrate may be a wafer-level interposer or a die-level interposer. A portion of the first substrate is removed to form a beveled edge. The beveled edge may be formed during singulation of the first substrate. A second substrate is disposed over the first substrate. The beveled edge is oriented towards the second substrate. A semiconductor die is disposed over the second substrate. The first and second substrates are disposed within a cavity of a mold. An encapsulant is deposited within the cavity over a first surface of the first substrate between the first and second substrates. The beveled edge reduces encapsulant flow onto a second surface of the first substrate opposite the first surface. The second surface of the first substrate remains free from the encapsulant. The first substrate is singulated before or after the encapsulant is deposited.

Abstract: A thermosetting encapsulation adhesive sheet which is used for encapsulating a chip type device (1) having connection electrodes (bumps) (3) and mounted on a wiring circuit board (2). The thermosetting encapsulation adhesive sheet is composed of an epoxy resin composition having a viscosity of 5×104 to 5×106 Pa·s as measured at a temperature of 80 to 120° C. before thermosetting thereof. The thermosetting encapsulation adhesive sheet makes it possible to conveniently encapsulate a hollow device with an improved yield.

Abstract: An electrical component and a method for the manufacture thereof, comprising a connection arrangement between an active surface of an electrical component and a carrier, wherein electrical connecting elements are disposed in a connection zone on the active surface and/or on the carrier, and at least one spacer element is provided, which is disposed on the active surface and/or on the carrier. The at least one spacer element has a smaller height than the connecting elements before the connecting elements are reflowed to produce the electrically conductive connection, and is preferably disposed in an edge region of the connection zone.

Abstract: A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: The present invention generally relates to a MEMS device in which silicon residues from the adhesion promoter material are reduced or even eliminated from the cavity floor. The adhesion promoter is typically used to adhere sacrificial material to material above the substrate. The adhesion promoter is the removed along with then sacrificial material. However, the adhesion promoter leaves silicon based residues within the cavity upon removal. The inventors have discovered that the adhesion promoter can be removed from the cavity area prior to depositing the sacrificial material. The adhesion promoter which remains over the remainder of the substrate is sufficient to adhere the sacrificial material to the substrate without fear of the sacrificial material delaminating. Because no adhesion promoter is used in the cavity area of the device, no silicon residues will be present within the cavity after the switching element of the MEMS device is freed.

Abstract: A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: A semiconductor module is provided which is well protected against corrosion and/or other damage which can be caused by moisture and/or other harmful substances surrounding the semiconductor module. A method for producing such a semiconductor module is also provided.

Abstract: A silicone resin is provided. The silicone resin may be effectively used to encapsulate a semiconductor element, for example, a light-emitting element of a light-emitting diode.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus.

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.

Abstract: A novel die seal design, and method for utilization thereof, controls contact of a mold material with the surfaces of a semiconductor die during application, reducing stresses due to a mismatch of the coefficient of thermal expansion of the mold material and the semiconductor die, thereby reducing cracking of the semiconductor die, resulting in increased yields and lower costs, and permits reuse of elements of a mold tool over a range of die sizes.

Abstract: A method for forming a nanofluidic channel measuring system is disclosed. The method includes forming a first trench in a substrate, forming a second trench in the substrate, the first trench and the second trench are separated by a first width, providing a first conductor pad at a first location, providing a second conductor pad at a second location, forming a first nano-wire for coupling the first conductor pad with the second conductor pad, and forming a nano-channel through the first nano-wire, the nano-channel also coupling the first trench and the second trench, the nano-channel configured to sever the first nano-wire. A nanofluidic channel measuring system is also disclosed.

Abstract: A method for manufacturing an underfill in a semiconductor chip stack having a cavity between a first surface and a second surface includes providing at least one access hole in one of the first or second surface; providing at least one vent hole in the one of the first or second surfaces; and applying a viscous filling material through the at least one access hole into the cavity thereby squeezing out air or gas through the at least one vent hole.

Abstract: A method for producing an encapsulating layer-covered semiconductor element includes the steps of preparing a support sheet including a hard support board formed with a through hole passing through in a thickness direction and a pressure-sensitive adhesive layer laminated on a surface at one side in the thickness direction of the support board so as to cover the through hole; disposing a semiconductor element on a surface at one side in the thickness direction of the pressure-sensitive adhesive layer in opposed to the through hole in the thickness direction; covering the semiconductor element with an encapsulating layer to produce an encapsulating layer-covered semiconductor element; and inserting a pressing member into the through hole from the other side in the thickness direction to peel the encapsulating layer-covered semiconductor element from the pressure-sensitive adhesive layer.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer.

Abstract: A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.

Abstract: A semiconductor device has a substrate with a cavity. A conductive layer is formed within the cavity and over the substrate outside the cavity. A plurality of indentations can be formed in a surface of the substrate opposite the cavity for stress relief. A first semiconductor die is mounted within the cavity. A plurality of conductive vias can be formed through the first semiconductor die. An insulating layer is disposed between the first semiconductor die and substrate with the first conductive layer embedded within the first insulating layer. An encapsulant is deposited over the first semiconductor die and substrate. An interconnect structure is formed over the encapsulant. The interconnect structure is electrically connected to the first semiconductor die and first conductive layer. The substrate is removed to expose the first conductive layer. A second semiconductor die is mounted to the conductive layer over the first semiconductor die.

Abstract: Silicon-based circuitry is dissolved or otherwise disabled in a controlled manner by reactive materials provided beneath the insulating layer on which the circuitry is formed. Heat and/or light induced acid generating materials are provided for corroding one or more circuitry components. Additionally and/or alternatively, gas-producing materials are deposited in compartments beneath the insulating layer. The gas-producing materials cause pressure to rise within the compartments, damaging the chip. Chemical reactions within the chip may be facilitated by heating elements and/or light generating elements embedded within the chip and actuated by triggering circuits.

Abstract: A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device.

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Abstract: Devices, components and methods containing one or more light emitter devices, such as light emitting diodes (LEDs) or LED chips, are disclosed. In one aspect, a light emitter device component can include a ceramic body having a top surface, one or more light emitter devices mounted directly or indirectly on the top surface, and one or more electrical components mounted on the top surface and electrically coupled to the one or more light emitter devices, wherein the one or more electrical components can be spaced from the ceramic body by one or more non-metallic layers. Components disclosed herein can result in improved light extraction and thermal management.

Abstract: The present invention provides a sealing material for a solar cell that seals a solar cell element of a solar cell in a short time in the production of a solar cell module, thereby enabling efficient production of solar cell modules. The sealing material for a solar cell of the present invention has a feature of containing 100 parts by weight of a modified butene-based resin that is produced by graft-modifying a butene-ethylene copolymer having a butene content of 1 to 25% by weight with maleic anhydride and has a total content of the maleic anhydride of 0.1 to 3% by weight, and 0.1 to 15 parts by weight of a silane compound having an epoxy group.

Abstract: A semiconductor device manufacturing method includes sealing a first surface of a semiconductor wafer with a resin, causing a resin-made warp suppression member to be adhered to a second surface on the opposite side of the first surface of the semiconductor wafer and causing the warp suppression member to shrink, measuring the amount of warp of the semiconductor wafer, and forming cuts in the warp suppression member in accordance with the amount of warp of the semiconductor wafer.

Abstract: A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.

Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Abstract: A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.

Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer.

Abstract: The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.

Abstract: A method (and apparatus) of assembling a die on an electronic substrate, includes processing an assembly including a substrate and a die, and during the processing, introducing a pre-stress to the assembly during a cure process.

Abstract: A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer.

Abstract: A wiring board of this invention includes a product formation area in which are arranged a plurality of product formation sections on which a semiconductor chip is mounted; a molding area that is provided on an outer circumferential side of the product formation area, and with which a seal portion that covers the semiconductor chips mounted on the product formation sections makes contact; a clamp area that is provided on an outer circumferential side of the molding area, and that is held by a molding die that forms the seal portion; wiring that is provided in the product formation area, and that is electrically connected to the semiconductor chips; a first solid pattern that is provided in the molding area, and in which a plurality of dots are arranged; and a second solid pattern that is provided in the clamp area, and in which a plurality of dots that are larger than the dots of the first solid pattern are arranged.

Abstract: Described herein is a sealant laminated composite for collectively sealing a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed. The composite can include a support wafer and an uncured resin layer constituted of an uncured thermosetting resin formed on one side of the support wafer. In certain aspects, the sealant laminated composite is very versatile, even when a large diameter or thin substrate or wafer is sealed.

Abstract: It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment.

Abstract: An anisotropic conductive film composition for bonding a semiconductor device, the composition including: a binder system including a urethane resin having a glass transition temperature of about 100° C. or higher, a radical polymerizable compound, an organic peroxide, and conductive particles.

Abstract: An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.

Abstract: In at least one embodiment of the component (10) the latter comprises a first substrate (1) and a second substrate (2), at least one radiation-emitting or radiation-receiving element (3) being arranged on the first substrate (1), which element contains at least one organic material. The first substrate (1) and the second substrate (2) are arranged relative to one another such that the element (3) is located between the first substrate (1) and second substrate (2). The first substrate (1) and second substrate (2) are bonded together mechanically by means of a bonding agent (4) arranged in a sheet between the first substrate (1) and the second substrate (2), which bonding agent contains a glass and surrounds the element (3) with the organic material in the manner of a frame.

Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

Abstract: A semiconductor device has a wiring substrate, a first semiconductor chip, a second semiconductor chip, and a sealing member. The second semiconductor chip has a chip-layered structure with a plurality of semiconductor chip components stacked in the height direction of the semiconductor device. The first semiconductor chip has an upper surface located at the same height from a surface of the wiring substrate as an upper surface of the second semiconductor chip.

Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

Abstract: An IC package that is suitable for surface mounting arrangements includes a heat spreader device that is coupled to a bottom portion of the package below the IC die. Coupling the heat spreader device to the bottom portion of the package reduces or eliminates the possibility that placement of the heat spreader device will result in the molding compound bleeding on top of the heat spreader device, and delamination at the footings of the heat spreader device that can cause the package to delaminate, or “popcorn”.

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.

Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.